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L64105 MPEG-2 Audio/Video Decoder Technical Manual
This document contains proprietary information Logic Corporation. information contained herein used disclosed third parties without express written permission officer Logic Corporation. Document DB14-000041-00, First Edition (July 1998) This document describes revision Logic Corporation's L64105 MPEG-2 Audio/Video Decoder will remain official reference source revisions/releases this product until rescinded update. receive product literature, call 1.800.574.4286 (U.S. Canada); +32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, Europe) Department JDS; visit http://www.lsilogic.com. Logic Corporation reserves right make changes products herein time without notice. Logic does assume responsibility liability arising application product described herein, except expressly agreed writing Logic; does purchase product from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties. particular, supply Logic L64105 does convey license imply right under certain patents and/or other industrial intellectual property rights claimed IRT, CCETT Philips, this ready-to-use electronic product. purchaser hereby notified that Philips, CCETT opinion that generally available patent license such required from them. warranty indemnity sort provided Logic regarding patent infringement. Copyright 1997, 1998 Logic Corporation. rights reserved. TRADEMARK ACKNOWLEDGMENT Logic logo design registered trademarks Logic Corporation. other brand product names trademarks their respective companies.
Contents
Preface Chapter Introduction L64105 Application L64105 Overview 1.2.1 Memory Utilization 1.2.2 Error Concealment Features Signal Descriptions Signals Organization Host Interface Channel Interface Memory Interface Video Interface Audio Interface Miscellaneous Test Interfaces Register Summary Summary Register Alphabetical Listing Register Descriptions Host Interface Registers Video Decoder Registers Memory Interface Registers Microcontroller Registers
Chapter
2-11
Chapter
3-30
Chapter
4-17 4-38 4-48
Contents
Chapter Host
Video Interface Registers Audio Decoder Registers Test Registers Interface Overview Interface Signals Register Access Functions 5.3.1 General Functions 5.3.2 Registers 5.3.3 Interrupt Registers SDRAM Access 5.4.1 Host Reads/Writes 5.4.2 Host SDRAM Transfers 5.4.3 SDRAM Block Move
4-58 4-72 4-91
5-10 5-10 5-14 5-18
Chapter
Channel Interface Overview Interface Signals Operation 6.2.1 Asynchronous Mode 6.2.2 Synchronous VALIDn Inputs 6.2.3 Synchronous A/VREQn Outputs 6.2.4 Channel Bypass Mode 6.2.5 Channel Pause Preparser 6.3.1 Host Selection Streams Headers 6.3.2 Elementary Streams 6.3.3 Packet Structure 6.3.4 Preparsing MPEG-1 System Stream 6.3.5 Preparsing Program Stream 6.3.6 Error Handling Program Streams 6.3.7 Preparsing Packets from Transport Stream 6.3.8 Error Handling Mode Channel Buffer Controller 6.4.1 Buffer Reset
6-12 6-14 6-16 6-18 6-21 6-24 6-25 6-27 6-28
Contents
6.4.2 Chapter
Detecting Potential Underflow Conditions Video Channel Summary
6-29 6-30
Memory Interface Overview SDRAM Configurations SDRAM Timing Modes SDRAM Refresh Arbitration Memory Channel Buffer Allocation Memory Frame Store Allocation 7.6.1 Luma Store 7.6.2 Chroma Store 7.6.3 Normal Mode 7.6.4 Reduced Memory Mode (RMM) Summary Video Decoder Module Overview Postparser Operation 8.2.1 Sequence Header 8.2.2 Sequence Extension 8.2.3 Sequence Display Extension 8.2.4 Group Pictures Header 8.2.5 Picture Header 8.2.6 Picture Coding Extension 8.2.7 Quant Matrix Extension 8.2.8 Host Access Table Entries 8.2.9 Picture Display Extension 8.2.10 Copyright Extension 8.2.11 User Data 8.2.12 Picture Data 8.2.13 Unsupported Syntax 8.2.14 Auxiliary Data FIFO Operation 8.2.15 User Data FIFO Operation
7-10 7-11 7-12
Chapter
8-11 8-13 8-14 8-15 8-17 8-18 8-18 8-18 8-19 8-21
Contents
Video Decoder Pacing 8.3.1 Channel Start/Reset Status Bits 8.3.2 Video Decoder Start/Stop Frame Store Modes 8.4.1 Normal (3-Frame Store) Mode 8.4.2 Reduced Memory Mode 8.4.3 Two-Frame Store Mode 8.4.4 Decode Display Frame Store Status Indicators Trick Modes 8.5.1 Skip Frame 8.5.2 Repeat Frame 8.5.3 Channel Buffer Underflow Panic Repeat 8.5.4 Forward Mode 8.5.5 Force Broken Link 8.5.6 Search Next GOP/Seq Command 8.5.7 Reconstruction Force Rate Control 8.5.8 Sequence Processing Error Handling Concealment 8.6.1 Error Conditions Detected 8.6.2 Recovery Mechanisms
8-24 8-25 8-26 8-30 8-30 8-32 8-34 8-34 8-35 8-35 8-38 8-40 8-40 8-43 8-43 8-43 8-46 8-48 8-49 8-49
Chapter
Video Interface Overview Television Standard Select Display Areas 9.3.1 Vertical Timing 9.3.2 Horizontal Timing Video Background Modes Still Image Display Display Modes Vertical Filtering Reduced Memory Mode Horizontal Postprocessing Filters On-Screen Display 9.9.1 Modes 9.9.2 Internal 9.9.3 External
9-10 9-12 9-13 9-16 9-19 9-20 9-23 9-24 9-24 9-31
Contents
9.10
9.11 9.12 9.13 9.14 Chapter
Scan Operation 9.10.1 Host Controlled Scan 9.10.2 Bitstream Controlled Scan 9.10.3 Vertical Scan Display Freeze Pulldown Operation Video Output Format Timing Display Controller Interrupts
9-32 9-33 9-35 9-35 9-36 9-38 9-39 9-40
Audio Decoder Module 10.1 Features 10.2 Audio Decoder Overview 10.3 Decoding Flow Control 10.3.1 Audio Decoder Play Mode 10.3.2 Audio Decoder Start/Stop 10.3.3 Audio Formatter Play Mode 10.3.4 Audio Formatter Start/Stop 10.3.5 Autostart 10.4 MPEG Audio Decoder 10.4.1 MPEG Audio Syntax 10.4.2 MPEG Audio Decoding 10.5 Linear Audio Decoder 10.5.1 Packet Header Syntax 10.5.2 Synchronization 10.5.3 Other Host Controls Status 10.5.4 Sample Decimation 10.6 MPEG Formatter 10.6.1 Number IEC958 Frames when Formatting MPEG Data 10.6.2 Field 10.6.3 Pause Burst 10.6.4 Synchronization 10.6.5 Error Conditions 10.7 FIFO Mode 10.8 Interface
10-1 10-2 10-6 10-6 10-7 10-8 10-8 10-9 10-10 10-10 10-12 10-14 10-14 10-16 10-18 10-18 10-19 10-21 10-21 10-22 10-24 10-24 10-26 10-27
Contents
Interface 10.9.1 Biphase Mark Coding 10.9.2 IEC958 Syntax 10.9.3 IEC958 Channel Status 10.10 Clock Divider Chapter Specifications 11.1 Electrical Requirements 11.2 Timing 11.3 Pinouts Packaging Video/Audio Compression Decompression Concepts Video Compression Decompression Concepts A.1.1 Video Encoding A.1.2 Bitstream Syntax A.1.3 Video Decoding Audio Compression Decompression Concepts A.2.1 MPEG Audio Encoding A.2.2 Audio Decoding Glossary Terms Abbreviations Index Customer Feedback Figures Typical L64105 Application L64105 Decoder Block Diagram L64105 Signals PLLVDD Decoupling Circuit Register (0x000) Register (0x001) Register (0x002) Register (0x003)
10.9
10-29 10-30 10-30 10-32 10-32
11-1 11-4 11-18
Appendix
A-11
Appendix
2-11
viii
Contents
4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29
4.30 4.31
Register (0x004) Register (0x005) Register (0x006) Register (0x007) Registers 9-12 (0x009-0x00C) Value [31:0] Registers 13-16 (0x00D-0x010) Compare/Capture [31:0] Register (0x011) Register (0x012) Register (0x013) Registers 20-23 (0x014-0x017) Compare Audio [31:0] Register (0x01C) Video Channel Bypass Data [7:0] Register (0x01D) Audio Channel Bypass Data [7:0] Register (0x040) Register (0x41) Register (0x042) User Data FIFO Output [7:0] Register (0x043) Data FIFO Output [7:0] Register (0x044) Register (0x045) Registers (0x048 0x049) Video Channel Buffer Start Address [13:0] Registers (0x04A 0x04B) Video Channel Buffer Address [13:0] Registers (0x04C 0x04D) Audio Channel Buffer Start Address [13:0] Registers (0x04E 0x04F) Audio Channel Buffer Address [13:0] Registers (0x050 0x051) Video Header Channel Buffer Start Address [13:0] Registers (0x052 0x053) Video Header Channel Buffer Address [13:0] Registers (0x058 0x059) Audio Header/System Channel Buffer Start Address [13:0] Registers (0x05A 0x05B) Audio Header/System Channel Buffer Address [13:0] Registers 96-98 (0x060-0x062) Video Channel Buffer Write Address [19:0]
4-10 4-11 4-13 4-13 4-14 4-15 4-15 4-16 4-16 4-17 4-17 4-18 4-19 4-19 4-20 4-21 4-22 4-23 4-23 4-24 4-24 4-24
4-25 4-25 4-26
Contents
4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49 4.50 4.51 4.52 4.53 4.54 4.55
Registers 99-101 (0x063-0x065) Audio Channel Buffer Write Address [19:0] Registers 102-104 (0x066-0x068) Video Header Channel Buffer Write Address [19:0] Registers 108-110 (0x06C-0x06E) Video Channel Buffer Read Address [19:0] Registers 108-110 (0x06C-0x06E) Video Channel Buffer Compare Address [18:0] Registers 111-113 (0x06F-0x071) Audio Channel Buffer Read Address [19:0] Registers 111-113 (0x06F-0x071) Audio Channel Buffer Compare Address [18:0] Registers 114-116 (0x072-0x074) Audio Header/System Channel Buffer Write Address [19:0] Registers 120-122 (0x078-0x07A) Channel Buffer Read Address [19:0] Register (0x07C) Registers 128-130 (0x080-0x082) Picture Start Code Read Address [19:0] Registers 131-133 (0x083-0x085) Audio Sync Code Read Address [19:0] Registers 134-136 (0x086-0x088) Video Channel Buffer Numitems [18:0] Registers 134-136 (0x086-0x088) Video Numitems/Pics Channel Compare Panic [18:0] Registers 137-139 (0x089-0x08B) Audio Channel Buffer Numitems [18:0] Registers 140-142 (0x08C-0x08E) Channel Buffer Numitems [18:0] Register (0x08F) Register (0x090) Register (0x091) Register (0x093) Register (0x094) Registers (0x096 0x097) Pictures Video Channel Buffer Counter [15:0] Register (0x0C0) Register (0x0C1) Register (0x0C2) Host SDRAM Read Data [7:0]
4-26 4-27 4-27 4-28 4-28 4-29 4-29 4-30 4-30 4-31 4-31 4-32 4-32 4-33 4-33 4-34 4-35 4-35 4-36 4-37 4-38 4-38 4-39 4-41
Contents
4.56 4.57 4.58 4.59 4.60 4.61 4.62 4.63 4.64 4.65 4.66 4.67 4.68 4.69 4.70 4.71 4.72 4.73 4.74 4.75 4.76 4.77 4.78 4.79 4.80 4.81 4.82
Register (0x0C3) Host SDRAM Write Data [7:0] Registers 196-198 (0x0C4-0x0C6) Host SDRAM Target Address [18:0] Registers 199-201 (0x0C7-0x0C9) Host SDRAM Source Address [18:0] Registers (0x0CA 0x0CB) Block Transfer Count [15:0] Register (0x0CC) Register (0x0CD) Register (0x0CE) Registers 207-212 (0x0CF-0x0D4) Registers 213-215 (0xD5-0x0D7) SDRAM Target Address [18:0] Registers 216-218 (0xD8-0x0DA) SDRAM Source Address [18:0] Register (0x0DB) SDRAM Read Data [7:0] Register (0x0DC) SDRAM Write Data [7:0] Register (0x0DD) Registers (0x0DE 0x0DF) Test Freq [15:8] Registers (0x0E0 0x0E1) Anchor Luma Frame Store Base Address [15:0] Registers (0x0E2 0x0E3) Anchor Chroma Frame Store Base Address [15:0] Registers (0x0E4 0x0E5) Anchor Luma Frame Store Base Address [15:0] Registers (0x0E6 0x0E7) Anchor Chroma Frame Store Base Address [15:0] Registers (0x0E8 0x0E9) Luma Frame Store Base Address [15:0] Registers (0x0EA 0x0EB) Chroma Frame Store Base Address [15:0] Register (0x0EC) Register (0x0ED) Register (0x0EE) Register (0x0EF) Register (0x0F0) Register (0x0F1) Register (0x0F2) Table Entry [7:0]
4-41 4-42 4-42 4-43 4-43 4-44 4-45 4-45 4-46 4-46 4-47 4-47 4-47 4-47 4-48 4-48 4-48 4-49 4-49 4-49 4-50 4-51 4-52 4-54 4-56 4-56 4-57
Contents
4.83 4.84 4.85 4.86 4.87 4.88 4.89 4.90 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 4.100 4.101 4.102 4.103 4.104 4.105 4.106 4.107 4.108 4.109 4.110
Register (0x0F3 0x0F4) Microcontroller [11:0] Register (0x0F5) Revision Number [7:0] Register (0x0F6) Register (0x0F8) Reduced Memory Mode (RMM) Register (0x109) Registers 266-268 (0x10A 0x10C) Programmable Background Y/Cb/Cr [7:0] Register (0x10D) Palette Write [7:0] Registers 270-273 (0x10E-0x111) Odd/Even Field Pointers [15:0] Register (0x112) Register (0x113) Register (0x114) Register (0x115) Horizontal Filter Scale [7:0] Register (0x116) Register (0x117) Register (0x118) Horizontal Scan Luma/Chroma Word Offset [7:0] Register (0x119) Vertical Scan Line Offset [7:0] Register (0x11A) Register (0x11B) Register (0x11C) Registers 285-288 (0x11D-0x120) Display Override Luma/Chroma Frame Store Start Addresses [15:0] Register (0x121) Register (0x122) Registers 297-299 (0x129-0x12B) Main Start/End Rows [10:0] Registers 300-302 (0x12C-0x12E) Main Start/End Columns [10:0] Register (0x12F) Register (0x130) Vcode Even [7:0] Register (0x131) Fcode [7:0] Registers 306-308 (0x132-0x134) SAV/EAV Start Columns [10:0]
4-57 4-57 4-57 4-58 4-58 4-60 4-60 4-61 4-61 4-62 4-63 4-64 4-65 4-65 4-66 4-66 4-66 4-67 4-67 4-68 4-68 4-69 4-70 4-70 4-70 4-71 4-71 4-72
Contents
4.111 4.112 4.113 4.114 4.115 4.116 4.117 4.118 4.119 4.120 4.121 4.122 4.123 4.124 4.125 4.126 4.127 4.128 4.129 4.130 4.131 4.132 4.133
Register (0x135) Register (0x150) Register (0x151) Register (0x152) Register (0x15F) Register (0x160) Register (0x161) Register (0x162) Register (0x163) Register (0x164) Register (0x165) Register (0x166) Register (0x167) FIFO Data [7:0] Register (0x168) Linear dynscalehigh [7:0] Register (0x169) Linear dynscalelow [7:0] Register (0x16A) Scale [7:0] Register (0x16B) Register (0x16C) Register (0x16D) Register (0x16E) Register (0x16F) Host Category [7:0] Register (0x170) Registers (0x171 0x172) Host Value [15:0] 4.134 Registers (0x180 0x181) Memory Test Address [11:0] 4.135 Register (0x182) 4.136 Registers 387-392 (0x183-0x188) Memory Test Pass/Fail Status Bits Host Interface Block Diagram Motorola Mode Write Timing Motorola Mode Read Timing Intel Mode Write Timing Intel Mode Read Timing Operation Counter Interrupt Structure Host Read/Write Flowchart SDRAM Read/Write Flowchart
4-72 4-72 4-74 4-76 4-77 4-77 4-77 4-78 4-79 4-80 4-81 4-82 4-83 4-83 4-83 4-84 4-84 4-85 4-87 4-88 4-89 4-90 4-91 4-91 4-91 4-93 5-13 5-17
Contents
xiii
5.10 6.10 6.11 6.12 6.13 6.14 6.15 6.16 8.10
Block Move Flowchart Channel Interface Block Diagram Asynchronous Channel Interface Timing xVALIDn Input Synchronization Circuits Synchronous Valid Signals Timing L64105 A/VREQn Circuits Elementary Stream Buffering Packet Structure Preparsing MPEG-1 System Stream System Channel Buffer MPEG-1 Streams System Channel Buffer Program Streams Audio Channel Buffer Linear Audio Audio Channel Buffer MPEG Audio Video Channel Buffer Parsing Audio/Video Transport Stream MPEG-1/MPEG-2 Channel Interface Operation Mode Channel Interface Operation Memory Interface Block Diagram SDRAM Timing Requirements Reads SDRAM Timing Requirements Writes SDRAM Timing Requirements Refresh Luma Frame Store Organization Chroma Frame Store Organization Video Decoder Block Diagram Time Line Frame Picture Time Line Field Picture Frame Store Organization Normal Mode Single Skip with without Display Freeze Frame Repeat Modes Setting Forward/Display Override Command Automatic Rate Control Using Force Rate Control Forward Mode Example Sequence Processing Video Interface Block Diagram Display Areas Example Vertical Timing Vcodes Fcodes NTSC Vertical Timing Vcodes Fcodes Sync Input Timing
5-19 6-13 6-15 6-16 6-17 6-19 6-20 6-21 6-21 6-24 6-30 6-31 7-10 8-28 8-29 8-31 8-37 8-39 8-42 8-45 8-46 8-47 9-10
Contents
9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8
Horizontal Input Timing Horizontal Timing 8-Bit Digital Transmission NTSC Luma Chroma Frame Store Format Frequency Response Impulse Response Frequency Response Impulse Response Area Data Organization Header Control Fields Header Color Fields Storage Formats Horizontal Scan Calculation Freeze Operation Timing Pulldown Operation Timing Video Control Output Timing L64105 Audio Decoder Block Diagram MPEG Audio Bitstream Syntax MPEG Audio Decoding Flow Linear Packet Syntax Linear Audio Sample Syntax Linear Output Ports Syntax MPEG Data IEC958 Format Length Burst Payload Inserting Pause Bursts MPEG Formatter Output Output Mode: Sample Precision Output Mode: Sample Precision Output Mode: Sample Precision IEC958 Biphase Mark Representation IEC958 Syntax IEC958 Channel Status Test Load Waveform Standard Outputs Test Load Waveform 3-State Outputs SDRAM Read Cycle SDRAM Write Cycle Host Write Timing (Motorola Mode) Host Read Timing (Motorola Mode) Host Write Timing (Intel Mode) Host Read Timing (Intel Mode)
9-11 9-12 9-14 9-21 9-21 9-22 9-22 9-25 9-26 9-27 9-29 9-35 9-37 9-39 9-40 10-4 10-11 10-13 10-14 10-16 10-19 10-20 10-21 10-23 10-27 10-28 10-28 10-30 10-31 10-32 11-4 11-5 11-7 11-8 11-10 11-11 11-13 11-13
Contents
11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17 Tables
Asynchronous Channel Write Timing Synchronous AVALIDn/VVALIDn Signals Timing Reset Timing Video Interface Timing Serial Data Timing A_ACLK Timing PREQn Timing 160-Pin Package Pinout 160-Pin PQFP (PZ) Mechanical Drawing (Sheet MPEG Macroblock Structure Typical Sequence Pictures Display Order Typical Sequence Pictures Bitstream Order Audio Encoding Process (Simplified) System Stream MPEG Audio Packet Structure
11-14 11-15 11-15 11-16 11-17 11-17 11-18 11-25 11-26
L64105 Register Groupings Host Interface Registers Video Decoder Registers Memory Interface Registers Microcontroller Registers Video Interface Registers Audio Decoder Registers Test Registers Display Mode Selection Table MPEG Bitrate Index Table Audio Decoder Modes ACLK Divider Select [3:0] Code Definitions Host Interface Signals Compare/Capture Mode Bits Mode Bits Levels Hierarchy MPEG-1 MPEG-2 System Syntax Video Stream Select Enable Bits Audio Stream Select Enable Bits Pack Header Enable Bits
3-14 3-17 3-20 3-24 3-27 4-64 4-73 4-81 4-86 5-14 6-10 6-11
Contents
6.10 6.11 6.12 6.13 6.14 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20
System Header Enable Bits Video Header Enable Bits Audio Header Enable Bits Buffer Start Address Registers Mode Buffer Write Read Pointer Registers Mode Number Items Buffers Mode SDRAM Addresses Audio Header/System Channel Buffer Video Header Channel Buffer Registers Compare Register Bits Fields Video Channel Underflow Control Registers NEC's Mbit Synchronous DRAM (Burst Length Example NTSC SDRAM Allocation Channel Buffer Architectures Example NTSC SDRAM Allocation with Frame Store (720 480) Sequence Header Processing Sequence Extension Processing Sequence Display Extension Processing Group Pictures Header Processing Picture Header Processing Picture Coding Extension Processing Quant Matrix Extension Processing Picture Display Extension Processing Number Frame Center Offsets Copyright Extension Processing User Data Processing Data FIFO Registers Data FIFO Status Auxiliary Data Layer Assignments User Data FIFO Registers User Data FIFO Status User Data Layer Assignments Frame Store Base Address Registers Current Decode/Display Frame Bits Coding Video Skip Frame Modes Television Standard Select Field Television Standard Select Default Values
6-11 6-12 6-12 6-13 6-14 6-14 6-18 6-25 6-28 6-29 7-12 8-11 8-13 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-22 8-24 8-32 8-34 8-35
Contents
xvii
9.10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12
Force Video Background Selections Override Display Registers Display Mode Selection Table Raster Mapper Increment Value Source Resolution Modes High Color Modes Host Controlled Scan Registers Freeze Modes Audio Decoder Modes Audio Autostart Registers Valid Linear Stream Permutations MPEG Formatter Data Burst Preamble Syntax IEC958 Frame Sizes Supported MPEG Audio Formatter Selection MPEG Formatter Pause Burst Syntax MPEG Audio Formatter Error Handling FIFO Mode Registers IEC958 Subframe Preambles ACLK Divider Select [3:0] Code Definitions Absolute Maximum Ratings Recommended Operating Conditions Capacitance Characteristics SDRAM Interface Timing Host Interface Timing (Motorola Mode) Host Interface Timing (Intel Mode) Asynchronous Channel Write Timing Synchronous AVALIDn/VVALIDn Signals Timing Video Interface Timing Audio Interface Timing Alphabetical Summary MPEG Compressed Bitstream Syntax
9-12 9-14 9-17 9-23 9-24 9-26 9-33 9-36 10-3 10-9 10-15 10-20 10-21 10-22 10-23 10-25 10-26 10-31 10-34 11-2 11-2 11-2 11-3 11-6 11-9 11-12 11-14 11-14 11-16 11-17 11-18
xviii
Contents
Preface
This book primary reference Technical Manual L64105 MPEG-2 Audio/Video Decoder. contains functional descriptions, signal register descriptions, includes complete physical electrical specifications L64105.
Audience This document assumes that have some familiarity with ISO/IEC 13818, Generic Coding Moving Pictures Associated Audio (MPEG-2), microprocessors, related support devices. people benefit from this book are:
Engineers managers evaluating L64105 possible
system
Engineers designing L64105 into system
Organization This document following chapters appendixes:
Chapter Introduction includes overview L64105
Decoder lists features.
Chapter Signal Descriptions describes input/output
signals L64105.
Chapter Register Summary summarizes registers
L64105 tabular form with page references their descriptions Chapter
Chapter Register Descriptions identifies describes
register bits fields L64105 accessible from host processor.
Preface
Chapter Host Interface describes host interface L64105
external SDRAM connected L64105.
Chapter Channel Interface describes processing
audio/video bitstream comes into L64105 various methods which L64105 uses handle recover from input stream errors.
Chapter Memory Interface describes SDRAM configurations
required L64105 interface those memories.
Chapter Video Decoder Module describes video
decoder portion L64105 supports MPEG-2 Main Profile Main Level decoding MPEG-1 Simple Profile Main Level decoding.
Chapter Video Interface describes video displayed from
decoded frame stores. Also describes features operation Display Controller program proper operation. Includes overview vertical horizontal post-processing filters.
Chapter Audio Decoder Module describes L64105
processes Linear MPEG (MUSICAM) input audio streams.
Chapter Specifications includes electrical requirements for,
timing characteristics summary L64105. Also contains listing package outline drawing 160-pin PQFP.
Appendix Video/Audio Compression Decompression
Concepts
Appendix Glossary Terms Abbreviations
Related Publications
L64108 MPEG-2 Transport with Embedded MIPS (CW4001) Control Chip Technical Manual, Logic Corporation, DB14-000039-00.
ISO/IEC 13818, Generic Coding Moving Pictures Associated Audio (MPEG-2), International Standard. ISO/IEC Copyright Office, Case Postal CH1211 Switzerland. ISO/IEC 11172 (1993), Information Technology-Coding Moving Picture Associated Audio Digital Storage Media about
Preface
Mbit/s (MPEG-1), International Standard. ISO/IEC Copyright Office, Case Postal CH1211 Switzerland. ITU-R BT.601-5 (10/95), Studio Encoding Parameters Digital Television Standard Wide-screen 16:9 Aspect Ratios, ITU-R BT.656-3 (10/95), Interface Digital Component Video Signals 525-line 625-line Television Systems Operating 4:2:2 Level Recommendation ITU-R BT.601 (Part
Conventions Used This Manual Unless otherwise specified, MPEG refers MPEG-2 standard.
indicates most-significant byte. indicates leastsignificant byte. byte obvious context, term spelled out.
first time word phrase defined this manual, italicized. word means change logic state. word clear means change logic state. word assert means drive signal true active. word deassert means drive signal false inactive. Signals that active "n." Hexadecimal numbers indicated prefix "0x" before number-for example, 0x32CF. Binary numbers indicated prefix "0b" before number-for example, 0b0011.0010.1100.1111.
Preface
xxii
Preface
Chapter Introduction
This chapter provides general overview information L64105 MPEG-2 Audio/Video Decoder chip. chapter contains following sections:
Section 1.1, L64105 Application," page Section 1.2, "L64105 Overview," page Section 1.3, "Features," page
L64105 Application
Figure illustrates L64105 typical application. L64105 specifically designed digital audio video MPEG-2 decoding systems based MPEG-2 algorithm. device considered "black box" that receives coded audio video data produces decoded audio video data streams. Logic optimized L64105 input/output interfaces low-cost integration into embedded applications. L64105 member family software compatible, advanced, MPEG-2 decoders. L64020 Audio/Video Decoder adds Dolby Digital audio decoding features.
Figure
Typical L64105 Application
L64X08 EBUS
Satellite
L647X4 QPSK Demod
L64X08 Integrated X-PORT
L64105 MPEG-2 Decoder
NTSC/PAL Encoder Audio DACs
Baseband Video Stereo Audio
Cable L64768 Demod
Mbit DRAM
Mbit SDRAM
Optional Mbit SDRAM
L64105 accepts 8-bit, parallel channel input from transport demultiplexer and, with interaction host microcontroller, decompresses decodes channel information into separate, serial video audio streams. L64105 handles NTSC formats provides Sony/Philips Digital Interface (S/P DIF) formatted output stream.
L64105 Overview
Figure shows block diagram L64105. major blocks include the:
Host Interface Channel Interface Memory Interface Video Decoder Video Interface Audio Decoder
Host Interface includes 512, 8-bit registers (some used), read write FIFOs, byte enable logic. host L64105 communicate with each other exclusively through registers. external interrupt signal from L64105 alerts host about internal events, such picture start code detection. Separate signals used handshaking. L64105 interface with either Intel Motorola type processor tying external high low.
Introduction
Figure
L64105 Decoder Block Diagram
L64105 Decoder CH_DATA[7:0] Channel Interface Microcontroller Video Decoder Video Interface Video NTSC/PAL Encoder Control
MHz)
Data Address Buses Status Control
Host Interface
64-bit
Data Audio Clocks Oversampling Clock
Address Memory Interface
SYSCLK MHz)
Audio Decoder
SDRAM Buffers Frame Stores
read write FIFOs used give host access external SDRAM. read/write paths still through registers. interface supports direct read/write, transfers using external controller, block moves within SDRAM. byte enable logic converts host byte writes 8-byte words write FIFO 64-bit internal vice versa. byte enable logic also performs byte switching little endian hosts. Channel Interface accepts byte-wide MPEG streams clock. interface synchronizes preparses incoming stream stripping system headers storing them dedicated buffer area SDRAM. interface also separates audio video streams stores them dedicated buffer areas SDRAM. buffer controller maintains read write pointers dedicated buffers. Memory Interface includes byte enable logic address converter. recommended SDRAM bits wide, byte enable logic performs conversion between SDRAM 8-byte wide internal L64105. host internal microcontroller
L64105 Overview
L64105 address SDRAM were 8-byte wide RAM. address converter changes these addresses chip selects, bank selects, column addresses SDRAM. Video Decoder reads MPEG video elementary stream from SDRAM buffer, performs postparsing decompresses decodes stores back SDRAM. postparser strips header information stores internal memory decoding process. postparser also strips auxiliary user data from stream stores FIFOs that read through registers host. decompressed decoded video stored back SDRAM frame form. Video Interface reads video frames from frame stores SDRAM, synchronizes them vertical horizontal sync signals from NTSC/PAL Encoder, mixes On-Screen Display (OSD) information. interface performs letterboxing, pulldown, scan. also handles trick modes such pause, slow play, fast forward, etc. Audio Decoder contains MPEG (Musicam) Decoder, Linear Decoder, MPEG Formatter, Audio Interface, (IEC958) Interface. decoders decompress decode audio stream. decoder outputs steered Interface. formatter converts encoded compressed streams format Interface. host controls mode Audio Decoder; that determines which decoder runs where output goes, which formatter runs. host also place Audio Decoder bypass mode connect inputs from another device directly L64105 audio outputs. microcontroller shown block diagram since controls most processes L64105.
Introduction
L64105 MPEG-2 Main Level, Main Profile decoder. handles image sizes pixels with frame rate NTSC pixels PAL. also decode MPEG-1 sequences. coded data channel have sustained rate Mbits/second. resolution decreases, amount bandwidth SDRAM memory required frame stores also decreases.
1.2.1 Memory Utilization
L64105 supports direct connection commercial SDRAM frame stores, channel buffers, overlay memory. L64105 uses frame stores frame reconstruction display, separate video audio channel buffers rate matching, zero more regions graphical overlay. This storage combined into single contiguous memory space accessed over 16-bit wide bus. most cases this will 16-bit SDRAM, total memory space Mbytes. interface between L64105 SDRAM requires external components. L64105 pinout allows connection SDRAM made single layer. During normal operation, L64105 exclusively controls SDRAM frame stores. However, possible access SDRAM through host port L64105 test verification access overlay stores channel information.
1.2.2 Error Concealment
L64105 detects data bitstream that does meet MPEG-2 syntax grammar rules flag data exception processing. Hardware error handling limited error masking application concealment vectors video. Audio error concealment limited muting errors searching error-free frames. L64105 flags gross errors bitstream channel buffer overrun underrun nonconformance bitstream. L64105 flags errors that they masked video audio output. host microcontroller programmed execute mechanisms recover from gross errors.
L64105 Overview
Features
Video Decoder
Fully compliant Main Profile Main Level MPEG-2 video
standard, 13818-2.
Decodes MPEG-2 bitstream, including MPEG-2 Program stream,
with private stream support.
Decodes MPEG-1 bitstream defined 11172, including
MPEG-1 system layer.
Operates image sizes ITU-R BT.601 resolution (720
pixels NTSC PAL).
Mbps sustained input channel data rate program
streams streams from transport demultiplexer.
8-bit parallel dedicated input channel interface. 8-bit luma/chroma output. Complete on-chip channel buffer controller display buffer
controls.
Error concealment maintains display images during channel
errors. Video Interface
Integrates flexible 256-color, On-Screen Display (OSD) controller. Allows connection external generator. Programmable display management. Slave video timing operation. Integrates postprocessing filters image resizing (horizontal
vertical).
Integrates vertical filter letterbox format display. Implements pulldown. Supports scan with 1/8-pixel accuracy. Supports 4:2:0 4:2:2 sampling filters.
Introduction
Audio Decoder
Processes MPEG audio with support Linear data. Decodes dual-channel MPEG audio, Layer 13818-2,
supporting rates Kbps Kbps sampling rates 22.05, 44.1, kHz.
Supports Linear streams with sample rates
24-bit resolution.
IEC958 output interface audio data bitstreams. Mute error concealment. Provides audio "Bypass" mode interface audio
decoder. System
Programmable preparser accepts PES, streams. Direct connection commodity SDRAM. Input/output interfaces optimized glueless integration into
consumer video systems.
Operates from single 27-MHz clock with additional audio
sample clock input.
Total external memory required audio video decoding
16-Mbit SDRAM ITU-R BT.601-5 resolution.
Interfaces Intel Motorola (and compatible) 8-bit
microcontrollers initialization, testing, status monitoring.
Direct interface off-the-shelf NTSC/PAL video encoders. Direct interface off-the-shelf audio stereo DACs. Available 160-pin, PQFP pack. power 3.3-Volt process. TTL-compatible pins.
Features
Introduction
Chapter Signal Descriptions
This chapter describes input/output signals L64105. chapter contains following sections:
Section 2.1, "Signals Organization," page Section 2.2, "Host Interface," page Section 2.3, "Channel Interface," page Section 2.4, "Memory Interface," page Section 2.5, "Video Interface," page Section 2.6, "Audio Interface," page Section 2.7, "Miscellaneous Test Interfaces," page 2-11
Signals Organization
L64105 major interfaces:
Host (8-bit microcontroller interface) Channel (8-bit synchronous asynchronous bitstream data
channel)
Memory (16-bit synchronous SDRAM interface) Video (8-bit multiplexed digital video output) Audio (serial digital audio output) Test
Figure shows signals, their grouping, their direction. lower case signal name indicates that active signal.
Figure
L64105 Signals
BUSMODE A[8:0] D[7:0] PD[7:0] CREF BLANK OSD_ACTIVE EXT_OSD[3:0] CD_ASDATA CD_BCLK CD_LRCLK CD_ACLK ASDATA AREQn VREQ CH_DATA[7:0] L64105 BCLK LRCLK A_ACLK AUDIO_SYNCn ACLK_32 ACLK_441 ACLK_48 SPDIF_IN SPDIF_OUT SCSn SCS1n SDQM SBA[11:0] PLLVDD PLLVSS RESETn SYSCLK TM[1:0] ZTEST SCAN_TE Miscellaneous Test Interface Audio Interface Video Interface
Host Interface
DSn/WRITEn READ/READn DTACKn/RDYn WAITn INTRn DREQn PREQn
Channel Interface
AVALIDn VVALIDn ERRORn
Memory Interface
SCASn SRASn SBD[15:0] SWEn SCLK
Signal Descriptions
Host Interface
BUSMODE Host Controller Select Input This must tied host Intel processor Motorola processor. Intel processor uses separate pins, READn WRITEn, read write transfers. Motorola processor uses single read/write signal, READ. Chip Select Input This active-LOW signal indicates attempt external host access L64105 either read write cycle. must asserted entire read/write cycle held more than transaction. Address Input Nine-bit address input selects internal registers. address value these lines latched falling edge READn read cycle falling edge WRITEn write cycle Intel mode. Motorola mode uses separate address strobe, ASn. Address Strobe Input Active-LOW address strobe input. This signal used Motorola mode latch address. Host Data Bidirectional host uses D[7:0] bidirectional data program L64105 access status bitstream information during operation. During read cycle, D[7:0] carries valid information from internal L64105 register. DTACKn/RDYn WAITn indicate when data valid. write cycles, data latched L64105 rising edge DSn/WRITEn.
A[8:0]
D[7:0]
DSn/WRITEn Data Strobe/Write Indicator Input Motorola Mode indicates when host strobes data L64105. Read transactions start when DSn, CSn, LOW. During write cycle, L64105 latches data rising edge DSn.
Host Interface
WRITEn Intel Mode external host asserts WRITEn start write cycle. READn must HIGH during write cycle, must during write cycle. address registered falling edge WRITEn. data latched L64105 rising edge WRITEn. READ/READn Read/Write Strobe Read Indicator Input READ Motorola Mode Motorola host asserts READ HIGH read cycle deasserts write cycle. must asserted select L64105. READn Intel Mode Intel host asserts READn holds WRITEn deasserted perform read cycle. address registered falling edge READn. must asserted select L64105. DTACKn/RDYn Data Acknowledge/Data Ready 3-State Output DTACKn Motorola Mode L64105 asserts this signal indicate external host that current transaction (read write) completed. DTACKn 3-stated asserted. cycle terminated L64105 deasserts DTACKn before cycle completed. RDYn Intel Mode L64105 asserts this signal indicate external host that current transaction (read write) completed. RDYn 3-stated asserted. cycle terminated L64105 deasserts RDYn before cycle completed. WAITn Wait 3-State Output This signal used instead DTACKn/RDYn hosts that require inverted sense. L64105 asserts WAITn indicate that Host Interface busy with read write cycle deasserts when current cycle completed. WAITn 3-stated when active. Interrupt Output INTRn active-LOW, open-drain, output signal. L64105 asserts this signal alert host that
INTRn
Signal Descriptions
unmasked interrupt condition occurred chip. host must read registers through determine cause interrupt, take appropriate action, Clear Interrupt Register (page 4-10) deassert INTRn. DREQn Transfer Request Output L64105 asserts this signal when ready receive byte data from transmit byte data external controller. state DREQn reflects condition internal read write FIFOs. write cycles, DREQn deasserted when write FIFO near full (more than space left) deasserted when FIFO near full (one space left). read cycles, DREQn asserted when read FIFO near empty (more than space filled) deasserted when FIFO near empty (one space filled). maximum transfer rate over this interface Mbps worst case conditions. peak data rate increase above this depending system SDRAM usage. FIFO Request Output L64105 asserts this signal when ready receive byte data FIFO, i.e., when FIFO near full (less than bytes unread). FIFO allows host send Linear audio samples Audio Decoder L64105. PREQn used request signal external controller.
PREQn
Channel Interface
AREQn Audio Transfer Request Output L64105 asserts AREQn when ready receive byte coded audio data stream mode (from transport stream demultiplexer) byte data program stream modes. decoder ready when channel input FIFO near full. Video Transfer Request Output L64105 asserts VREQn when ready receive byte coded audio data stream mode (from transport stream demultiplexer). decoder ready when channel input FIFO near full. VREQn used program stream modes.
VREQn
Channel Interface
CH_DATA[7:0] Channel Data Input CH_DATA used transfer 8-bit, parallel bitstreams into L64105. maximum transfer rate over this interface Mbps worst case conditions. peak data rate increase above this rate depending system SDRAM usage. AVALIDn Audio Data Valid Input channel device asserts this signal response AREQn when data byte placed CH_DATA valid. L64105 transfers byte when AVALIDn deasserted. This signal used with input synchronous transfers. Video Data Valid Input channel device asserts this signal response VREQn when data byte placed CH_DATA valid. L64105 transfers byte when VREQn deasserted. This signal used with input synchronous transfers. This signal used only stream mode when channel input program from transport stream demultiplexer. AVALIDn signal data bytes program stream modes. Bitstream Error Input ERRORn asserted channel device signal uncorrectable errors bitstream used L64105 invoke error handling routines. latched L64105 rising edge AVALIDn VVALIDn. Channel Clock Input free-running clock from external channel device. must have period that SYSCLK MHz). DCK, together with AVALIDn VVALIDn signals, used write data synchronously L64105 channel input.
VVALIDn
ERRORn
Signal Descriptions
Memory Interface
Important: length connections between L64105 SDRAM layout must kept short possible, must matched length load, load should less than SDRAM Chip Select Output host asserts this signal select address SDRAM chip, first Mbytes memory. recommended SDRAM size L64105
2048 bits
SCSn
SCS1n
Second SDRAM Chip Select Output host asserts this signal select high address SDRAM chip systems that have more than Mbytes memory. high address SDRAM chip must have same page size address SDRAM chip does have have same number pages. SDRAM Control Output SDQM active HIGH output signal SDRAM data control mask. SDRAM Address Output row/column multiplexed address SDRAM memory. L64105's microcontroller host address SDRAM were RAM. Memory Interface converts these addresses SDRAM format. SDRAM Column Address Select Output Memory Interface asserts this signal when SDRAM column address SBA[11:0]. SDRAM Address Select Output Memory Interface asserts this signal when SDRAM address SBA[11:0]. SDRAM Data Bidirectional This 16-bit bidirectional data directly connected SDRAM(s) buffering channel data reconstructed pictures.
SDQM
SBA[11:0]
SCASn
SRASn
SBD[15:0]
Memory Interface
SWEn
SDRAM Write Enable Output Memory Interface asserts SWEn SDRAM write cycles holds deasserted SDRAM read cycles. SDRAM 81-MHz Clock Output 27-MHz SYSCLK input multiplied three using on-chip generate 81-MHz SCLK. SCLK should connected through terminating resistor mounted close possible SCLK L64105.
SCLK
Important:
Video Interface
PD[7:0] Pixel Data Output Output PD[7:0] carries pixel data reconstructed pictures. pixel data formatted ITU_R BT.601 chromaticity. Chroma Reference Output Video Interface asserts CREF when component Chroma PD[7:0] deasserts other times. Blank Output BLANK composite blank output from L64105 display controller. polarity user-defined. On-Screen Display Output Memory Interface asserts this signal indicate that on-chip pixel PD[7:0] nontransparent. This signal indicates which pixels have mixed OSD. EXT_OSD[3:0] Palette Selection Input host controls external device (such character generator) write half-bytes across this select colors from 16-color look-up table L64105 used external OSD.
CREF
BLANK
OSD_ACTIVE
Signal Descriptions
Horizontal Sync Input horizontal sync signal from PAL/NTSC Encoder. used reset horizontal counters display controller. should synchronous SYSCLK. Vertical Sync/Odd-Even Field Indicator Input vertical sync signal from PAL/NTSC Encoder. programmed either conventional vertical sync input even/odd field indicator. even/odd field indicator mode, internal display controller counters reset each time changes state beginning each field). polarity field controlled timing relative should synchronous SYSCLK.
Audio Interface
CD_ASDATA Mode Audio Data Input Unencoded serial audio data from other storage device. Connected directly ASDATA output when host selects Bypass mode. CD_BCLK Mode Clock Input clock from player. Connected directly BCLK output when host selects Bypass mode. Mode Left/Right Clock Input Left/right sample clock from player. Connected directly LRCLK output when host selects Bypass mode. Mode Clock Input clock from player. Connected directly A_ACLK output when host selects Bypass mode. Audio Serial Data Output Serial audio data from L64105's Audio Decoder nonbypass modes. data MPEG Linear audio. Serial audio data from CD_ASDATA input Bypass mode.
CD_LRCLK
CD_ACLK
ASDATA
Audio Interface
BCLK
Clock Output Serial data clock used L64105's Interface serialize decoded audio data external clock rising edge. BCLK derived from ACLK_ inputs under host control normal modes CD_BCLK input Bypass mode. Left/Right Sample Clock Output Used indicate which samples belong left right stereo channels. default mode, LRCLK asserted when right channel sample ASDATA deasserted when left channel sample ASDATA pin. host Invert LRCLK Register (page 4-84) invert sense clock (HIGH left channel, right). Clock Output This clock buffered from selected input ACLK_ (see following ACLK_ description). CD-bypass mode, this clock comes directly from CD_ACLK input pin.
LRCLK
A_ACLK
AUDIO_SYNCn Audio Sync Strobe Output Provides indication Audio Decoder synchronization bitstream. Used transport systems requiring hardware sync controls. This active pulse time audio frame decode start. ACLK_32, ACLK_441, ACLK_48 Audio Reference Clocks Input Host selectable audio reference clocks from which clocks external DAC, internal Interface, internal Interface derived. ACLK_32 ACLK_441 44.1 ACLK_48 where 768, 512, 384, 256. least three ACLK_ inputs must supplied must integrally divisible into required sample rate clocks. ACLK Select bits Register (page 4-84) ACLK Divider Select bits Register (page 4-85).
2-10
Signal Descriptions
SPDIF_IN
External Input This input directly connected SPDIF_OUT when host selects Bypass mode. Output Output IEC958 formatted output L64105's Interface normal modes SPDIF_IN Bypass mode.
SPDIF_OUT
Miscellaneous Test Interfaces
PLLVDD Power Supply Input This provides power (3.3 on-chip deriving 81-MHz SDRAM clock. This power supply must isolated from digital power plane with filter shown Figure only connected voltage regulator. PLLVDD Decoupling Circuit
Ferrite Bead PLLVDD
Figure
PLLVSS
PLLVSS
PLLVSS
Ground Input This provides ground on-chip deriving 81-MHz SDRAM clock. This supply must isolated from digital ground plane, only connected voltage regulator. should decoupled from PLLVDD pin. Reset Input When RESETn asserted, L64105 resets internal microcontroller, FIFO controllers, state machines, registers. minimum RESETn pulse width cycles SYSCLK (8/27 ns). SYSCLK selected ACLK (ACLK_32, ACLK_441, ACLK_48) must running during reset.
RESETn
Miscellaneous Test Interfaces
2-11
SYSCLK
Device Clock Input Device clock nominal frequency MHz. Picture reconstruction video timing referenced with respect this clock. SYSCLK also drives generate 81-MHz clock SDRAM interface. Test Mode Input These inputs used Logic during manufacturing test. They exercised customer system. They should both tied system. Test Mode Input Test mode pin. This should tied system normal operation. Forcing this signal 3-states outputs allowing simple bed-of-nails testing. Test Mode Input Test mode pin. This should tied system normal operation.
TM[1:0]
ZTEST
SCAN_TE
2-12
Signal Descriptions
Chapter Register Summary
Communication with L64105 Decoder through 512, 8-bit registers. registers named their decimal address, 511. They organized into eight groups listed Table 3.1. registers, fields, bits each group further detailed Table through Table 3.8. find register, field, bit, Table find starting page summary table group. Then summary table find page Chapter which register described. know name field bit, alphabetic index starting page 3-31 find page number which described.
Summary Register
Table
Register Number 0-63 64-191 192-223 224-255 256-335 336-383 384-415
L64105 Register Groupings
Table Number Page Reference 3-14 3-17 3-20 3-24 3-27
Register Group Host Interface Registers Video Decoder Registers Memory Interface Registers Microcontroller Registers Video Interface Registers Audio Decoder Registers Test Registers
Table
Host Interface Registers
Default Value (Hex) Status/Command/Data Decode Status Interrupt Decode Status Mask Aux/User Data FIFO Ready Interrupt Aux/User Data FIFO Ready Mask First Slice Start Code Detect Interrupt First Slice Start Code Detect Mask Sequence Code Detect Interrupt Sequence Code Detect Mask SDRAM Transfer Done Interrupt SDRAM Transfer Done Mask Reserved Audio Sync Recovery Interrupt Audio Sync Recovery Mask Field Interrupt Field Mask Audio Sync Code Detect Interrupt Audio Sync Code Detect Mask Picture Start Code Detect Interrupt Picture Start Code Detect Mask Compare Audio Interrupt Compare Audio Mask Reserved Begin Active Video Interrupt Begin Active Video Mask
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref.
(Sheet
Register Summary
Table
Host Interface Registers (Cont.)
Default Value (Hex) Status/Command/Data Begin Vertical Blank Interrupt Begin Vertical Blank Mask Overflow Interrupt Overflow Mask Compare Interrupt Compare Mask Pack Data Ready Interrupt Pack Data Ready Mask Audio Data Ready Interrupt Audio Data Ready Mask Video Data Ready Interrupt Video Data Ready Mask Reserved Code Video Channel Interrupt Code Video Channel Mask Reserved Audio Event Interrupt Audio Event Mask Video Event Interrupt Video Event Mask Audio Channel Buffer Overflow Interrupt Audio Channel Buffer Overflow Mask Video Channel Buffer Overflow Interrupt Video Channel Buffer Overflow Mask
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref.
(Sheet
Summary Register
Table
Host Interface Registers (Cont.)
Default Value (Hex) Status/Command/Data
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref.
Reserved Audio Channel Buffer Underflow Interrupt Audio Channel Buffer Underflow Mask Video Channel Buffer Underflow Interrupt Video Channel Buffer Underflow Mask Reserved Length Error Interrupt Length Error Mask Context Error Interrupt Context Error Mask Audio Illegal Error Interrupt Audio Illegal Error Mask Audio Sync Error Interrupt Audio Sync Error Mask Reserved Packet Error Interrupt Packet Error Interrupt Mask Channel Buffer Underflow Interrupt Channel Buffer Underflow Mask Invert Channel Clock Channel Request Mode Channel Pause Channel Bypass Enable AREQ Status 4-10
(Sheet
Register Summary
Table
Host Interface Registers (Cont.)
Default Value (Hex) Status/Command/Data VREQ Status Reserved Clear Interrupt (INTRn) Reserved Channel Status Channel Start/Reset Reserved Stream Select [1:0] Pause Software Reset Reserved Reserved Value [7:0] Value [15:8] Value [23:16] Value [31:24] Compare/Capture [7:0] Compare/Capture [15:8] Compare/Capture [23:16] Compare/Capture [31:24] Compare/Capture Mode [1:0] Capture Picture Start Code Capture Audio Sync Code Capture Beginning Active Video 4-14 4-13 4-13 4-12 4-11 4-10
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref. 4-10
(Sheet
Summary Register
Table
Host Interface Registers (Cont.)
Default Value (Hex) Status/Command/Data Capture Pack Data Ready Capture Audio Ready Capture Video Ready Reserved Capture Video Capture Audio Reserved Audio Start Compare Video Start Compare Reserved Compare Audio [7:0] Compare Audio [15:8] Compare Audio [23:16] Compare Audio [31:24] Reserved Video Channel Bypass Data [7:0] Audio Channel Bypass Data [7:0] Reserved 4-16 4-17 4-16 4-15 4-16 4-15
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref. 4-14 4-15
24-27 30-63
18-1B 1E-3F
(Sheet Cleared after read.
Register Summary
Table
Video Decoder Registers
Default Value (Hex) Status/Command/Data Reset Data FIFO Data FIFO Status [1:0] Data Layer [2:0] Reserved Reset User Data FIFO User Data FIFO Status [1:0] User Data Layer [2:0] Reserved User Data FIFO Output [7:0] Data FIFO Output [7:0] Reset Channel Buffer Error Reset Audio Header/System Channel Buffer Reset Video Header Channel Buffer Reserved Reset Video Channel Buffer Reset Audio Channel Buffer Reserved Enable Video Read Compare Enable Audio Read Compare [1:0] Video Numitems/Pics Panic Mode Select [1:0] Reserved 4-22 4-21 4-20 4-20 4-19 4-19 4-18 4-18
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref. 4-17
(Sheet
Summary Register
Table
Video Decoder Registers (Cont.)
Default Value (Hex) Status/Command/Data Reserved Video Channel Buffer Start Address [7:0]1 Video Channel Buffer Start Address Reserved Video Channel Buffer Address [7:0]1 Video Channel Buffer Address [13:8]1 Reserved Audio Channel Buffer Start Address [7:0]1 Audio Channel Buffer Start Address [13:8]1 Reserved Audio Channel Buffer Address [7:0]1 Audio Channel Buffer Address [13:8]1 Reserved Video Header Channel Buffer Start Address [7:0]1 Video Header Channel Buffer Start Address [13:8]1 Reserved Video Header Channel Buffer Address [7:0]1 Video Header Channel Buffer Address [13:8]1 Reserved Reserved 4-24 4-24 4-24 4-23 4-23 [13:8]1 4-22
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref.
84-87
54-57
(Sheet
Register Summary
Table
Video Decoder Registers (Cont.)
Default Value (Hex) Status/Command/Data Audio Header/System Channel Buffer Start Address [7:0]1 Audio Header/System Channel Buffer Start Address [13:8]1 Reserved Audio Header/System Channel Buffer Address [7:0]1 Audio Header/System Channel Buffer Address [13:8]1 Reserved Reserved Video Channel Buffer Write Address [7:0]2 Video Channel Buffer Write Address [15:8]2 Video Channel Buffer Write Address [19:16]2 Reserved Audio Channel Buffer Write Address [7:0]2 Audio Channel Buffer Write Address [15:8]2 Audio Channel Buffer Write Address [19:16]2 Reserved Video Header Channel Buffer Write Address [7:0]2 Video Header Channel Buffer Write Address [15:8]2 Video Header Channel Buffer Write Address [19:16]2 Reserved 4-27 4-26 4-26 4-25
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref. 4-25
92-95
5C-5F
(Sheet
Summary Register
Table
Video Decoder Registers (Cont.)
Default Value (Hex) Status/Command/Data Reserved Video Channel Buffer Read Address [7:0]2 Video Channel Buffer Compare Address [7:0] Video Channel Buffer Read Address [15:8]2 Video Channel Buffer Compare Address [15:8] Video Channel Buffer Read Address [19:16])2 Video Channel Buffer Compare Address [18:16] Reserved Audio Channel Buffer Read Address [7:0]2 Audio Channel Buffer Compare Address [7:0] Audio Channel Buffer Read Address [15:8]2 Audio Channel Buffer Compare Address [15:8] Audio Channel Buffer Read Address [19:16]2 Audio Channel Buffer Compare Address [18:16] Reserved Audio Header/System Channel Buffer Write Address [7:0]3 Audio Header/System Channel Buffer Write Address [15:8]3 4-29 4-28 4-29 4-28 4-29 4-28 4-29 4-27 4-28 4-27 4-28 4-27 4-28
Addr (Dec) 105-
Addr (Hex) 69-6B
Bit(s)
Page Ref.
(Sheet
3-10
Register Summary
Table
Video Decoder Registers (Cont.)
Default Value (Hex) Status/Command/Data Audio Header/System Channel Buffer Write Address [19:16]3 Reserved Reserved Channel Buffer Read Address [7:0]3 Channel Buffer Read Address [15:8]3 Channel Buffer Read Address [19:16]3 Reserved Reserved MPEG Audio Extension Stream [4:0] Reserved Reserved Picture Start Code Read Address [7:0]3 Picture Start Code Read Address [15:8]3 4-31 4-30 4-30
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref. 4-29
117-
75-77
125-
7D-7F
Picture Start Code Read Address [19:16]3 Reserved Audio Sync Code Read Address [7:0]3 Audio Sync Code Read Address [15:8]3 4-31
Audio Sync Code Read Address [19:16]3 Reserved Video Channel Buffer Numitems [7:0]2 Video Numitems/Pics Channel Compare Panic [7:0]2 4-32
(Sheet
Summary Register
3-11
Table
Video Decoder Registers (Cont.)
Default Value (Hex) Status/Command/Data Video Channel Buffer Numitems [15:8]2 Video Numitems/Pics Channel Compare Panic [15:8]2 Video Channel Buffer Numitems [18:162] Video Numitems/Pics Channel Compare Panic [18:16]2 Reserved Audio Channel Buffer Numitems [7:0]2 Audio Channel Buffer Numitems [15:8]2 4-33 4-32
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref. 4-32
Audio Channel Buffer Numitems [18:16]2 Reserved Channel Buffer Numitems [7:0]2 Channel Buffer Numitems [15:8]2 4-33
Channel Buffer Numitems [18:16]2 Reserved Audio Stream [4:0] Audio Stream Select Enable [2:0] Transport Private Stream Audio Reserved Video Stream [3:0] Video Stream Select Enable [1:0] Video Header Enable [1:0] Reserved 4-36 4-35 4-35 4-34
(Sheet
3-12
Register Summary
Table
Video Decoder Registers (Cont.)
Default Value (Hex) Status/Command/Data Audio Header Enable [1:0] System Header Enable [1:0] Pack Header Enable [1:0] Reserved Reserved Audio Packet Error Status4 Video Packet Error Reserved Pictures Video Channel Buffer Counter [7:0] Pictures Video Channel Buffer Counter [15:8] Reserved 4-38 Status4 4-37 4-37
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref. 4-36
152-
(Sheet channel must stopped access these registers. Addresses SDRAM 256-byte boundaries. SDRAM addresses 8-byte boundaries. most significant indicates that circular buffer executed "wraparound." Bytes must read least, next, most significant order. SDRAM addresses 8-byte boundaries. Bytes must read least, next, most significant order. Cleared after read.
Summary Register
3-13
Table
Memory Interface Registers
Default Value (Hex) Status/Command/Data Host Read FIFO Empty Host Read FIFO Full Host Write FIFO Empty Host Write FIFO Full Read FIFO Empty Read FIFO Full Write FIFO Empty Write FIFO Full Reserved Mode [1:0] (idle, DMA, R/W, block move) Host SDRAM Transfer Byte Ordering Refresh Extend [1:0] SDRAM Transfer Byte Ordering Reserved Host SDRAM Read Data [7:0] Host SDRAM Write Data [7:0] Host SDRAM Target Address [7:0] Host SDRAM Target Address [15:8] Host SDRAM Target Address [18:16] Reserved Host SDRAM Source Address [7:0] Host SDRAM Source Address [15:8] 4-42 4-42 4-41 4-41 4-39 4-40
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref. 4-38
(Sheet
3-14
Register Summary
Table
Memory Interface Registers (Cont.)
Default Value (Hex) Status/Command/Data Host SDRAM Source Address [18:16] Reserved Block Transfer Count [7:0] Block Transfer Count [15:8] Test Reserved Sync Control Programmable Delay Path Control Programmable Delay Path Phase Locked Status Internal Lock Counter State Internal DRAM State Reserved Internal Phase State cycles before) Internal Phase State cycles before) Internal Phase State cycle before) Internal Phase State (current cycle) Phase Detect Test High Freq [7:0] Phase Detect Test High Freq [15:8] Phase Detect Test Freq [7:0] Phase Detect Test Freq [15:8] Test High Freq [7:0] Test High Freq [15:8] 4-45 4-45 4-44 4-44 4-43 4-43 4-43
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref. 4-42
(Sheet
Summary Register
3-15
Table
Memory Interface Registers (Cont.)
Default Value (Hex) Status/Command/Data SDRAM Target Address [7:0] SDRAM Target Address [15:8] SDRAM Target Address [18:16] Reserved SDRAM Source Address [7:0] SDRAM Source Address [15:8] SDRAM Source Address [18:16] Reserved SDRAM Read Data [7:0] SDRAM Write Data [7:0] Phase Detect High Freq Test Pass Phase Detect Freq Test Pass High Freq Test Pass Freq Test Pass Reserved Test Freq [7:0] Test Freq [15:8] 4-47 4-47 4-46
Addr (Dec)
Addr (Hex)
Bit(s)
Page Ref. 4-46
(Sheet
3-16
Register Summary
Table
Microcontroller Registers
Default Value (Hex) Status/Command/Data Anchor Luma Frame Store Base Address [7:0]1 Anchor Luma Frame Store Base Address [15:8]1 Anchor Chroma Frame Store Base Address [7:0]1 Anchor Chroma Frame Store Base Address [15:8]1 Anchor Luma Frame Store Base Address [7:0]1 Anchor Luma Frame Store Base Address [15:8]1 Anchor Chroma Frame Store Base Address [7:0]1 Anchor Chroma Frame Store Base Address [15:8]1 Luma Frame Store Base Address [7:0]1 Luma Frame Store Base Address [15:8]1 Chroma Frame Store Base Address [7:0]1 Chroma Frame Store Base Address [15:8]1 Video Skip Frame Status [1:0] Video Skip Frame Mode [1:0] Video Continuous Skip Status Video Continuous Skip Mode Reserved Video Repeat Frame Status Video Repeat Frame Enable Video Continuous Repeat Frame Status Video Continuous Repeat Frame Mode Reserved 4-52 4-51 4-51 4-50 4-49 4-49 4-49 4-48 4-48
Addr Addr (Dec) (Hex) Bit(s)
Page Ref. 4-48
(Sheet
Summary Register
3-17
Table
Microcontroller Registers (Cont.)
Default Value (Hex) Status/Command/Data Forward Mode Status Forward Mode Enable Forward Display Single Step Status Forward Display Single Step Command Current Display Frame [1:0] Current Decode Frame [1:0] Reserved Reserved Host Force Broken Link Mode Panic Prediction Enable User Data Only Concealment Copy Option Force Rate Control Ignore Sequence Reserved Host Next GOP/Seq Status Host Search Next GOP/Seq Command Reserved Table Ready Intra Table Table Address [5:0] Table Entry [7:0] 4-57 4-56 4-56 4-55 4-54 4-53
Addr Addr (Dec) (Hex) Bit(s)
Page Ref. 4-52
(Sheet
3-18
Register Summary
Table
Microcontroller Registers (Cont.)
Default Value (Hex) Status/Command/Data Microcontroller [7:0] Microcontroller [11:8] Reserved Revision Number [7:0] Decode Start/Stop Command Reserved Reserved Reduced Memory Mode (RMM) Reserved Reserved 4-58 4-57 4-57
Addr Addr (Dec) (Hex) Bit(s) 249-
Page Ref. 4-57
(Sheet SDRAM addresses 64-byte boundaries.
Summary Register
3-19
Table
Video Interface Registers
Default Value (Hex)
Addr 256-
Addr 100-
Bit(s)
Status/Command/Data Reserved
Page Ref.
Mode [1:0] Reserved Palette Counter Zero Flag Clear Palette Counter Display Override Mode [1:0] Force Video Background [1:0] Programmable Background Y[7:0] Programmable Background Cb[7:0] Programmable Background Cr[7:0] Palette Write [7:0] Field Pointer [7:0]
4-58
4-59
(Sheet
4-59 4-60
4-60 4-61
Field Pointer [15:8]1 Even Field Pointer [7:0]1 Even Field Pointer [15:8]1 Weight [3:0] Chroma Filter Enable Reserved Horizontal Decimation Filter Enable Reserved Freeze Mode [1:0] Pulldown from Bitstream Host Repeat First Field 4-62 4-61 4-61
3-20
Register Summary
Table
Video Interface Registers (Cont.)
Default Value (Hex)
Addr
Addr
Bit(s)
Status/Command/Data Host Field First First Field Odd/Not Even Field Top/Not Bottom Field Last Field Horizontal Filter Enable Horizontal Filter Select Display Mode [3:0] Field Sync Enable Horizontal Filter Scale [7:0] Main Reads Line [6:0] Reserved Scan Pixel Offset [2:0] Scan Byte Offset [2:0] Scan from Bitstream Automatic Field Inversion Correction Horizontal Scan Luma/Chroma Word Offset [7:0] Vertical Scan Line Offset [7:0] Vline Count Init [2:0] Reserved Override Picture Width [6:0] Reserved
Page Ref. 4-62
4-63
4-63
4-64
4-64 4-65
4-65
4-66
4-67
(Sheet
Summary Register
3-21
Table
Video Interface Registers (Cont.)
Default Value (Hex)
Addr
Addr
Bit(s)
Status/Command/Data ITU-R BT.656 Mode Sync Active Reserved Pixel State Reset Value [1:0] CrCb Complement VSYNC Input Type Reserved Display Override Luma Frame Store Start Address [7:0]1 Display Override Luma Frame Store Start Address [15:8]1 Display Override Chroma Frame Store Start Address [7:0]1 Display Override Chroma Frame Store Start Address [15:8]1 Reserved Number Segments [5:0] Reserved Television Standard Select [1:0] Reserved Reserved
Page Ref. 4-67
4-67 4-68
4-68
4-69
4-69
291-
123-
Main Start [7:0] Main [7:0] Main Start [10:8] Reserved
4-70
(Sheet
3-22
Register Summary
Table
Video Interface Registers (Cont.)
Default Value (Hex)
Addr
Addr
Bit(s)
Status/Command/Data Main [10:8] Reserved Main Start Column [7:0] Main Column [7:0] Main Start Column [10:8] Reserved Main Column [10:8] Reserved Vcode Zero [4:0] Vcode Even Vcode Even Plus Fcode Vcode Even [7:0] Fcode [7:0] Start Column [7:0] Start Column [7:0] Start Column [10:8] Reserved Start Column [10:8] Reserved Display Start Command Reserved Reserved
Page Ref. 4-70
4-70
4-70
4-70 4-71
4-71
4-72
4-72
4-72
310-
136-
(Sheet
Summary Register
3-23
Table
Audio Decoder Registers
Default Value (Hex) Status/Command/Data MPEG bitrate_index [3:0] MPEG protection_bit MPEG layer_code [1:0] MPEG MPEG copyright MPEG mode_extension [1:0] MPEG mode [1:0] MPEG private_bit MPEG sampling_freq [1:0] Reserved MPEG emphasis [1:0] MPEG original/copy Reserved num_of_audio_ch [2:0] audio_frm_num [4:0] Reserved mute_bit emphasis [1:0] quantization [1:0] [1:0] Reserved FIFO Empty 4-77 4-77 4-77 4-76 4-75 4-76 4-74
Addr
Addr
Bit(s)
Page Ref. 4-72 4-73 4-74
339-
153-
(Sheet
3-24
Register Summary
Table
Audio Decoder Registers (Cont.)
Default Value (Hex) Status/Command/Data FIFO Near Full FIFO Full Audio Decoder Play Mode Status [1:0] Audio Decoder Soft Mute Status Audio Decoder Reconstruct Error MPEG Multichannel Extension Sync Word Missing Reserved Reserved Audio Decoder Play Mode [1:0] Audio Decoder Start/Stop Reserved Audio Formatter Play Mode [1:0] Audio Formatter Start/Stop Reserved Audio Decoder Mode Select [2:0] Reserved Audio Dual-Mono Mode [1:0] Reserved User Mute Mute Error FIFO Data [7:0] Linear dynscalehigh [7:0] Linear dynscalelow [7:0] 4-83 4-82 4-82 4-81 4-80 4-79 4-80 4-79
Addr
Addr
Bit(s)
Page Ref. 4-78
(Sheet
Summary Register
3-25
Table
Audio Decoder Registers (Cont.)
Default Value (Hex) Status/Command/Data Scale [7:0] ACLK Select [1:0] Invert LRCLK Reserved User Valid ACLK Divider Select [3:0] LPCM Dynamic Range Reserved Reserved Host Emphasis [2:0] Overwrite Emphasis Host Copyright Overwrite Copyright Overwrite Category Host Overwrite Quantization [1:0] Overwrite Quantization Enable MPEG Formatter Only Formatter Skip Frame Size [1:0] Reserved Host Category [7:0] Reserved Data Valid 4-90 4-89 4-89 4-88 4-88 4-87 4-85 4-87 4-85
Addr
Addr
Bit(s)
Page Ref. 4-84
(Sheet
3-26
Register Summary
Table
Audio Decoder Registers (Cont.)
Default Value (Hex) Status/Command/Data Reserved Selection [1:0] Host Info [2:0] Host Value [15:8] Host Value [7:0] Reserved diagnostic 4-91 4-90
Addr
Addr
Bit(s)
Page Ref.
371-
173-
(Sheet
Table
Test Registers
Default Value (Hex) Status/Command/Data Memory Test Address [7:0] Memory Test Address [11:8] Reserved Operational Mode Test [1:0] Report Test Initiate Memory Test Data Pattern Applied [1:0] Memory Test Output Select Reserved 4-91 4-92
Addr
Addr
Bit(s)
Page Ref. 4-91
(Sheet
Summary Register
3-27
Table
Test Registers (Cont.)
Default Value (Hex) Status/Command/Data MemTest01 Pass/Fail Status1 MemTest02 Pass/Fail Status1 MemTest03 Pass/Fail Status1 MemTest04 Pass/Fail Status1 MemTest05 Pass/Fail Status MemTest06 Pass/Fail Status1 MemTest07 Pass/Fail Status1 MemTest08 Pass/Fail Status1 MemTest09 Pass/Fail Status1 MemTest10 Pass/Fail Status1 MemTest11 Pass/Fail Status1 MemTest12 Pass/Fail Status1 MemTest13 Pass/Fail Status1 MemTest14 Pass/Fail Status1 MemTest15 Pass/Fail Status1 MemTest16 Pass/Fail Status1 4-93 4-93
Addr
Addr
Bit(s)
Page Ref. 4-93
(Sheet
3-28
Register Summary
Table
Test Registers (Cont.)
Default Value (Hex) Status/Command/Data MemTest17 Pass/Fail Status1 MemTest18 Pass/Fail Status1 MemTest19 Pass/Fail Status1 MemTest20 Pass/Fail Status1 MemTest21 Pass/Fail Status1 MemTest22 Pass/Fail Status1 MemTest23 Pass/Fail Status1 MemTest24 Pass/Fail Status1 MemTest25 Pass/Fail Status1 MemTest26 Pass/Fail Status1 MemTest27 Pass/Fail Status1 MemTest28 Pass/Fail Status1 MemTest29 Pass/Fail Status1 MemTest30 Pass/Fail Status1 MemTest31 Pass/Fail Status1 MemTest32 Pass/Fail Status1 MemTest33 Pass/Fail Status1 MemTest34 Pass/Fail Status1 MemTest35 Pass/Fail Status1 MemTest36 Pass/Fail Status1 Reserved 4-93 4-93
Addr
Addr
Bit(s)
Page Ref. 4-93
(Sheet
Summary Register
3-29
Table
Test Registers (Cont.)
Default Value (Hex) Status/Command/Data MemTest37 Pass/Fail Status1 MemTest38 Pass/Fail Status1 MemTest39 Pass/Fail Status1 Reserved Overall MemTest Pass/Fail Status1 Reserved 4-93
Addr
Addr
Bit(s)
Page Ref. 4-93
393-
189-
(Sheet Reset after read.
3-30
Register Summary
Alphabetical Listing Register Bits Fields
Numerics Pull Down From Bitstream ACLK Divider Select [3:0] ACLK Select [1:0] Anchor Chroma Frame Store Base Address [15:0] Anchor Chroma Frame Store Base Address [15:0] Anchor Luma Frame Store Base Address [15:0] Anchor Luma Frame Store Base Address [15:0] AREQ Status Audio Channel Bypass Data [7:0] Audio Illegal Error Interrupt Audio Decoder Play Mode [1:0] Audio Decoder Play Mode Status [1:0] Audio Decoder Reconstruct Error Audio Decoder Soft Mute Status Audio Decoder Start/Stop Audio Dual-Mono Mode [1:0] Audio Channel Buffer Compare Address [19:0] Audio Channel Buffer Address [13:0] Audio Channel Buffer Numitems [18:0] Audio Channel Buffer Overflow Interrupt Audio Channel Buffer Read Address [19:0] Audio Channel Buffer Start Address [13:0] Audio Channel Buffer Underflow Interrupt Audio Channel Buffer Write Address [19:0] Audio Formatter Play Mode [1:0] Audio Formatter Start/Stop Audio Module Mode Select [2:0] Audio Packet Error Status Audio Data Ready Interrupt Audio Header Enable [1:0] Audio Header/System Channel Buffer Address [13:0] Audio Header/System Channel Buffer Start Address [13:0] Audio Header/System Channel Buffer Write Address [19:0] Audio Start Compare Audio Stream [4:0] Audio Stream Select Enable [2:0] Audio Sync Code Detect Interrupt 4-85 4-84 4-48 4-49 4-48 4-48 4-10 4-17 4-79 4-78 4-78 4-78 4-80 4-82 4-29 4-24 4-33 4-28 4-23 4-26 4-80 4-80 4-81 4-37 4-36 4-25 4-25 4-29 4-15 4-34 4-34 4-62
Alphabetical Listing Register Bits Fields
3-31
Audio Sync Code Read Address [19:0] Audio Sync Error Interrupt Audio Sync Recovery Interrupt Automatic Field Inversion Correction Data FIFO Output [7:0] Data FIFO Status [1:0] Data Layer [2:0] Aux/User Data FIFO Ready Interrupt Chroma Frame Store Base Address [15:0] Luma Frame Store Base Address [15:0] Begin Active Video Interrupt Begin Vertical Blank Interrupt Block Transfer Count [15:0] Capture Audio Ready Capture Audio Sync Code Capture Beginning Active Video Capture Audio Capture Video Capture PACK Data Ready Capture Picture Start Code Capture Video Ready Channel Bypass Enable Channel Pause Channel Request Mode Channel Start/Reset Channel Status Clear Interrupt Clear Palette Counter Sync Concealment Copy Option Context Error Interrupt Control Programmable Delay Path [1:0] Control Programmable Delay Path [1:0] CrCb Complement Current Decode Frame [1:0] Current Display Frame [1:0]
4-31 4-65 4-19 4-17 4-18
4-49 4-49 4-43
4-15 4-14 4-14 4-15 4-15 4-14 4-14 4-15 4-10 4-10 4-11 4-11 4-10 4-59 4-43 4-55 4-43 4-44 4-68 4-53 4-53
3-32
Register Summary
Data Pattern Applied [1:0] Decode Start/Stop Command Decode Status Interrupt Display Mode [3:0] Display Override Luma/Chroma Frame Store Start Addresses [15:0] Display Override Mode [1:0] Display Start Command Mode [1:0] Read FIFO Empty Read FIFO Full SDRAM Read Data [7:0] SDRAM Source Address [18:0] SDRAM Target Address [18:0] SDRAM Write Data [7:0] SDRAM Transfer Byte Ordering Write FIFO Empty Write FIFO Full Audio Event Interrupt Video Event Interrupt Enable Audio Read Compare [1:0] Enable Video Read Compare Fcode [7:0] Fcode Field Sync Enable First Field First Slice Start Code Detect Interrupt Force Rate Control Force Video Background [1:0] Formatter Skip Frame Size [1:0] Freeze Mode [1:0] User Data Only Horizontal Decimation Filter Enable Horizontal Filter Enable 4-61 4-63 4-55 4-71 4-71 4-64 4-62 4-55 4-59 4-89 4-62 4-21 4-21 4-92 4-57 4-63 4-68 4-59 4-72 4-39 4-38 4-38 4-47 4-46 4-46 4-47 4-41 4-38 4-38
Alphabetical Listing Register Bits Fields
3-33
Horizontal Filter Scale [7:0] Horizontal Filter Select Horizontal Scan Luma/Chroma Word Offset [7:0] Host Category [7:0] Host SDRAM Transfer Byte Ordering Host Force Broken Link Mode Host Next GOP/Seq Status Host Overwrite Quantization [1:0] Host Info [2:0] Host Value [15:0] Host Read FIFO Empty Host Read FIFO Full Host Repeat First Field Host SDRAM Read Data [7:0] Host SDRAM Source Address [18:0] Host SDRAM Target Address [18:0] Host SDRAM Write Data [7:0] Host Search Next GOP/Seq Command Host Field First Host Write FIFO Empty Host Write FIFO Full Host Copyright Host Emphasis [2:0] Overwrite Copyright Overwrite Emphasis Ignore Sequence Initiate Memory Test Internal Lock Counter State [1:0] Internal Phase State cycle before) [1:0] Internal Phase State cycles before) [1:0] Internal Phase State cycles before) [1:0] Internal Phase State (current cycle) [1:0] Internal SDRAM State [2:0] Intra Table Invert Channel Clock Invert LRCLK ITU-R BT.656 Mode
4-64 4-63 4-66 4-89 4-40 4-54 4-56 4-88 4-90 4-91 4-38 4-38 4-62 4-41 4-42 4-42 4-41 4-56 4-62 4-38 4-38
4-87 4-87 4-88 4-87 4-55 4-92 4-44 4-45 4-45 4-45 4-45 4-44 4-56 4-84 4-67
3-34
Register Summary
Last Field Linear dynscalehigh [7:0] Linear dynscalelow [7:0] LPCM Dynamic Range Main Reads Line [6:0] MAIN Start/End Columns [10:0] MAIN Start/End Rows [10:0] Memory Test Address [11:0] Memory Test Output Select Memory Test Pass/Fail Status Bits Microcontroller [11:0] MPEG bitrate_index [3:0] MPEG copyright MPEG emphasis [1:0] MPEG MPEG layer code [1:0] MPEG mode [1:0] MPEG mode_extension [1:0] MPEG original/copy MPEG private_bit MPEG protection_bit MPEG sampling_frequency [1:0] MPEG Audio Extension Stream [4:0] MPEG Formatter Only MPEG Multichannel Extension Sync Word Missing Mute Error Field Interrupt Number Segments [5:0] Odd/Not Even Field Operational Mode Test [1:0] Chroma Filter Enable Weight [3:0] Mode [1:0] Odd/Even Field Pointers [15:0] Palette Counter Zero Flag Palette Write [7:0] 4-63 4-91 4-61 4-61 4-58 4-61 4-59 4-60 4-69 4-65 4-70 4-70 4-91 4-92 4-93 4-57 4-72 4-74 4-76 4-74 4-74 4-75 4-74 4-76 4-76 4-73 4-76 4-30 4-89 4-79 4-82 4-63 4-83 4-83 4-87
Alphabetical Listing Register Bits Fields
3-35
Override Picture Width [6:0] Overwrite Category Overwrite Quantization Enable Pack Data Ready Interrupt Pack Header Enable [1:0] Packet Error Interrupt Scan Pixel Offset [2:0] Scan Byte Offset [2:0] Scan From Bitstream Panic Prediction Enable audio_frm_num [4:0] emphasis [1:0] [1:0] mute_bit num_of_audio_ch [2:0] quantization [1:0] FIFO Empty FIFO Full FIFO Near Full Scale [7:0] FIFO Data [7:0] Data Valid Selection Phase Detect Test High Freq [15:0] Phase Detect Test Freq [15:0] Phase Locked Status Picture Start Code Detect Interrupt Picture Start Code Read Address [19:0] Pictures Video Channel Buffer Counter [15:0] Pixel State Reset Value [1:0] Phase Detect High Frequency Test Pass Phase Detect Frequency Test Pass Test High Frequency Test Pass Frequency Test Pass Programmable Background Y/Cb/Cr [7:0] Table Address [5:0] Table Entry [7:0] Table Ready
4-67 4-88 4-89
4-37 4-65 4-65 4-65 4-54 4-77 4-77 4-77 4-77 4-77 4-77 4-77 4-78 4-78 4-84 4-83 4-90 4-90 4-45 4-45 4-44 4-31 4-38 4-67 4-47 4-47 4-43 4-47 4-47 4-60
4-56 4-57 4-56
3-36
Register Summary
Reduced Memory Mode (RMM) Refresh Extend [1:0] Report Test Reset Audio Channel Buffer Reset Audio Header/System Channel Buffer Reset Data FIFO Reset Channel Buffers Error Reset User Data FIFO Reset Video Channel Buffer Reset Video Header Channel Buffer Revision Number [7:0] Forward Display Single Step Command Forward Display Single Step Status Forward Mode Enable Forward Mode Status (IEC958) Channel Buffer Read Address [19:0] Channel Buffer Numitems [18:0] Channel Buffer Underflow Interrupt SAV/EAV Start Columns [10:0] Compare Audio [31:0] Compare Audio Interrupt Compare Interrupt Compare/Capture [31:0] Compare/Capture Mode [1:0] Overflow Interrupt Pause Value [31:0] SDRAM Transfer Done Interrupt Code Video Channel Interrupt Sequence Code Detect Interrupt Software Reset Stream Select [1:0] Sync Active System Header Enable [1:0] Television Standard Select [1:0] Top/Not Bottom Field Transport Private Stream Audio 4-69 4-63 4-35 4-30 4-33 4-72 4-16 4-13 4-14 4-12 4-13 4-12 4-12 4-67 4-36 4-58 4-40 4-92 4-20 4-20 4-17 4-20 4-18 4-20 4-20 4-57 4-53 4-53 4-52 4-52
Alphabetical Listing Register Bits Fields
3-37
User User Data FIFO Output [7:0] User Data FIFO Status [1:0] User Data Layer [1:0] User Mute Valid Test High Freq [15:0] Test Freq [15:8] Vcode Even [7:0] Vcode Even Vcode Even Plus Vcode Zero [4:0] Vertical Scan Line Offset [7:0] Video Channel Bypass Data [7:0] Video Continuous Repeat Frame Mode Video Continuous Repeat Frame Status Video Continuous Skip Mode Video Continuous Skip Status Video Channel Buffer Compare Address [19:0] Video Channel Buffer Address [13:0] Video Channel Buffer Numitems [18:0] Video Channel Buffer Overflow Interrupt Video Channel Buffer Read Address [19:0] Video Channel Buffer Start Address [13:0] Video Channel Buffer Underflow Interrupt Video Channel Buffer Write Address [19:0] Video Numitems/Pics Channel Compare Panic [18:0] Video Numitems/Pics Panic Mode Select [1:0] Video Packet Error Status Video Data Ready Interrupt Video Header Channel Buffer Address [13:0] Video Header Channel Buffer Start Address [13:0] Video Header Channel Buffer Write Address [19:0] Video Headers Enable [1:0] Video Repeat Frame Enable Video Repeat Frame Status Video Skip Frame Mode [1:0] Video Skip Frame Status [1:0] Video Start Compare Video Stream [3:0] 4-85 4-45 4-47 4-71 4-71 4-71 4-70 4-66 4-16 4-52 4-51 4-51 4-50 4-28 4-23 4-32 4-27 4-22 4-26 4-32 4-22 4-37 4-24 4-24 4-27 4-36 4-51 4-51 4-50 4-50 4-16 4-35 4-85 4-19 4-18 4-19 4-82
3-38
Register Summary
Video Stream Select Enable [1:0] Length Error Interrupt Vline Count Init [2:0] VREQ Status VSYNC Input Type
4-35 4-66 4-10 4-68
Alphabetical Listing Register Bits Fields
3-39
3-40
Register Summary
Chapter Register Descriptions
This chapter describes field assignments registers L64105. chapter contains following sections:
Section 4.1, "Host Interface Registers," page Section 4.2, "Video Decoder Registers," page 4-17 Section 4.3, "Memory Interface Registers," page 4-38 Section 4.4, "Microcontroller Registers," page 4-48 Section 4.5, "Video Interface Registers," page 4-58 Section 4.6, "Audio Decoder Registers," page 4-72 Section 4.7, "RAM Test Registers," page 4-91
locate specific register, field, bit, register summary Chapter know name field bit, alphabetic index starting page 3-31 find page number which described.
Host Interface Registers
Figure
Field Interrupt
Register (0x000)
Audio Sync Recovery Interrupt Audio Sync Recovery Mask SDRAM Transfer Done Interrupt Sequence Code Detect Interrupt First Slice Start Code Detect Interrupt Aux/User Data FIFO Ready Interrupt Decode Status Interrupt
Read
Reserved
Write
Field Mask
Reserved
SDRAM Sequence First Slice Aux/User Decode Transfer Code Start Code Data FIFO Status Mask Done Mask Detect Mask Detect Mask Ready Mask
Decode Status Interrupt This when video decode status changes from stopped running cleared when status changes from running stopped Either status change causes assertion INTRn interrupt signal host masked. transition occurs picture start code boundary after channel start. linked timing last field display system. decode status updated internally change when following events recognized internal microcontroller: write Decode Start/Stop Command register (page 4-57) host. When Video Start Compare register (page 4-16) host compare occurs. this case, status goes from stopped running. Reading this register does change Decode Status bit. INTRn asserted host sets mask bit. Aux/User Data FIFO Ready Interrupt When set, indicates there data User Data FIFO ready read. ready ready change causes assertion INTRn signal masked. status Data FIFO (page 4-17) User Data FIFO (page 4-18) read determine which valid data. cleared reading. Even though data remains FIFOs, further interrupts generated. INTRn asserted host sets mask bit.
Register Descriptions
First Slice Start Code Detect Interrupt This when decoder detects first slice start code after picture layer. INTRn asserted unless host sets mask bit. Sequence Code Detect Interrupt This when decoder detects sequence code. INTRn asserted unless host sets mask bit. SDRAM Transfer Done Interrupt This when SDRAM block move completed. INTRn asserted unless host sets mask bit. Reserved this when writing Register Audio Sync Recovery Interrupt audio sync recovery when sync reestablished after errors, i.e., when three good frames detected after synchronization lost. This cleared when read. INTRn also asserted unless host sets mask bit. Field Interrupt This after short delay after termination Vertical Sync pulse from PAL/NTSC Encoder. INTRn also asserted unless host sets mask bit. Figure
Compare Interrupt Compare Mask
Register (0x001)
Overflow Interrupt Overflow Mask Begin Vertical Blank Interrupt Begin Active Video Interrupt Compare Audio Interrupt
Read
Reserved
Picture Start Audio Sync Code Detect Code Detect Interrupt Interrupt
Write
Begin Begin Active Vertical Video Mask Blank Mask
Reserved
Picture Start Audio Sync Compare Code Detect Code Detect Audio Mask Mask Mask
Audio Sync Code Detect Interrupt This when Audio Decoder detects valid audio sync code. interrupt intended used synchronization presentation units. This achieved sampling System Clock Reference (SCR) using capture register function SCR. Also this time,
Host Interface Registers
decoder samples channel read pointers maintains audio sync code read address picture start code address. These addresses current read pointers which generally addresses higher than picture start code addresses higher than audio sync code (due size channel FIFOs). These related channel buffer address stored time Packetized Elementary Stream (PES) packet header when packet entered system allow correlating packet particular picture audio frame contained that packet. This cleared when read. INTRn also asserted unless host sets mask bit. Picture Start Code Detect Interrupt This when decoder detects picture start code bitstream. cleared when read. INTRn also asserted unless host sets mask bit. Compare Audio Interrupt This when System Clock Reference (SCR) Compare Audio value Registers (page 4-16) matches current value. Compare Audio value different from main Compare value. This cleared when read. INTRn also asserted unless host sets mask bit. Reserved this when writing Register Begin Active Video Interrupt Video Interface module sets this asserts INTRn masked) beginning active video. This time defined vertical blanking code (Vcode) Start Active Video/End Active Video (SAV/EAV) timing codes programmed into Video Interface. This cleared when read. INTRn asserted host sets mask bit.
Register Descriptions
Begin Vertical Blank Interrupt Video Interface module sets this asserts INTRn masked) beginning vertical blanking interval. This time defined Vcode Start Active Video/End Active Video (SAV/EAV) timing codes programmed into Video Interface. This cleared when read. INTRn asserted host sets mask bit. Overflow Interrupt This when System Clock Reference (SCR) counter (page 4-13) overflows. This cleared when read. INTRn also asserted unless host sets mask bit. Compare Interrupt This when System Clock Reference (SCR) Compare mode enabled match between value stored Compare/Capture registers (page 4-13) current value occurs. This cleared when read. INTRn also asserted unless host sets mask bit. Figure Register (0x002)
Code Video Channel Interrupt Code Video Channel Mask
Read
Video Audio Event Event Interrupt Interrupt
Reserved
Video Audio Pack Data Reserved Data Ready Data Ready Ready Interrupt Interrupt Interrupt
Write
Video Audio Reserved Event Mask Event Mask
Reserved
Video Audio Pack Data Data Ready Data Ready Ready Mask Mask Mask
Pack Data Ready Interrupt This INTRn asserted masked) preparser when detects start pack. interrupt alerts host that pack header, system header, first packet pointer channel buffer. This cleared when read. INTRn asserted host sets mask bit.
Host Interface Registers
Audio Data Ready Interrupt This INTRn asserted masked) preparser when detects audio packet. This cleared when read. INTRn asserted host sets mask bit. Video Data Ready Interrupt This INTRn asserted masked) preparser when detects video packet. This cleared when read. INTRn asserted host sets mask bit. Reserved this when writing this register. Code Video Channel Interrupt This INTRn asserted masked) preparser when detects sequence code video channel. This cleared when read. INTRn asserted host sets mask bit. Reserved this when writing this register. Audio Interrupt When chip Audio Read Compare mode (Register bits page 4-21), channel buffer controller generates single cycle pulse when read pointer channel buffer matches preset value (Registers 111, 112, 113, page 4-28). pulse, internal state machine waits audio sync code, sets this bit, then generates interrupt asserting INTRn output signal. interrupt used audio/video synchronization. This cleared when read. INTRn asserted host sets mask bit. Video Event Interrupt When chip Video Read Compare mode (Register page 4-21), channel buffer controller generates single cycle pulse when read pointer channel buffer matches preset value (Registers 108, 109, 110, page 4-28). pulse, internal state machine waits picture start code, sets this bit, then generates interrupt asserting
Register Descriptions
INTRn output signal. interrupt used audio/video synchronization. This cleared when read. INTRn asserted host sets mask bit. Figure Register (0x003)
Video Channel Buffer Underflow Interrupt Video Channel Buffer Underflow Mask Audio Channel Buffer Underflow Interrupt Audio Channel Buffer Underflow Mask Video Channel Buffer Overflow Interrupt Video Channel Buffer Overflow Mask Audio Channel Buffer Overflow Interrupt Audio Channel Buffer Overflow Mask
Read
Reserved
Reserved
Write
Reserved
Reserved
Audio Channel Buffer Overflow Interrupt This INTRn asserted masked) when Audio channel buffer SDRAM overflows. cleared when read. INTRn asserted host sets mask bit. Video Channel Buffer Overflow Interrupt This INTRn asserted masked) when Video channel buffer SDRAM overflows. cleared when read. INTRn asserted host sets mask bit. Reserved these bits when writing this register. Audio Channel Buffer Underflow Interrupt This INTRn asserted masked) when Audio channel buffer SDRAM underflows (becomes empty). cleared when read. INTRn asserted host sets mask bit. Video Channel Buffer Underflow Interrupt This INTRn asserted masked) when Video channel buffer SDRAM underflows (becomes empty). cleared when read. INTRn asserted host sets mask bit. Reserved these bits when writing this register. [7:6] [2:3]
Host Interface Registers
Figure
Register (0x004)
Channel Buffer Underflow Interrupt Channel Buffer Underflow Mask Packet Error Interrupt Context Error Interrupt Length Error Interrupt
Read
Reserved
Audio Audio Sync Illegal Error Error Interrupt Interrupt
Write
Packet Error Interrupt Mask
Reserved
Audio Audio Sync Context Illegal Length Error Mask Error Mask Error Mask Error Mask
Length Error Interrupt This INTRn asserted masked) when illegal variable length code (VLC) detected bitstream, example: when start code found unexpected location bitstream, when there error run-length parameters supplied IDCT unit. cleared when read. INTRn asserted host sets mask bit. Context Error Interrupt This INTRn asserted masked) when Video Decoder detects parameter bitstream that consistent with context, e.g., illegal value. cleared when read. INTRn asserted host sets mask bit. Audio Illegal Error Interrupt This INTRn asserted masked) Audio Decoder when detects illegal error. cleared when read. INTRn asserted host sets mask bit. Audio Sync Error Interrupt This INTRn asserted masked) when audio sync code expected location bitstream. cleared when read. INTRn asserted host sets mask bit.
Register Descriptions
Reserved these bits when writing this register.
[5:4]
Packet Error Interrupt This INTRn asserted masked) when preparser detects error while processing packet data. When this interrupt occurs, host should read Packet Error Status register (page 4-37) determine which packet error occurred. Packet Error Interrupt cleared when read. INTRn asserted host sets mask bit. Channel Buffer Underflow Interrupt This INTRn asserted masked) when read pointer Audio channel buffer catches write pointer (all buffer data read Formatter). cleared when read. INTRn asserted host sets mask bit. Figure
Reserved
Register (0x005)
VREQ Status AREQ Status Channel Bypass Enable Channel Pause Channel Request Mode Invert Channel Clock
Invert Channel Clock When this set, internal inverted from external clock. default, host interface accepts ACLK signals them together generate internal VALID signal. This assumes that channel data available immediately after rising edge DCK. systems which data available immediately after falling edge DCK, this needs that internal VALID signal generated falling edge DCK. Asynchronous systems ground. Channel Request Mode default, L64105 expects external device sample REQn (AREQn VREQn) signals synchronously with system clock L64105. external device requires REQn signals
Host Interface Registers
synchronous with external device clock (DCK), then Channel Request Mode needs set. this mode, channel internal request sampled twice, first rising edge internal then falling edge internal DCK, before being sent REQn signal. Channel Pause Setting this prevents channel request signals (AREQn VREQn) from being asserted channel data transferred into L64105. external host must clear this reassert REQn signals. Channel Bypass Enable Setting this allows host write data directly channel, bypassing parallel channel input port. Video Audio channel data written into Registers respectively (page 4-16) when this mode. reset, this register defaults i.e., bypass. AREQ Status This when AREQn signal chip asserted. This position read only. VREQ Status This when VREQn signal chip asserted. This position read only. Reserved Figure
Reserved
[7:6]
Register (0x006)
Clear Interrupt
Clear Interrupt This used clear interrupt signal, INTRn, previous pending interrupts. normal operation, events L64105 cause INTRn asserted event mask cleared. bits interrupt registers (Registers through cleared when read host. However, INTRn remains asserted until interrupt registers read (all bits cleared) Clear Interrupt set.
4-10
Register Descriptions
This separate control provided systems with priority interrupts since this will allow driver software exit interrupt handler before completion service higher priority interrupts. While INTRn still asserted, interrupt handler returns interrupt routine L64105 when again highest priority interrupt. Reserved Figure
[7:1]
Register (0x007)
Channel Status Pause Stream Select [1:0] Reserved Channel Start/Reset
Reserved
Software Reset
Channel Status This indicates status channel time. reset power-up, this cleared indicate that channel stopped. When Channel Start command issued (host writes this position), L64105 microcontroller updates this indicating that channel start command been acknowledged channel started. When Channel Reset command issued (host writes this position) L64105 microcontroller updates this indicating acknowledgment Channel Reset command that channel currently stopped. Channel Start/Reset Setting this starts channel. Clearing stops channel. Reserved default value this should overwritten with
Host Interface Registers
4-11
Stream Select [1:0] [3:2] host must program these bits L64105 format input bitstream shown following table.
Stream Select [1:0] 0b00 0b01 0b10 0b11 Bitstream Format Packets MPEG-1 System MPEG-2 Program Stream (Not defined) Elementary Streams
0b11 these bits causes L64105 skip packet searching byte count matching. Video data taken first start code. Subsequent start codes re-establish byte alignment. Audio data byte aligned channel buffer. 0b00 through 0b10, L64105 parses from packet layer resynchronizes preparser packet layer start codes packet layer errors. Pause When set, this prevents Counter (Figure 4.9) from incrementing. However, Counter still written host (override). When this cleared, Counter operates normal mode, i.e., increments with system clock. power-on reset, this initialized
Software Reset When host, this causes L64105 reset (reinitialize). effect same asserting hard reset signal chip, RESETn. This reset function generates 10-clock cycle reset pulse that resets internal modules. host register values reinitialized need reconfigured host proper operation. Reserved [7:6] default value these bits 0b11 should overwritten with 0b00. Reserved [7:0]
Register (0x008)
4-12
Register Descriptions
Figure
Registers 9-12 (0x009-0x00C) Value [31:0]
Value [7:0] Value [15:8] Value [23:16] Value [31:24]
Reg. Reg. Reg. Reg.
These registers contain current value System Clock Reference (SCR) Counter. host must read Register LSB, first. This captures upper bits writes them into Registers host must Pause Register before writing these registers. Figure 4.10 Registers 13-16 (0x00D-0x010) Compare/Capture [31:0]
Reg. Reg. Reg. Reg. Compare/Capture [7:0] Compare/Capture [15:8] Compare/Capture [23:16] Compare/Capture [31:24]
reset, these registers initialized 0xFFFF.FFFF. They configured ways. Compare/Capture Mode Register 0b10, host write value generate interrupt when Counter reaches that value. Compare/Capture Mode 0b01, L64105 captures Counter value event specified host writes value these registers. capture triggered when bits Registers corresponding event occurs.
Host Interface Registers
4-13
Figure 4.11
Capture Video Ready
Register (0x011)
Capture Audio Ready Capture Pack Data Ready Capture Capture Audio Sync Code Capture Picture Start Code
Compare/Capture Mode
Compare/Capture Mode [1:0] value these bits sets operating mode Registers shown following table.
Mode Bits Mode 0b00 0b01 0b10 0b11 compare capture. overflow works. Capture Compare Reserved
Capture Picture Start Code When this L64105 Capture Mode, Counter value captured written Registers through when preparser detects Picture Start Code. Capture Audio Sync Code When this L64105 Capture Mode, Counter value captured written Registers through when preparser detects Audio Sync Code. Capture Beginning Active Video (BAV) When this L64105 Capture Mode, Counter value captured written Registers through when preparser detects Beginning Active Video. Capture Pack Data Ready When this L64105 Capture Mode, Counter value captured written Registers through when preparser detects Pack Data Ready.
4-14
Register Descriptions
Capture Audio Ready When this L64105 Capture Mode, Counter value captured written Registers through when preparser detects Audio Ready. Capture Video Ready When this L64105 Capture Mode, Counter value captured written Registers through when preparser detects Video Ready. Figure 4.12
Reserved
Register (0x012)
Capture Audio Capture Video Reserved
Reserved Clear these bits when writing this register.
[2:0]
Capture Video When this L64105 Capture Mode, Counter value captured written Registers through when preparser detects Decode Time Stamp (DTS) Video. Capture Audio When this L64105 Capture Mode, Counter value captured written Registers through when preparser detects Audio. Reserved Clear these bits when writing this register. Figure 4.13
Reserved
[7:5]
Register (0x013)
Video Start Audio Start Compare Compare
Audio Start Compare When L64105 Compare Mode, setting this generates single-cycle, autostart pulse starting Audio Decoder when current value Counter equal value Compare Audio
Host Interface Registers
4-15
register. This autostart pulse also clears Audio Start Compare bit. Audio Decoder must Pause Mode autostart signal effective. Video Start Compare When L64105 Compare Mode, setting this generates single-cycle, autostart pulse start Video Decoder when current value Counter equal value Compare register. This cleared after autostart signal generated. Reserved Figure 4.14 Registers 20-23 (0x014-0x017) Compare Audio [31:0]
Reg. Reg. Reg. Reg. Compare Audio [7:0] Compare Audio [15:8] Compare Audio [23:16] Compare Audio [31:24]
[7:2]
When Audio Start Compare Register (Figure 4.13) set, Compare/Capture mode Compare, Counter reaches value these registers, autostart pulse generated start Audio Decoder. compare also sets Compare Audio Interrupt (bit Register page 4-4) asserts INTRn signal host masked. Audio Start Compare cleared when compare event occurs. Registers 24-27 (0x018-0x01B) Reserved Figure 4.15
Video Channel Bypass Data [7:0]
[7:0]
Register (0x01C) Video Channel Bypass Data [7:0]
4-16
Register Descriptions
Setting Channel Bypass Enable (bit Register page 4-10) allows host write data directly video channel through this register, bypassing parallel channel input port. Figure 4.16
Audio Channel Bypass Data [7:0]
Register (0x01D) Audio Channel Bypass Data [7:0]
Setting Channel Bypass Enable (bit Register page 4-10) allows host write data directly audio channel through this register, bypassing parallel channel input port. Registers 30-63 Reserved [7:0]
Video Decoder Registers
Figure 4.17
Register (0x040)
Data FIFO Status [1:0] Reserved Data Layer [2:0] Read Only Reset Data FIFO
Data FIFO Status [1:0] [1:0] states these indicate status Data FIFO shown following table. Once "overrun" (0b11) occurs, status stays overrun until register read.
Bits 0b00 0b01 0b10 0b11 Status Empty Data ready Full Overrun
Reset Data FIFO Writing this resets Data FIFO empty. data FIFO this time lost.
Video Decoder Registers
4-17
Data Layer [2:0] [4:2] Data Layer indicates layer origin physical parameter current Data FIFO output. Reading does change FIFO status. Reading current byte Auxiliary Data FIFO Output register (page 4-19) change Data Layer host should always read this layer register before reading FIFO output register. layers defined following table.
Bits 0b100 0b000 0b001 0b010 0b111 Layer Packet Sequence Group pictures Picture Extension layer (picture sequence)
Reserved Figure 4.18
[7:5]
Register (0x41)
User Data FIFO Status [1:0] Reserved User Data Layer [1:0] Read Only Reset User Data FIFO
User Data FIFO Status [1:0] [1:0] following table shows user data FIFO status codes their meanings. Once "overrun" (11) occurs stays overrun until status read.
Bits 0b00 0b01 0b10 0b11 Status Empty Data ready Full Overrun
Reset User Data FIFO Writing this position resets User Data FIFO empty. data currently FIFO lost.
4-18
Register Descriptions
User Data Layer [1:0] [3:2] User Data Layer bits indicate layer origin user data extra data current User Data FIFO output. Reading does change FIFO status. host should always read this layer register before reading FIGO output register. four layers defined following table.
Bits 0b00 0b01 0b10 0b11 Layer Sequence Group pictures Picture Slice
Reserved Clear these bits when writing this register. Figure 4.19
User Data FIFO Output [7:0] Read Only
[7:4]
Register (0x042) User Data FIFO Output [7:0]
User data read host byte time through this read port. When byte read, next byte FIFO loaded into register. also Register Figure 4.20
Data FIFO Output [7:0] Read Only
Register (0x043) Data FIFO Output [7:0]
Auxiliary data read host microprocessor byte time through this read port. When byte read, next byte FIFO loaded into register. also Register
Video Decoder Registers
4-19
Figure 4.21
Register (0x044)
Reset Channel Buffers Error
Reserved
Reset Audio Reset Video Channel Channel Buffer Buffer
Reserved
Reset Audio Reset Video Header/ Header System Channel Channel Buffer Buffer
Reset Channel Buffers Error Setting this causes preparser reset channel buffers detects packet sync error. this cleared, preparser does reset channel buffers packet sync error. Reset Audio Header/System Channel Buffer Setting this resets write pointer Audio Header/System channel buffer buffer start address. read pointer maintained this buffer. Reset Video Header Channel Buffer Setting this resets write pointer Video Header channel buffer buffer start address. read pointer maintained this buffer. Reserved Clear these bits when writing this register. Reset Video Channel Buffer Setting this resets read write pointers Video channel buffer buffer start address. Reset Audio Channel Buffer Setting this resets Audio channel buffer read write pointers read pointer buffer start address. Reserved Clear these bits when writing this register. [4:3]
4-20
Register Descriptions
Figure 4.22
Register (0x045)
Reserved Enable Video Read Compare
Video Numitems/Pics Panic Mode Select
Enable Audio Read Compare
Enable Video Read Compare When this set, Video channel buffer read pointer compared with Video Channel Buffer Compare Address written Registers 108, 109, (page 4-27) host. When addresses match, Video Event Interrupt (Register page 4-6) interrupt generated, masked, asserting INTRn output signal. This used audio/video synchronization host software. When INTRn asserted, host should read Registers through determine cause interrupt, take necessary action, deassert INTRn setting Clear Interrupt (Register page 4-10). Enable Audio Read Compare [1:0] [2:1] encoding meanings shown following table.
Bits 0b00 0b01 0b10 0b11 Description Disable compare Audio decoder read pointer compare IEC958 (S/P DIF) read pointer compare Reserved
When these bits configured compare, selected Audio channel buffer read pointer compared with Audio Channel Buffer Compare Address written Registers 111, 112, (page 4-28) host. When addresses match, Audio Event Interrupt (Register page 4-6) interrupt generated, masked, asserting INTRn output signal. This used audio/video synchronization host software.
Video Decoder Registers
4-21
When INTRn asserted, host should read Registers through determine cause interrupt, take necessary action, deassert INTRn setting Clear Interrupt (Register page 4-10). Video Numitems/Pics Panic Mode Select [1:0] [4:3] This field allows host select "panic" mode shown following table.
Bits 0b00 0b01 0b10 0b11 Description Disable panic feature Video numitems panic mode Pics-in-channel panic mode Reserved
When enabled either Video Numitems Panic Mode Pics-in-channel Panic Mode, Video Decoder suspends decoding when number items (64-bit words) number complete encoded compressed pictures Video channel buffer falls below Video Channel Numitems threshold value written Registers 134, 135, (page 4-32) host. This helps handle potential video channel underflow situations gracefully without interrupting host. During panic situation, display frozen (freeze field) last picture displayed before panic recognized. Reserved Registers (0x046 0x047) Figure 4.23 Reserved [7:5] [7:0]
Registers (0x048 0x049) Video Channel Buffer Start Address [13:0]
Video Channel Buffer Start Address [7:0] Reserved Video Channel Buffer Start Address [13:8]
Reg. Reg.
These registers allow host program Video channel buffer start address. address entered were upper bits 21-bit address conventional address. Memory
4-22
Register Descriptions
Interface L64105 converts address SDRAM address 256-byte boundary SDRAM. This register should only updated while channel stopped (reset). Figure 4.24 Registers (0x04A 0x04B) Video Channel Buffer Address [13:0]
Reg. Reg. Reserved Video Channel Buffer Address [7:0] Video Channel Buffer Address [13:8]
These registers allow host program Video channel buffer address. address entered were upper bits 21-bit address conventional address. Memory Interface L64105 converts address SDRAM address 256-byte boundary SDRAM. This register should only updated while channel stopped (reset). Figure 4.25 Registers (0x04C 0x04D) Audio Channel Buffer Start Address [13:0]
Reg. Reg. Reserved Audio Channel Buffer Start Address [7:0] Audio Channel Buffer Start Address [13:8]
These registers allow host program Audio channel buffer start address. address entered were upper bits 21-bit address conventional address. Memory Interface L64105 converts address SDRAM address 256-byte boundary SDRAM. This register should only updated while channel stopped (reset).
Video Decoder Registers
4-23
Figure 4.26
Registers (0x04E 0x04F) Audio Channel Buffer Address [13:0]
Audio Channel Buffer Address [7:0] Reserved Audio Channel Buffer Address [13:8]
Reg. Reg.
These registers allow host program Audio channel buffer address. address entered were upper bits 21-bit address conventional address. Memory Interface L64105 converts address SDRAM address 256-byte boundary SDRAM. This register should only updated while channel stopped (reset). Figure 4.27 Registers (0x050 0x051) Video Header Channel Buffer Start Address [13:0]
Reg. Reg. Reserved Video Header Channel Buffer Start Address [7:0] Video Header Channel Buffer Start Address [13:8]
These registers allow host program Video Header channel buffer start address. address entered were upper bits 21-bit address conventional address. Memory Interface L64105 converts address SDRAM address 256-byte boundary SDRAM. This register should only updated while channel stopped (reset). Figure 4.28 Registers (0x052 0x053) Video Header Channel Buffer Address [13:0]
Reg. Reg. Reserved Video Header Channel Buffer Address [7:0] Video Header Channel Buffer Address [13:8]
These registers allow host program Video Header channel buffer address. address entered were upper bits 21-bit address conventional
4-24
Register Descriptions
address. Memory Interface L64105 converts address SDRAM address 256-byte boundary SDRAM. This register should only updated while channel stopped (reset). Registers 84-87 (0x054-0x057) Reserved Figure 4.29 Registers (0x058 0x059) Audio Header/System Channel Buffer Start Address [13:0]
Reg. Reg. Reserved Audio Header/System Channel Buffer Start Address [7:0] Audio/System Buff Start Address [13:8]
[7:0]
These registers allow host program Audio Header/System channel buffer start address. address entered were upper bits 21-bit address conventional address. Memory Interface L64105 converts address SDRAM address 256-byte boundary SDRAM. This register should only updated while channel stopped (reset). Figure 4.30 Registers (0x05A 0x05B) Audio Header/System Channel Buffer Address [13:0]
Reg. Reg. Reserved Audio Header/System Channel Buffer Address [7:0] Audio Header/System Channel Buffer Address [13:8]
These registers allow host program Audio Header/System channel buffer address. address entered were upper bits 21-bit address conventional address. Memory Interface L64105 converts address SDRAM address 256-byte boundary SDRAM. This register should only updated while channel stopped (reset). Registers 92-95 (0x05C-0x05F) Reserved [7:0]
Video Decoder Registers
4-25
Figure 4.31
Registers 96-98 (0x060-0x062) Video Channel Buffer Write Address [19:0]
Reg. Reg. Reg.
Video Channel Buffer Write Address [7:0] Read Only Video Channel Buffer Write Address [15:8] Read Only Reserved Video Channel Buffer Write Address [19:16] Read Only
These registers contain current write pointer address Video channel buffer. should read first. since this captures next significant byte Registers These should then read immediately ensure that correct captured value read. When set, most significant (bit Register indicates that write pointer wrapped around from address start address buffer. Figure 4.32 Registers 99-101 (0x063-0x065) Audio Channel Buffer Write Address [19:0]
Reg. Reg. Reg.
Audio Channel Buffer Write Address [7:0] Read Only Audio Channel Buffer Write Address [15:8] Read Only Reserved Audio Channel Buffer Write Address [19:16] Read Only
These registers contain current write pointer address Audio channel buffer. should read first. since this captures next significant byte Registers 101. These should then read immediately ensure that correct captured value read. When set, most significant (bit Register 101) indicates that write pointer wrapped around from address start address buffer.
4-26
Register Descriptions
Figure 4.33
Registers 102-104 (0x066-0x068) Video Header Channel Buffer Write Address [19:0]
Reg. Reg. Reg.
Video Header Channel Buffer Write Address [7:0] Read Only Video Header Channel Buffer Write Address [15:8] Read Only Reserved Video Header Channel Buffer Write Address [19:16] Read Only
These registers contain current write pointer address Video Header channel buffer. should read first. since this captures next significant byte Registers 104. These should then read immediately ensure that correct captured value read. When set, most significant (bit Register 104) indicates that write pointer wrapped around from address start address buffer. Registers 105-107 (0x069-0x06B) Reserved Figure 4.34 Registers 108-110 (0x06C-0x06E) Video Channel Buffer Read Address [19:0]
Reg. Reg. Reg.
[7:0]
Video Channel Buffer Read Address [7:0] Read Only Video Channel Buffer Read Address [15:8] Read Only Reserved Video Channel Buffer Read Address [19:16] Read Only
These registers contain current read pointer address Video channel buffer. should read first since this

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