APEX 20KC 7000B Devices October 2001, ver. Introduction

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APEX 20KC 7000B Devices October 2001, ver. Introduction

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Using Selectable Standards APEX 20KE,
APEX 20KC 7000B Devices
October 2001, ver.
Introduction
High-performance, low-voltage standards have been introduced keep pace with increasing clock speeds, higher data rates, low-voltage devices. These standards used interface with memory, microprocessors, backplanes, peripheral devices. Designers want these standards with programmable logic need flexible, high-performance, multi-standard buffers. Altera's revolutionary APEX20KE APEX 20KC devices offer highest density, highest performance programmable logic solution with necessary standards communication computer industries. Altera® MAX® 7000B devices product-term leader standard support: 7000B devices only macrocell-based devices support GTL+, 2.5-V SSTL-2, 3.3-V SSTL-3. With programmable standards supported APEX 20KE 7000B devices, single device simultaneously support multiple standards, well interface with high-speed, low-voltage memory buses backplanes. These standards include LVDS, which supports data rates megabits second (Mbps). Embedding standard support programmable logic devices (PLDs) simplifies board design. Dedicated circuitry like LVDS transceivers integrated into PLDs, saving board space, reducing usage, improving performance. This application note provides guidelines designing with selectable standards Altera devices covers following topics:
Overview standards applications APEX 20KE, APEX 20KC 7000B standard support Operating conditions Board termination schemes APEX family standard software support
Overview Standards Applications
ability PLDs support industry standards gives customers quick time-to-market design solution. This section provides overview typical applications selectable standards supported Altera devices. specifications each standard listed this section.
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117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
LVTTL
LVTTL standard single-ended, general-purpose standard 3.3-V applications. LVTTL interface defined JEDEC Standard JESD 8-A, Interface Standard Nominal V/3.3 Supply Digital Integrated Circuits. LVTTL output buffer push-pull driver. This standard requires output buffer drive (minimum does require input reference voltages termination. APEX 20K, APEX 20KE, 7000B devices compliant with this standard. maximum recommended input voltage APEX 7000B devices which exceeds 3.9-V requirement this specification.
LVCMOS
LVCMOS standard defined JEDEC Standard JESD 8-A, Interface Standard Nominal V/3.3 Supply Digital Integrated Circuits. LVCMOS single-ended general-purpose standard also used 3.3-V applications. input buffer requirements same LVTTL requirements, output buffer required drive rail (minimum VCCIO This standard requires 3.3-V supply voltage (VCCIO), input reference voltages termination. APEX 20K, APEX 20KE, APEX 20KC 7000B devices compliant with LVCMOS standard.
2.5-V standard documented JEDEC Standard JESD 8-5, (Normal Range) (Wide Range) Power Supply Voltage Interface Standard Nonterminated Digital Integrated Circuit. This standard similar LVCMOS used 2.5-V power supply levels. APEX 20K, APEX 20KE, APEX 20KC 7000B devices compliant with this standard, which requires 2.5-V VCCIO, input reference voltages termination.
1.8-V standard documented JEDEC Standard JESD 8-7, 0.15 (Normal Range) 1.95 (Wide Range) Power Supply Voltage Interface Standard Nonterminated Digital Integrated Circuit. This standard similar LVCMOS used 1.8-V power supply levels reduced input output thresholds. APEX 20K, APEX 20KE, APEX 20KC 7000B devices compliant with this standard, which requires 1.8-V VCCIO, input reference voltages termination.
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3.3-V
APEX 20K, APEX 20KE APEX 20KC devices compliant with Local Specification, Revision 3.3-V operation. standard supports 64-bit width operation MHz. This standard uses LVTTL-type input output buffers requires 3.3-V VCCIO input reference voltages termination. 7000B devices compliant with aspects this standard except that they offer clamps VCCIO.
PCI-X
PCI-X standard enhanced version standard that support higher average bandwidth more stringent requirements. APEX 20KE APEX 20KC drivers meet requirements PCI-X. Quartus IIsoftware, buffer setting support PCI-X requirements, including overshoot clamp. future version Quartus software will include ability choose PCI-X standard.
LVDS
LVDS standard used very high-performance, low-power-consumption data transfer. industry standards define LVDS: IEEE 1596.3 SCI-LVDS ANSI/TIA/EIA-644. Both standards have similar features, IEEE standard supports maximum data transfer Mbps. APEX 20KE devices designed meet ANSI/TIA/EIA-644 requirements Mbps. LVDS standard requires 3.3-V VCCIO termination resistor between traces input buffer. input reference voltage required.
more information LVDS, Altera site http://www.altera.com.
LVPECL
LVPECL standard differential standard that similar LVDS. APEX 20KE devices support LVPECL standard using pins LVDS mode with external resistor network.
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GTL+
GTL+ standard high-speed standard first used Intel Corporation interfacing with Pentium processor often used processor interfacing communication across backplane. GTL+ voltage-referenced standard requiring 1.0-V input reference voltage (VREF) board termination voltage (VTT) GTL+ standard open-drain standard that requires minimum VCCIO supply voltage APEX 20KE 7000B devices compliant with this standard.
SSTL-2 Class
SSTL-2 standard, specified JEDEC Standard JESD 8-9, Stub-Series Terminated Logic Volts (SSTL-2), voltage-referenced standard requiring 1.25-V VREF, 2.5-V VCCIO, 1.25-V VTT. SSTL-2 used high-speed SDRAM interfaces. APEX 20KE, APEX 20KC 7000B devices compliant with this standard.
SSTL-3 Class
SSTL-3 standard, specified JEDEC Standard JESD 8-8, Stub-Series Terminated Logic Volts (SSTL-3), voltage-referenced standard requiring 1.5-V VREF, 3.3-V VCCIO, 1.5-V VTT. SSTL-3 used high-speed SDRAM interfaces. APEX 20KE, APEX 20KC 7000B devices compliant with this standard.
HSTL Class
HSTL standard, specified JEDEC Standard JESD 8-6, High-Speed Transceiver Logic (HSTL), output buffer supply voltage based interface standard digital integrated circuits. HSTL voltage-referenced standard requiring 0.75-V VREF, 1.5-V VCCIO, 0.75-V VTT. APEX 20KE APEX 20KC devices support HSTL Class operation with VCCIO voltage APEX 20KE APEX 20KC devices drive compliant levels with VCCIO
standard specified Advanced Graphics Port Interface Specification Revision introduced Intel Corporation graphics applications. voltage-referenced standard requiring 1.32-V VREF 3.3-V VCCIO does require termination. APEX 20KE APEX 20KC devices support interface.
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117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
standard specified JEDEC Standard JESD 8-4, Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface Standard Digital Integrated Circuits. voltage-referenced standard requiring 1.5-V VREF, 3.3-V VCCIO, 1.5-V VTT. standard superset LVTTL LVCMOS. receivers compatible with LVCMOS LVTTL standards. drivers, when unterminated, compatible with specifications LVCMOS LVTTL.
APEX 20KE 7000B Standards Support
APEX 20KE blocks support standards only PLDs industry with LVDS. 7000B devices provide support GTL+, SSTL-2, SSTL-3, unique feature among product-term-based PLDs. programmable input/output element (IOE) blocks both APEX 20KE 7000B devices have individual power supplies with separate supply voltage (VCCIO) pins each block. VCCIO supply supports 3.3-V, 2.5-V, 1.8-V levels.
APEX 20KE 7000B Standards
APEX 20KE 7000B buffers meet voltage, drive strength, characteristics necessary comply with standards listed Table
Altera Corporation
117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
Table APEX 20KE 7000B Supported Standards Standard Device APEX 20KE 7000B v(2) Type Input Output Supply Board Reference Voltage Termination Voltage (VCCIO) Voltage (VREF) (VTT)
1.25 0.75 1.32 1.25 0.75
LVTTL LVCMOS PCI-X LVDS LVPECL GTL+ SSTL-2 Class SSTL-3 Class HSTL Class Notes:
Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Differential Differential Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced
values shown VREF, VCCIO, typical values. 7000B devices have diode clamp CCIO. These devices comply with other 64-bit/66-MHz 3.3-V specifications. APEX 20KE devices drive HSTL-compliant signal levels with CCIO corrected 1.8-V supply.
Each standard different VREF, VTT, VCCIO requirements. more information, refer "Board Termination Schemes" page
APEX 20KE Standards
banks APEX 20KE devices support standards first programmable logic devices (PLDs) industry with dedicated LVDS circuitry. APEX 20KE devices FineLine BGApackages have eight programmable banks LVDS blocks (one transmitter block receiver block) within banks. programmable input/output element (IOE) banks APEX 20KE devices have individual power planes with separate supply voltage (VCCIO) pins each bank. VCCIO supply supports 3.3-V, 2.5-V, 1.8-V levels.
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117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
APEX 20KE devices FineLine packages have eight programmable blocks LVDS blocks. Figure shows representation blocks. APEX 20KE designs that LVDS, LVDS blocks used other standard. Figure APEX 20KE Blocks
Bank Bank
Bank
LVDS Output Block Bank
Regular Banks Support LVTTL LVCMOS PCI-X GTL+ SSTL-2 Class SSTL-3 Class HSTL Individual Power
Bank LVDS Input Block
Bank
Bank
Bank
Note:
first pins that border LVDS blocks only used input maintain acceptable noise level VCCIO supply. LVDS input output blocks used LVDS, they support standards used input, output, bidirectional pins with VCCIO
7000B Standards
Each 7000B device programmable blocks. Each block configured independently utilize standards supported 7000B devices. Additionally, standards with common VCCIO voltages simultaneously within single block. Each programmable block power supply with separate VCCIO pins support 3.3-V, 2.5-V, 1.8-V voltage levels. Figure shows representation 7000B programmable blocks.
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117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
Figure 7000B Banks
Notes (1), (2),
Programmable Banks
LVTTL LVCMOS 3.3-V GTL+ SSTL-2 Class SSTL-3 Class Individual Power
Notes:
input referenced available VREF levels. 7000B devices have VREF pins that referenced both blocks. output drivers dependent VCCIO. VCCIO pins each block powered different voltage.
Operating Conditions
Tables through list operating specifications supported standards. These tables list minimal specifications only. APEX 20KE 7000B devices exceed these specifications. Consult individual device data sheets details.
Table LVTTL Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Maximum
VCCIO
Units
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117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
Table LVCMOS Specifications Symbol
VCCIO
Parameter
Power supply voltage range High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Maximum
VCCIO
Units
VCCIO -0.1 VCCIO
VCCIO
Table 2.5-V Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage
Conditions
Minimum
2.375 -0.3
Maximum
2.625 VCCIO
Units
-0.1
Low-level output voltage
Table 1.8-V Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
Maximum
0.35 VCCIO
Units
0.65 VCCIO VCCIO VCCIO 0.45 0.45
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117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
Table 3.3-V Specifications Symbol
VCCIO
Parameter
supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
VCCIO -0.5
Typical
Maximum
VCCIO VCCIO VCCIO
Units
VCCIO IOUT -500 IOUT 1,500
VCCIO
Table 3.3-V PCI-X Specifications Symbol
VCCIO VIPU Lpin
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage Input leakage current High-level output voltage Low-level output voltage Inductance
Conditions
Minimum
VCCIO -0.5 VCCIO
Typical
Maximum
VCCIO 0.35 VCCIO 10.0 VCCIO 15.0
Units
VCCIO Iout -500 Iout 1500
-10.0 VCCIO
Table 3.3-V LVDS Specifications Symbol
VCCIO
Parameter
supply voltage Differential output voltage Change between high Output offset voltage Change between high Differential input threshold Receiver input voltage range Receiver differential input resistor (external APEX devices)
Conditions
Minimum
3.135
Typical
Maximum
3.465
Units
1.125
1.25
1.375
-100
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Table GTL+ Specifications Symbol
VREF
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.35 0.88 VREF
Typical
Maximum
1.65 1.12 VREF
Units
0.65
Table SSTL-2 Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF 0.04 1.15 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
2.625 VREF 0.04 1.35 VCCIO VREF 0.18 0.57
Units
-7.6
0.57
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117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
Table SSTL-2 Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF 0.04 1.15 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
2.625 VREF 0.04 1.35 VCCIO VREF 0.18 0.76
Units
-15.2 15.2
0.76
Table SSTL-3 Class Specifications Symbol
VCCIO VREF
Parameter
Supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.05 VREF -0.3
Typical
VREF
Maximum
VREF 0.05 VCCIO VREF
Units
Table SSTL-3 Class Specifications Symbol
VCCIO VREF
Parameter
Supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.05 VREF -0.3
Typical
VREF
Maximum
VREF 0.05 VCCIO VREF
Units
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117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
Table HSTL Class Specifications Symbol
VCCIO VREF
Parameter
Supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 VREF 0.05 0.68 VREF -0.3
Typical
VREF 0.75
Maximum
1.89 VREF 0.05 0.90 VCCIO VREF
Units
VCCIO
Table LVPECL Specifications Symbol
VCCIO tDSKEW
Parameter
Output Supply Voltage Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Input Voltage Differential Output Voltage Differential Rise/Fall Time 80%) Differential Skew Output Load Receiver differential input resistor
Minimum
3.135 1300 2100 1450 2275
Typical
Maximum
3.465 1700 2600 1650 2420
Units
Table 3.3-V Specifications Symbol
VCCIO VREF
Parameter
supply voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current
Conditions
Minimum
3.15 0.39 VCCIO VCCIO
Typical
Maximum
3.45 0.41 VCCIO VCCIO VCCIO VCCIO
Units
IOUT -500 IOUT 1500 VCCIO
VCCIO
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Table Specifications Symbol
VCCIO
Parameter
supply voltage
Conditions
Minimum
1.35 VREF
Typical
Maximum
1.65
Units
VTT/VREF Termination reference voltage High-level input voltage Low-level input voltage Input leakage current VCCIO High-level output voltage Low-level output voltage Output leakage current (when output high VOUT VCCIO
VREF VREF VREF
Note:
VREF specifies center point switching range.
Board Termination Schemes
various standards supported APEX 20KE 7000B devices require specific termination schemes achieve their high speeds. Each standard individual termination scheme. diagram Figure shows series parallel termination resistors that used with standards. Figure Board Termination Diagram
Driving Device Receiving Device
VREF
LVDS standard requires termination resistor between signals receiving device shown Figure termination resistor should match differential load impedance ranging from typically
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Figure LVDS Board Termination Receiver
Transmitting Device Receiving Device
Table shows board termination values reference voltages that each APEX 20KE standard uses. Table Board Termination Values Standard
GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class HSTL Class
Output Driver
Open-drain Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull
VREF
1.25 1.25 0.75 1.32
1.25 1.25 0.75
7000B Software Support
Software Support 7000B Devices
Selectable standards programmable basis both APEX 20KE 7000B devices. APEX 20KE devices have total blocks, including LVDS blocks. LVDS blocks also used other standards when used LVDS. 7000B devices have blocks; standards supported 7000B devices shown Table page QuartusII MAX+PLUS® software tools define standard used each block. Software support 7000B devices selectable standards provided MAX+PLUS software version higher. This document explains Quartus software's support selectable standards. information MAX+PLUS software supports these standards, contact Altera Applications.
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APEX Family Standard Software Support
This section shows implement view selectable standards APEX family Quartus software gives placement assignment guidelines. following topics will discussed:
Device Options dialog Assignments dialog Representation banks standards floorplan editor Automatic placement verification selectable standards with Quartus software Guidelines selectable standards VREF placement guidelines
Device Options Dialog
Voltage Device Options dialog (Compiler Settings dialog box) contains Default Standard drop-down menu, which used default standard device. pins without specific standard assignment will default standard specified this drop-down menu. drop-down menu following options APEX 20KE devices:
LVTTL (default setting) LVCMOS PCI-X (supported future version Quartus software) LVDS LVPECL (supported future version Quartus software) GTL+ SSTL-2 Class SSTL-3 Class HSTL Class (supported future version)
options available APEX devices drop-down menu follows:
LVTTL LVCMOS (default setting) 3.3-V
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Figure shows Device Options dialog (Compiler Settings dialog box) when targeting APEX 20KE device. Figure Device Options Dialog APEX 20KE Devices
Assignments Dialog
Assignments dialog box, designers make assignments, specify standards, VREF assignments, view settings made each pin.
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Figure shows Assignments dialog box. Number column corresponds with number specified package. Name column contains user-specified name design. There relevant columns note: Bank Standard. Type column Available Pins Existing Assignments list displays following types: I/O, Column I/O, VREF, Reserved, dual-purpose names. list sortable column clicking column heading. There drop-down menus making standard reserved assignments pin-by-pin basis. VREF pins assigned same reserved pins. select standard VREF pins, choose standard from standard drop-down menu. assign VREF, enter name (reserve names declared design file), check Reserve box, select reserve VREF from drop-down menu. Figure Assignments Dialog
Follow steps below make assignments, designate standard types, reserve pins. Designers should reserve pins that needed future.
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have already done open create project that want modify. Choose Compiler Settings (Processing menu). Click Chips Devices tab. Select target device Available devices list. Click Assign Pins. Assignments dialog box, show pins which cannot assign node name Available pins existing assignments list, select Show connect pins. Available pins existing assignments list, select number which want assign, change, delete node name assignment. delete node name assignment from pin, under Assignment, click Delete. assign node name pin, change existing node name assignment pin, under Assignment, type node name name Copy node name Assignments dialog with Node Finder.
added changed node name assignment want assign Standard pin, under Assignment, select standard from Standard list. added changed node name assignment standard want reserve future use, under Assignment, turn Reserve (even does exist design file), select input tri-stated, output driving ground, output driving unspecified signal, VREF from list. save assignment assignment Available pins existing assignments list, under Assignment, click Add. save changed assignment assignment Available pins existing assignments list, under Assignment, click Change. Repeat steps each additional assignment want make, change, delete. Click
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Representation Banks Standards Floorplan Editor
Floorplan Editor supports many features APEX 20KE devices, including multiple standards, PLLs, LVDS transmitter receiver block. Floorplan Editor shows membership banks using unique background fill color around each each bank. addition, bank number shown. Floorplan editor package views (Package Package Bottom) three internal views (Interior MegaLABTM, Interior LABs Interior Cells). package views bank number labeled above pin-grid array (PGA) packages, inside device quad flat pack (QFP) packages. interior views, outside package background around name. Only VCCIO pins have colored background; GNDINT, GNDIO, VCCINT pins not, they specific particular bank. Figure shows coloring Floorplan Editor EP20K600E device (1,020-pin FineLine device package) package view. Figure Package View with Show Banks
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Under View pull-down menu Floorplan Editor, Show Banks option controls displays bank colors. This command also turns display both bank colors bank numbers three interior views. Floorplan Editor Color Legend, located under View pull-down menu, entry each bank color, shown Figure output clock feedback pins PLL1 PLL2 reside Bank Bank support standards supported APEX 20KE devices. Figure Color Legend Window Floorplan Editor
Figure shows portion package view EP20K100E device Banks 240-pin plastic quad flat pack (PQFP) package Floorplan Editor. PQFP packages, eight banks have been merged into merged banks. VCCIO planes merged banks internally connected PQFP packages. naming convention merged banks lists real bank that belongs then lists bank with which shares VCCIO. bank Bank6 (Bank7) share VCCIO with Bank7 (and Bank6), different VREF bus. This allows Bank6 (and Bank7) used voltage-referenced standard Bank7 (and Bank6) another because they have separate VREF buses, long those standards same level. example, Bank6 (and Bank7) implement GTL+ while Bank7 (and Bank6) implements SSTL-3 Class
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Figure View 240-Pin PQFP Package
Figure shows internal cells view APEX 20KE device's support. diamond next dedicated clocks indicates that used.
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Figure View Internal Cells Floorplan Editor
dedicated clock pins (CLK1p, CLK2p, CLK3p, CLK4p) support LVDS have optional dual-purpose negative polarity pins associated with them. feedback pins (CLKLK_FB1p, CLKLK_FB2p) output pins (CLKLK_OUT1p, CLKLK_OUT2p) also support LVDS following same convention dedicated clock pins. Figure shows LVDS receiver Floorplan Editor. receiver data channel, represented LVDSRX01p LVDSRX01n, feeds dedicated serial-to-parallel converter. LVDS clock (LVDSRXINCLK1p, LVDSINCLK1n) clocks serial-to-parallel converter. serial-to-parallel converter shown filled rectangle adjacent register associated with each positive polarity LVDS data clock pin.
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Figure Internal Cells View LVDS Receiver
Guidelines Selectable Standards
following guidelines should used when designing selectable standards APEX 20KE devices. guidelines define which standards compatible based input, output, bidirectional types within bank.
input pins placed same bank their standards require different VREF voltage. However, non-voltage-referenced standards coexist with voltage-referenced standards; e.g., bank support GTL+ LVTTL. PQFP packages, merged banks still support separate VREF inputs each bank. example, Bank1 Bank8 merged together, bank support GTL+ while Bank8 support SSTL-3. push-pull standard output pins placed same bank they require different VCCIO voltage level. output pins have same VCCIO level merged banks PQFP packages. GTL+ open-drain standard therefore assigned banks with 2.5-V 3.3-V VCCIO level.
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clamp diode affects input tolerance. When clamp diode turned clamped VCCIO. example, 2.5-V VCCIO bank without clamp diode tolerant 3.3-V inputs. However, when clamp turned 2.5-V VCCIO bank 3.3-V tolerant. LVTTL input that does have clamp diode turned placed bank that 2.5-V VCCIO level. Bidirectional pins have satisfy both input output guidelines. output drivers between GNDIO pins should sink more current than total. Pins using 1.8-V standard current limited. current requirement standards with 3.3-V 2.5-V VCCIO levels defined follows: VCCIO GTL+ LVTTL ILVTTL) 1.5) LVCMOS ILVCMOS) SSTL-3 class (SSTL-3 class LVDS 4.5) 1.5) Where ILVTTL (4-mA default value) LVCMOS (0.1 default value) current sink LVTTL LVCMOS pins, respectively. your system requires higher LVTTL LVCMOS pins (for example, termination) then adjust equation accordingly. VCCIO 2.5V SSTL-2 class 7.6) SSTL-2 class 15.2) practice, this rule applies only SSTL-2 Class SSTL-3 Class GTL+, LVCMOS LVTTL pins which sink more than output pin. other standards, every used without violating this requirement. APEX Programmable Logic Device Family Data Sheet shows relationship pins GNDIO pins enable correct placement. This also shown Quartus software's Floorplan Editor Quartus Help.
When placing VREF pins, follow these guidelines. Output pins that switch while input using VREF have placed distance pads away from VREF pin, distance away from VREF between them power (VCC GND) pad. Figure shows both cases. Multiple VREF pins used bank same standards. Further VREF guidelines discussed "I/O VREF Placement Guidelines" page
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Figure Examples VREF Placement
VREF input pins
VREF Power
Multiple VREF pins should considered bank
VREF Power
VREF
Automatic Placement Verification Selectable Standards With Quartus Software
Quartus software verifies correct placement VREF pins, following same rules outlined "Guidelines Selectable Standards" page
Designers must assign VREF pins voltage-referenced pins. Quartus software automatically places pins different VREF standards without assignments separate banks. Quartus software verifies that voltage-referenced pins requiring different VREF LVDS levels placed bank. Quartus software ensures that requiring VREF more than pins from VREF pin. voltage-referenced pins placed only side VREF staggered both sides VREF pin. Quartus software reports error message current limitation exceeded between GNDIO pins. uses equations documented "Guidelines Selectable Standards" page Quartus software ensures that more than voltage referenced standard pins using single VREF.
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Quartus software does allow place output within pins VREF power does separate them. view orientation, Show Pads view Floorplan Editor. Quartus software will reserve unused LVDS channels LVDS transmitter receiver blocks when LVDS channels being used. will also reserve pins adjacent LVDS blocks that share VCCIO with LVDS blocks. Quartus software will allow placement non-LVDS output pins within pins (with common VCCIO pin) LVDS blocks.
VREF Placement Guidelines
This section discusses VREF placement guidelines when designing with buses. Each VREF support eight voltage-referenced input pins each side, input pins total, shown Figure Quartus software will give error message voltage-referenced input placed more than pads from VREF pin. Figure Each VREF Support Input Pins
Output pins should placed more pins away from VREF pins, except when VREF next power pin. that case power isolates VREF from switching output. Output pins placed other side power pin, shown Figure
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Figure VREF Placement Guidelines
VREF
Inputs
Inputs Ouputs
VREF
Voltage-referenced bidirectional buses that share single tri-state control signal placed around VREF pin, shown Figure This works because only operating direction time. When bidirectional pins driving out, inputs using VREF pin. When bidirectional pins accepting input signals, there output pins that would interfere with input pins' ability VREF level. Figure Placement Bidirectional Buses with Single Control
VREF
VREF
Output pins placed outside without affecting VREF bidirectional bus, shown Figure Furthermore, unrelated output placed within voltage-referenced bidirectional output more than pads from VREF separated power pin.
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Figure Placement Output Pins Outside Bidirectional Buses
VREF
These outputs affect inputs bidirectional pins VREF
Output pins also placed inside they more than pins away from VREF pin, shown Figure Figure Output Placement Bidirectional
VREF
This output affects input bidirectional pins when within pins VREF unless separated power VREF
Place outputs more pins from VREF
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117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
Conclusion
advanced programmable features standards simplify board design minimizing number devices used interface with memory, microprocessors, backplanes. APEX 20KE devices, which 64-bit, 66-MHz compliant, support programmable standards, allowing customization wide variety applications. Input, output, bidirectional pins different standards intermixed with banks following guidelines this document. APEX 20KE devices also offer increased performance with standards features like LVDS (840 Mbps data transfer).
References
Interface Standard Nominal V/3.3 Supply Digital Integrated Circuits, JESD8-A, Electronic Industries Association, June 1994. Stub-Series Terminated Logic Volts (SSTL-3), EIA/JESD8-8, Electronic Industries Association, August 1996. Stub-Series Terminated Logic Volts (SSTL-2), EIA/JESD8-9, Electronic Industries Association, September 1998. Electrical Characteristics Voltage Differential Signaling (LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National Standards Institute/Telecommunication Industry Association/Electronic Industries Association. ±0.2 (Normal Range) (Wide Range) Power Supply Voltage Interface Standard Nonterminated Digital Integrated Circuit, EIA/JESD8-5, Electronic Industries Association, October 1995. ±0.15 (Normal Range) 1.95 (Wide Range) Power Supply Voltage Interface Standard Nonterminated Digital Integrated Circuit, EIA/JESD8-7, Electronic Industries Association, February 1997. Local Specification, Revision 2.2, Special Interest Group, December 1998.
Revision History
information contained Application Note (Using Selectable I/OStandards APEX 20KE, APEX 20KC 7000B Devices) version supersedes information published previous versions. Application Note (Using Selectable I/OStandards APEX 20KE, APEX 20KC 7000B Devices) version contains folllowing change: title been changed throughout document.
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117: Using Selectable Standards APEX 20KE, APEX 20KC 7000B Devices
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APEX 20KC 7000B Devices October 2001, ver. Introduction

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