QDRTM: Introduction evolution newer systems increased demands spe

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QDRTM: Introduction evolution newer systems increased demands spe

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Interfacing QDRwith Altera APEX20KE
QDRTM: Introduction
evolution newer systems increased demands speed performance. result this, faster processors have emerged that have increased demands memory performance. Newer memory architectures with higher through-put have been designed that support current systems processors. This application note introduces QDRarchitecture, SRAM architecture designed improve SRAM interface bandwidth much four times current solutions. This application note also shows this high performance SRAM interfaced Altera APEX 20KE FPGA. family synchronous SRAMs with innovative architecture designed especially high-performance-netwroking systems co-development team, comprised Cypress, IDT, Micron. stands Quad Data Rate, which effectively means that words data transferred through SRAM single clock cycle. Family (currently 1/01) includes devices, which differ number data words that will burst every access. Table shows current planned devices family.
Address /BWS0, /BWS1 /WPS Data
Write Port
Data
256Kx18 256Kx18 Memory Memory Array Array
Read Port
Data
/RPS Data
Vref
Control Logic
Figure Block Diagram CY7C1302V25 CY7C1302V25 Block Diagram CY7C1302V25 shows block diagram CY7C1302V25 device. SRAM family members: two-word burst device (CY7C1302V25) four-word burst device (CY7C1304V25). difference between number words data that obtained from SRAM single read provided SRAM write. block diagram Timing Diagram CY7C1302V25 CY7C1302V25. Data ports seperated read write ports. address lines shared read write ports. Data transferred Double Data Rate manner (DDR) both input output ports. This allows four words data transferred every clock cycle. Description Inputs SRAM Clock Inputs SRAMs have four clocks: clocks used sampling inputs clocks used clock data from SRAM. transactions initiated rising edge Control Inputs SRAMs have very simple control structure. control signals: (Read Port Select) (Write Port Select) used control read write operations SRAM. These signals sampled rising edge clock. More information these will provided later sections. Address Inputs address inputs common read write ports. CY7C1304V25 addresses samples alternate cycles clock read write. CY7C1302V25 address inputs sampled rising edge read rising edge write.
Table Devices QDRFamily Device CY7C1302V25 CY7C1304V25 What QDR? Most existing SRAM's solutions optimized applications, with interfaces designed move data efficiently PC-type common applications. most networking applications continous movement data through SRAM neccesity. such applications, there continous transitions between read writes through memory. Common devices like standard synchrounous pipelined SRAMs perform well under these conditions. LatencySRAMs have optimized synchronous SRAM architecture allow latency read/write transitions have 100% utilization bus. most networking applications, this improvement throughput enough. applications that need have read write done simultaneously, will benefit tremedously from SRAM. Applications such Aswitches routers will benefit from fact that simultaneous reads write done SRAM with latency data through SRAM guaranteed even simultaneous access same address location. more details refer application note "QDR: Next Generation High-Performance Networking SRAM." SIze 512K 512K Description Burst Burst
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134
408-943-2600 March 2001
Interfacing QDRTMwith Altera APEX20KE
Data Inputs/Outputs data lines unidirectional. words transferred from every cycle. More details functionality device explained section timings. Timings Timing Diagram CY7C1302V25 shows timing diagram CY7C1302V25, word burst device QDR.
Figure Performance comparison Read/Write
SRAM Bandwidth Gb/s
10.00
Pipe-166 NoBL-166 5.00 DDR-166 QDR-166
/WPS /RPS Add. Data Data
D(B)
0.00 Cache Networking
D(B)+1
D(D)
D(D)+1
D(F)
D(F)+1
D(H)
D(H)+1
Memory Controller SRAMs simplify process designing interface SRAM, memory controller developed using Altera APEX 20KE FPGA. block diagram memory controller shown Performance comparison QDR. Figure Performance comparison
Q(A) Q(A)+1
Q(C) Q(C)+1 Q(E)
Figure Timing Diagram CY7C1302V25 first clock cycle, both asserted active LOW. address read latched rising edge clock address write latched rising edge clock. data write address also latched rising edges clock (D(B)) clock (D(B+1). byte writes also latched same clock data. Read accesses CY7C1302V25 conducted cycles 2-stage pipeline). During first cycle address latched rising edge clock. address then presented memory. next rising edge clocks first 18-bit data word (Q(A)). next rising edge clocks second 18-bit data word (Q(A+1)). seen from timing diagram, could start read write same address same cycle. When such operation occurs, forwards write write port ensures that valid data driven data bus. doing data coherency guaranteed. Performance Comparision Performance comparison Read/Write shows performance comparison against other SRAMs. comparison done assuming that interfaces operate Mhz. performance ahead other SRAMs performance closest device networking application.
Radd data Rdata BWS(0,1)
SRAM#1
Altera
APEX 20KE
A[0:17] Din[0:17] Dout[0:17]
SRAM#2
emory Controller
RPS/WPS Clocks Feedback
SRAM#3
Rest system SRAM#4
A[0:17] Din[0:17] /RPS Dout[0:17]
QDR_2
memory controller designed control four SRAMs depth expanded fashion. Each SRAMs receive seperate control signals read write ports, while
Interfacing QDRTMwith Altera APEX20KE
address data ports common SRAMs. SRAMs form bank memory controller generates control signals memory array, memory controller views complete SRAM bank like unified memory array. supports concurrent double data rate operation inputs outputs, also allows byte write operation memory bank. memory controller assumes that SRAMs single clock mode. This simplify memory interface. operates Mhz, allowing bandwidth Gbits/s. memory controller independent read write state machines. memory controller command based interface with two-bit command input. This memory controller shows interface between APEX CY7C1302V25. memory controller modified interface 4-word burst device, CY7C1304V25.
signals needed specified Table these generated Altera FPGA. Because interface between APEX device high speed, some timing issues arise. Timing critical timing parameters are: Set-up/Hold window write. Set-up/Hold window APEX read. following sections discuss each these seperately. Write Cycle Time When designing proper write cycle timing, meeting set-up hold requirements SRAM primary concern. Set-up hold specifications CY7C1302V25 (100-MHz speed grade) each. Both clock data signals driven from controller, clock-to-output delay from APEX device pins same both sets pins. same principle applies board delay, because flight times clock data signals equalized.
Table SRAM Interface Signals Signal Name K,K_Bar C,C_Bar RPS_Bar WPS_Bar BWS_Bar A(17.0) Dout(0:17) Din(0:17) State Machine Appendix gives details state machine. SRAM essentialy viewed two-port device, with input port output port data. When using SRAM system, memory controller generates signals needed SRAM serves interface system. memory controller used interface below Altera APEX20KE. APEX family embedded programmable logic device family which used broad range applications. Altera APEX20KE devices, with their speed configurability ideal such interface. Altera APEX architecture features: four programmable phase locked loops device; contains ClockBoost, ClockShift, ClockLock circuitry increased performance, flexible clock frequency multiplication division. APEX family combination three families into architecture, which permits designers integrate complex system into single device, eliminating need multi-device modules, saving board space simplifying complex design implementation. Together, these features provide significant improvements system performance bandwidth. Description Clock Inputs QDRSRAM Output Clocks Read Control Signal Write Control Signal Byte Write Select Signal Address Inputs Read Data output from QDRWrite Data Input QDRQDR
outputs clocked from registers, clkout clkout. these registers placed logic element (LE) registers adjacent logic array block (LAB), their clock-to-output time only slightly greater than clock-to-output time data address signals. Because clocked positve edge clock while data address signals clocked negative edge, there cushion each timing purposes. following calculations apply controller SRAM data transfers. calculation allows difference between clock data /address upto board skew. [tCO(APEX Clock) tCO(APEX Data Address)] Board Skew(Clock Data) tSU(SRAM) [4.5 +1.0 [tCO(APEX Data Address) tCO( APEX Clock)] Board Skew(Clock Data) tH(SRAM) [3.4 -2.2 Read Cycle Timing When read data sent from SRAM controller, setup times APEX device must met. set-up times achieved using programmable delay features available APEX device. Arrival time "dout" signal determined clock-tooutput specification SRAM. CY7C1302V25, maximum value while minimum value (i.e., data output hold time tDOH) Board delay ignored, because flight times signal "dout" roughly equal. Regardless, timing calculation allows some skew between clock data lines. Data sent SRAM rising edge captured controller falling edge clock speed there 5-ns window between rising falling edges. Subtracting clock-to-output delay
Interfacing QDRTMwith Altera APEX20KE
leaves set-up time APEX pins. This timing meets setup requirement with margin signal skew. following calculations apply data transfer from SRAM controller: tCO(SRAM) Board Skew(Clock Data) tSU(APEX) tDOH(SRAM) Board Skew(Data clock) APEX)
Conclusion
SRAM architecture designed greatly increase memory bandwidth communication systems. APEX devices suited interface SRAM because their speed programmability. VHDL implementation shown Appendix2. This implementation available verilog also. These downloaded from following website. models.html
Interfacing QDRTMwith Altera APEX20KE
Appendix
Latch Raddress
Latch Waddress/WData
Decode Raddress(20,19)
Wait
Decode Waddress(20,19)
/RPS(x)
/WPS(x)
Read/Write
A(0:17) Raddress(0:17) A(0:17) Waddress(0:17)
Rdata(0:17) Data(0:17)
Data(0:17) Wdata(0:17)
Rdata(33:18) Data(0:17)
Data(0:17) Wdata(33:18)
Figure State Machine Memory Controller
Read
Write
Interfacing QDRTMwith Altera APEX20KE
Appendix2
Quad Data Rate SRAM Controller Altera Corporation -LIBRARY IEEE; IEEE.STD_LOGIC_1164.ALL; ENTITY qdr_ctrl1 PORT User signals STD_LOGIC_VECTOR(1 DOWNTO 0);- command input: 00=wait, 01=read, 10=write, 11=read/write Raddr STD_LOGIC_VECTOR(17 DOWNTO 0);- read address input Waddr STD_LOGIC_VECTOR(17 DOWNTO 0);- write address input Wdata STD_LOGIC_VECTOR(35 DOWNTO 0);- write data input Rdata STD_LOGIC_VECTOR(35 DOWNTO 0);- read data output inclk: INSTD_LOGIC;- system clock pll_locked:OUT STD_LOGIC;- status output interface (all signals HSTL) OUTSTD_LOGIC; positive SRAM clock K_bar: STD_LOGIC; negative SRAM clock INSTD_LOGIC;- positive feedback clock STD_LOGIC_VECTOR(17 DOWNTO 0);- address STD_LOGIC_VECTOR(17 DOWNTO 0);- data SRAM Dout STD_LOGIC_VECTOR(17 DOWNTO 0);- data from SRAM WPS_bar :OUT STD_LOGIC;- write port select RPS_bar: STD_LOGIC;- read port select BWS_bar: STD_LOGIC_VECTOR(1 DOWNTO byte write select qdr_ctrl1; ARCHITECTURE behavioral qdr_ctrl1 SIGNAL write_address, write_address_reg: STD_LOGIC_VECTOR(17 DOWNTO 0);-write address input register pipeline register SIGNAL write_data_p, write_data_n: STD_LOGIC_VECTOR(17 DOWNTO 0);- positive negative edge write data input registers SIGNAL write_data_p_reg, write_data_n_reg: STD_LOGIC_VECTOR(17 DOWNTO 0);-write data pipeline register SIGNAL temp_write_data, temp_write_data_reg STD_LOGIC_VECTOR(17 DOWNTO write data output register pipleine register SIGNAL read_address, read_address_reg: STD_LOGIC_VECTOR(17 DOWNTO 0);- read address input register pipeline register SIGNAL read_data, read_data_hold STD_LOGIC_VECTOR(35 DOWNTO 0);- read data input register pipeline register SIGNAL read_data_reg, read_data2_reg STD_LOGIC_VECTOR(35 DOWNTO 0);- read data pipeline registers SIGNAL temp_a, temp_a_reg: STD_LOGIC_VECTOR(17 DOWNTO address output register pipeline register SIGNAL cmd1, cmd2: STD_LOGIC_VECTOR(1 DOWNTO 0);- command registers SIGNAL clk2x, clk1x STD_LOGIC;- pipeline clock interface clock from SIGNAL clk_sel_p, clk_sel_n: STD_LOGIC;- clocks used select lines data address muxes SIGNAL clk_sel_p_temp, clk_sel_n_temp: STD_LOGIC;- clocks used select lines data address muxes SIGNAL pll_inclocken STD_LOGIC;- enable signal SIGNAL K_temp, K_bar_temp: STD_LOGIC;- temporary signals output clocks COMPONENT pll1 PORT inclock: STD_LOGIC; clock0: STD_LOGIC; clock1: STD_LOGIC; locked: STD_LOGIC; inclocken: STD_LOGIC COMPONENT; COMPONENT clockgen PORT in1x: STD_LOGIC; in2x: STD_LOGIC; clkout: STD_LOGIC; clkout_bar: STD_LOGIC;
clk_sel_out STD_LOGIC; clk_sel_out_bar STD_LOGIC COMPONENT; COMPONENT controlgen PORT clk2x: STD_LOGIC; STD_LOGIC_VECTOR(1 downto BWS_bar STD_LOGIC_VECTOR(1 downto RPS_bar STD_LOGIC; WPS_bar STD_LOGIC COMPONENT;
BEGIN Clock control generation pll_one: pll1 ClockLock instantiation; generate clocks PORT inclock inclk, clock0 clk1x, clock1 clk2x, locked pll_locked, inclocken pll_inclocken pll_inclocken '1'; always enable K_K_bar_generation: clockgen SRAM clock generation PORT in1x clk1x, in2x clk2x, clkout K_temp, clkout_bar K_bar_temp, clk_sel_out clk_sel_p_temp, clk_sel_out_bar clk_sel_n_temp K_temp; K_bar K_bar_temp; clk_sel_gen: clock select line address data muxes PROCESS(clk2x) BEGIN (clk2x'EVENT clk2x '0') THEN clk_sel_p clk_sel_p_temp; clk_sel_n clk_sel_n_temp; PROCESS clk_sel_gen; BWS_RPS_WPS_generation: controlgen control signal generation PORT clk2x clk2x, cmd2, bws_bar bws_bar, rps_bar rps_bar, wps_bar wps_bar Cmd_pos: save previous command signals PROCESS(clk1x) BEGIN (clk1x'EVENT clk1x '1') THEN cmd1 cmd; cmd2 cmd1; PROCESS Cmd_pos;
Interfacing QDRTMwith Altera APEX20KE
Address path reads writes Addr_inreg: clock addresses from user rising edge feed into address pipeline PROCESS(clk1x) BEGIN (clk1x'EVENT clk1x '1') THEN write_address Waddr; read_address Raddr; write_address_reg write_address; read_address_reg read_address; PROCESS Addr_inreg; A_outreg: transfer address signals domain clock SRAM PROCESS(clk2x) address must valid posedge K_bar writes, posedge reads BEGIN (clk2x'EVENT clk2x '0') THEN (clk_sel_n '0') THEN with inverse clock allow propagation time SRAM temp_A_reg write_address_reg; ELSE temp_A_reg read_address_reg; temp_A temp_A_reg; PROCESS A_outreg; temp_A;
Read_data_pos: register higher data byte rising edge feedback clock PROCESS(C) BEGIN (C'EVENT '1') THEN Read_data_hold(35 DOWNTO Dout; PROCESS Read_data_pos; Read_data_reg_pipeline: transfer read data back system clock domain PROCESS(clk1x) BEGIN (clk1x'EVENT clk1x '1') THEN read_data2_reg read_data_reg; Read_data read_data2_reg; PROCESS Read_data_reg_pipeline; Rdata Read_data
behavioral;
Data path writes Write_data_inreg: clock data from user rising edge feed into data pipeline PROCESS(clk1x) BEGIN (clk1x'EVENT clk1x '1') THEN write_data_p Wdata(17 DOWNTO write_data_n Wdata(35 DOWNTO 18); write_data_p_reg write_data_p; write_data_n_reg write_data_n; PROCESS Write_data_inreg; Din_outreg: transfer write data signals domain clock higher lower bytes alternating clock cycles PROCESS(clk2x) BEGIN (clk2x'EVENT clk2x '0') THEN (clk_sel_p '1') THEN temp_write_data_reg write_data_n_reg; ELSE temp_write_data_reg write_data_p_reg; temp_write_data temp_write_data_reg; PROCESS Din_outreg; temp_write_data;
Data path reads Read_data_neg: register lower data byte falling edge feedback clock PROCESS(C) BEGIN (C'EVENT '0') THEN Read_data_hold(17 DOWNTO Dout; read_data_reg read_data_hold; PROCESS Read_data_neg;
Cypress Semiconductor Corporation, 2001. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

QDRTM: Introduction evolution newer systems increased demands spe

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