HE80000 SERIES Command Mode Flash Preliminary Target Specifi

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HE80000 SERIES Command Mode Flash Preliminary Target Specifi

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HF88F04
HE80000 SERIES
Command Mode Flash
Preliminary Target Specification
Product Name
JESS Doc. HF88F04.doc
Command Mode Flash Memory
JESS Product. HF88F04
Table Contents
7.1. 7.2. 7.3. 7.4. 8.1. 8.2. 8.3. 8.4. 8.5. General Description Features Description Diagram Coordinates Function Block Diagram Parallel Mode Parallel Write Command Mode Parallel Write Data Mode Parallel Read Data Mode Parallel Read Checksum Mode_ Serial Mode Bi-directional Synchronous Serial Data Interface Serial Write Command Mode Serial Write Data Mode_ Serial Read Data Mode Serial Read Checksum Mode Power consideration Absolute Maximum Rating Electrical Characteristics Electrical Characteristics Application Circuit
-102/04/29
HF88F04
HE80000 SERIES
Command Mode Flash
General Description
HF88F04 command mode flash device. features parallel serial bi-directional dual access modes. Multiple device array accessed with only minimal additional device select pin. Simple exclusive checksum provides error detection during data transfer between device. interface logic protocol include setting starting address data transfer, writing data into Flash Memory, well read back verification, error checking Exclusive checksum. used non-volatile memory extension JESS's MCUs. Chip Select pins allows array HF88F04 devices used simultaneously both parallel serial transfer mode. serial mode, HF88F04 connected daisy chain configuration minimize required multi-chip array, while parallel mode, devices share most control pins data except chip select pins.
Features
Dual (parallel serial) command access modes. Address automatically increment with each Read/Write data access. Page erase mode erase verify mode. Exclusive checksum error detection Multiple chip array allowed with easy addressing logic Read access voltage range 2.2V 3.6V Organization Memory Cell Array: 512K Package Dice form
02/04/29
HF88F04
HE80000 SERIES
Command Mode Flash
Description
P_SN CS0N D_CN R_WN BUSY HF88F04
SCLK
Symbol
P_Sn CS0n D_Cn R_Wn Busy SCLK/ Strobe
Description
Input select either parallel (when `1') serial (when `0') interface used transferring data. Negative power supply device CS0n active chip select input pin. device selected when high CS0n simultaneously. Otherwise, deselected. Input select either FLASH memory Registers (TPP, TPH, TPL, Mode Checksum). Input select either Read operation (when `1') write operation (when `0') performed. Busy indicator output. When high, indicates FLASH occupied internal process. Bi-directional data parallel transfer mode. This shared between parallel serial modes. serial mode, this serial clock SCLK transferring data from/to SDI/SDO. parallel mode, strobe signal used write registers FLASH well read checksum contents FLASH memory. This equipped with Schmidt type input structure prevent input from chattering slow rising clock source transition. Serial Data Input writing either Registers Flash Memory. Serial Data Output reading data from either Checksum Register Flash Memory. active high chip select input. device selected when high CS0n simultaneously. Otherwise, deselected. Positive power supply device
02/04/29
HF88F04
HE80000 SERIES
Command Mode Flash
Diagram
Coordinates
Number Name Coordinate Coordinate Number Name P_SN 340.5 1022.7 D[1] 225.5 1022.7 D[2] CS0N 110.5 1022.7 D[3] STROBE[2] -4.5 1022.7 D[4] STROBE[1] -119.5 1022.7 D[5] STROBE[0] -234.5 1022.7 D[6] D_CN -349.5 1022.7 D[7] R_WN -464.5 1022.7 SCLK PMS[0] 2632.97 332.41 PMS[1] 2632.61 448.7 PMS[2] 2525.51 1022.7 PMS[3] 2410.51 1022.7 PPWD PMS[4] 2295.51 1022.7 BUSY 2180.51 1022.7 D[0] 2065.51 1022.7 Coordinate Coordinate 1950.51 1022.7 1835.51 1022.7 1720.51 1022.7 1605.51 1022.7 1490.51 1022.7 1375.51 1022.7 1260.51 1022.7 1145.51 1022.7 1030.51 1022.7 915.51 1022.7 800.5 1022.7 685.5 1022.7 570.5 1022.7 455.5 1022.7
02/04/29
HF88F04
HE80000 SERIES
Command Mode Flash
Function Block Diagram
Several registers used interface logic. functions registers described below their initial values indicated following table.
FDIN[7.0] TP[21.0]
FLASH Memory
FDOUT[7.0] MODE
CHKSUM
SCLK/Strobe
Busy
R_Wn
CS0n
D_Cn
Register Type Description Initial Value Address register Address register Address register Mode Mode Control Register "-000" Checksum checksum data Table Pointer register keeps address FLASH memory being written read from. will automatically increment completion each read/write access.
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P_Sn
D[7.0]
HF88F04
HE80000 SERIES
Command Mode Flash
Checksum Register keeps Exclusive checksum data bytes they written to/read from FLASH memory. Checksum register cannot written cleared access TPP, TPH, Mode Register. Mode register 3-bit register, which used control operation modes FLASH memory. There five modes FLASH module: Power down, Read, Byte program, Page Erase Erase verify operations. Read Erase Verify modes need read data operation execute. Byte program Page Erase modes performed through Write Data operation. enter Power down mode, just fill "000" mode register sufficient, extra data read write operation required. Mode2 Mode1 Mode0 Operation None Read Write Write Read Description Power down mode Read mode Byte program mode Page erase mode Erase verify mode
After Page erase operation, user perform blank checking executing Erase verify mode. erasure incomplete, then user page erase again. page still totally blank after erasures, then device already worn out.
Parallel Mode
When parallel mode, 8-bit data D[7.0] used transfer information between Flash memory. advantage parallel transfer mode that higher speed achieved. operate parallel mode, drive P_Sn with high level.
7.1. Parallel Write Command Mode
Loading addresses Mode register parallel mode asserting Strobe (going then high) write command mode (both R_Wn D_Cn low), which will also clear CHKSUM register same time. After previous data transfer when device just selected (CS1 high CS0n low), command data will written registers order TPL, TPH, TPP, then Mode, TPL. when unsure, dummy data read deselect select device again will reset register select.
-602/04/29
HF88F04
HE80000 SERIES
Command Mode Flash
7.2. Parallel Write Data Mode
write Flash memory, assert Strobe Data Write Mode (D_Cn R_Wn Vil) with proper mode code Mode register. There Flash Write modes Byte Program Page Erase mode. control timing similar, only mode codes different. When writing data Flash memory modes, Busy signal will high after assertion (turning low) Strobe signal. mode select pins (D_Cn, P_Sn, R_Wn) should held steady Strobe must remain asserted (held level) until Busy signal falls. Additionally, Byte Programming mode, Data D[7.0] should held stable before Busy signal goes low. checksum register will updated, register will incremented with rising edge Strobe signal.
7.3. Parallel Read Data Mode
Flash Mode (Read Flash mode) Mode (Erase verify mode), contents Flash memory read asserting Strobe Read Data mode (R_Wn high D_Cn low). data will appear Data after proper access time. will increment Checksum will
-702/04/29
HF88F04
HE80000 SERIES
Command Mode Flash
update rising edge Strobe. Register select will reset read data operation.
7.4. Parallel Read Checksum Mode
read checksum result from previous data transfer (either from Flash Flash), assert Strobe signal Read Command mode (R_Wn high D_Cn low).
Serial Mode
serial interface preferable parallel interface applications where pins limited. interface logic circuit basically same parallel mode except that internal shift register counter used facilitate transferring serial data from/to external MCU. Multiple devices array also used serial mode. chip array connected daisy chain manner. MCU's serial data output drives first device. device then, turn, drives next device chain. last device then connects back MCU's complete loop. There could only active device array time, while other device must deselected.
02/04/29
HF88F04
HE80000 SERIES
Command Mode Flash
8.1. Bi-directional Synchronous Serial Data Interface
Serial interface Bi-directional Synchronous Serial Interface. Data written Registers (such TPL, TPH, TPP, Mode registers) well Flash memory through serial interface. Checksum Flash memory contents also read through Serial Interface, too. Serial Data Input connected internal shift register. With each rising edge SCLK pin, input shifted into shift register. eighth rising edge SCLK, content shift register transferred from/to registers Flash memory depending status D_Cn R_Wn. R_Wn "high" state eighth rising edge SCLK then either contents Checksum Register D_Cn "low") Flash memory been addressed D_Cn "high") will latched into internal shift register. Then contents shift register shifted with next eight rising edges SCLK. thing important should noted here when using Serial Data Interface read checksum register FLASH data that dummy read should performed before real data shifted from pin.
8.2. Serial Write Command Mode
sequence setting addresses data transfer mode similar parallel mode. register pointer will reset accesses FLASH data same parallel mode does. immediately after completion previous data transfers when device just selected, command writes will made TPL, TPH, then Mode registers then wrap around. unsure time during transfer, dummy data read made reset register select.
02/04/29
HF88F04
HE80000 SERIES
Command Mode Flash
8.3. Serial Write Data Mode
With each rising edge SCLK signal serial data write mode, Data will shifted into internal shift register. Busy signal will high after assertion (falling edge) eighth SCLK. After Busy signal falls, content less significant Bits internal shift register along with will transfer Flash memory eighth rising edge SCLK. this rising edge, checksum register will updated, register will incremented. status R_Wn, D_Cn must held steady mean time.
8.4. Serial Read Data Mode
Flash mode both R_Wn, D_Cn high level eighth rising edge SCLK then contents Flash memory been addressed will latched into internal shift register. Then contents shift register shifted with next eight rising edges SCLK. thing important should noted here when using Serial Data Interface read FLASH data that dummy read should performed before real data shifted from
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HF88F04
HE80000 SERIES
Command Mode Flash
pin.
8.5. Serial Read Checksum Mode
Reading checksum serial mode similar Read data mode except that D_Cn level instead high.
Power consideration
order conserve power consumed device, static power consumption Flash memory Sense Amplifier need minimized. Since Sense Amplifier whenever device selected Strobe/SCLK asserted Data Read Mode. Therefore save power minimize duty overall Strobe/SCLK signal extent that just long enough satisfy access time that static power consumption lowered.
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HF88F04
HE80000 SERIES
Command Mode Flash
Absolute Maximum Rating
Items Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol TOPR TSTR Rating -0.3 -0.3 Vdd+0.3 Condition
Electrical Characteristics
READ CYCLE
Item Symbol VCC=3.3V 0.3V Unit
Access Time
tacc
Electrical Characteristics
(VSS TOPR 25°C unless otherwise noted) Parameter Supply Voltage Operating Current Standby Current Input voltage Input current leakage Sym. Min. Typ. Unit load load 2.7V 3.6V Condition
Application Circuit
application circuit diagram shows JESS's uses HF88F04 non-volatile Read/Write memory extension. Please note that first device drive second device only device select DEV1 used select between device. P_Sn pins tied ground operate serial mode.
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02/04/29
HF88F04
HE80000 SERIES
Command Mode Flash
P_SN CS0N D_CN R_WN HF88S04 SCLK DEV1 SCLK P_SN CS0N D_CN R_WN HF88S04 SCLK D_Cn R_Wn DEV1 D_Cn R_Wn SCLK
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02/04/29

HE80000 SERIES Command Mode Flash Preliminary Target Specifi

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