November 1997 Revised 2003 High-Speed CMOS Logic 8-Bit Addressabl

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November 1997 Revised 2003 High-Speed CMOS Logic 8-Bit Addressabl

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CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
November 1997 Revised 2003
High-Speed CMOS Logic 8-Bit Addressable Latch
Description
'HC259 'HCT259 Addressable Latch features low-power consumption associated with CMOS circuitry speeds comparable low-power Schottky. This latches three active modes reset mode. When both Latch Enable (LE) Master Reset (MR) inputs (8-line Demultiplexer mode) output addressed latch follows Data input other outputs forced low. When both high (Memory Mode), outputs isolated from Data input, i.e., latches hold last data presented before transition from high. condition high (Addressable Latch mode) allows addressed latch's output follow data input; other latches unaffected. Reset mode (all outputs low) results when high low.
Features
Buffered Inputs Outputs
/Title (CD74 HC259 CD74 HCT25 /Subject (High Speed CMOS Logic 8-Bit Addres sable Latch)
Four Operating Modes Typical Propagation Delay 15ns 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Ordering Information
PART NUMBER CD54HC259F3A CD54HCT259F3A CD74HC259E CD74HC259M CD74HC259M96 CD74HCT259E CD74HCT259M CD74HCT259M96 TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC SOIC PDIP SOIC SOIC
NOTE: When ordering, entire part number. suffix denotes tape reel.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Pinout
CD54HC259, CD54HCT259 (CERDIP) CD74HC259, CD74HCT259 (PDIP, SOIC) VIEW
Functional Diagram
1-OF-8 DECODER LATCHES
TRUTH TABLE INPUTS OUTPUT ADDRESS LATCH
LATCH SELECTION TABLE SELECT INPUTS LATCH ADDRESSED
EACH OTHER OUTPUT
FUNCTION Addressable Latch Memory 8-Line Demultiplexer Reset
High Voltage Level Voltage Level level data input level 1.7, appropriate) before indicated steady-state input conditions were established.
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. .±25mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, IGND .±50mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (PDIP) Package (SOIC) Package. Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. (Note -2.1 -0.02 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1
Input Loading Table
INPUT UNIT LOADS 0.75
NOTE: Unit Load limit specified Electrical Table, e.g., 360µA 25oC.
Prerequisite Switching Specifications
25oC PARAMETER TYPES Pulse Width SYMBOL -40oC 85oC -55oC 125oC UNITS
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Prerequisite Switching Specifications
(Continued) 25oC PARAMETER SYMBOL Setup Time Hold Time TYPES Pulse Width Setup Time Hold Time -40oC 85oC -55oC 125oC UNITS
Switching Specifications
50pF, Input 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay
SYMBOL
TEST CONDITIONS
tPHL
50pF 15pF 50pF 15pF 50pF
tPHL
50pF
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Switching Specifications
50pF, Input (Continued) 25oC PARAMETER SYMBOL tPHL TEST CONDITIONS 50pF 15pF 50pF tPHL, tPLH 50pF 15pF 50pF Output Transition Time tTHL, tTLH 50pF Power Dissipation Capacitance (Notes Input Capacitance TYPES Propagation Delay tPHL, tPLH 50pF 15pF 50pF 15pF 50pF 15pF 50pF 15pF Power Dissipation Capacitance (Notes Input Capacitance Output Transition Time NOTES: used determine dynamic power consumption, package. VCC2 VCC2 where Input Frequency, Output Frequency, Output Load Capacitance, Supply Voltage. tTHL, tTLH 15pF 50pF 50pF 15pF 50pF -40oC 85oC -55oC 125oC UNITS
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Test Circuits Waveforms
trCL CLOCK tfCL CLOCK trCL tfCL 2.7V 0.3V 1.3V 0.3V 1.3V 1.3V
NOTE: Outputs should switching from accordance with device truth table. fMAX, input duty cycle 50%. FIGURE CLOCK PULSE RISE FALL TIMES PULSE WIDTH
NOTE: Outputs should switching from accordance with device truth table. fMAX, input duty cycle 50%. FIGURE CLOCK PULSE RISE FALL TIMES PULSE WIDTH
INPUT
INPUT 2.7V 1.3V 0.3V
tTLH
tTHL
tTLH tPHL tPLH
tTHL
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
1.3V
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
trCL CLOCK INPUT tH(H)
tfCL tH(L) DATA INPUT tSU(H) CLOCK INPUT
trCL 2.7V 0.3V tH(H)
tfCL 1.3V tH(L) 1.3V 1.3V 1.3V tSU(L) tTLH tTHL 1.3V tPHL
DATA INPUT tSU(H) tTLH OUTPUT tPLH tREM SET, RESET PRESET tSU(L) tTHL tPHL
OUTPUT
1.3V tPLH
tREM SET, RESET PRESET
1.3V
50pF
50pF
FIGURE SETUP TIMES, HOLD TIMES, REMOVAL TIME, PROPAGATION DELAY TIMES EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE SETUP TIMES, HOLD TIMES, REMOVAL TIME, PROPAGATION DELAY TIMES EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Test Circuits Waveforms
OUTPUT DISABLE tPZL tPHZ OUTPUT HIGH OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED tPZH OUTPUT HIGH OUTPUTS ENABLED OUTPUT tPHZ
(Continued)
tPLZ OUTPUT DISABLE tPZL
tPLZ OUTPUT
tPZH
1.3V
1.3V OUTPUTS DISABLED OUTPUTS ENABLED
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM
OTHER INPUTS TIED HIGH OUTPUT DISABLE
WITH THREESTATE OUTPUT
OUTPUT 50pF
tPLZ tPZL tPHZ tPZH
NOTE: Open drain waveforms tPLZ tPZL same those three-state shown left. test circuit Output VCC, 50pF. FIGURE THREE-STATE PROPAGATION DELAY TEST CIRCUIT
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
0.775 (19,69) 0.745 (18,92)
0.775 (19,69) 0.745 (18,92)
0.920 (23,37) 0.850 (21,59)
1.060 (26,92) 0.940 (23,88)
0.260 (6,60) 0.240 (6,10)
MS-100 VARIATION
0.070 (1,78) 0.045 (1,14)
0.045 (1,14) 0.030 (0,76)
0.020 (0,51)
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
0.430 (10,92)
14/18 ONLY vendor option
4040049/E 12/2002
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width.
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20)
Gage Plane 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,75) 0.337 (8,55)
0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE 655303
DALLAS, TEXAS 75265
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Copyright 2003, Texas Instruments Incorporated

November 1997 Revised 2003 High-Speed CMOS Logic 8-Bit Addressabl

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