November 1997 Revised 2003 High-Speed CMOS Logic Quad 2-Input Mul

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November 1997 Revised 2003 High-Speed CMOS Logic Quad 2-Input Mul

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CD54HC257, CD74HC257, CD54HCT257, CD74HCT257
November 1997 Revised 2003
High-Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs
control common Select Input (S). Output Enable input (OE) active LOW. When HIGH, outputs (1Y-4Y) high impedance state regardless other input conditions. Moving data from groups registers four common output buses common 257. state Select input determines particular register from which data comes. also used function generator.
Features
Buffered Inputs
/Title (CD74 HC257 CD74 HCT25 /Subject (High Speed CMOS Logic Quad 2-Input Multiplexer
Typical Propagation Delay Output 12ns 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Ordering Information
PART NUMBER CD54HC257F3A CD54HCT257F3A CD74HC257E CD74HC257M CD74HC257M96 CD74HCT257E CD74HCT257M CD74HCT257M96 TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC SOIC PDIP SOIC SOIC
Description
'HC257 'HCT257 quad 2-input multiplexers which select four bits data from sources under
NOTE: When ordering, entire part number. suffix denotes tape reel.
Pinout
CD54HC257, CD54HC257 (CERDIP) CD74HC257, CD74HC257 (PDIP, SOIC) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Functional Diagram
CIRCUITS IDENTICAL CIRCUIT ABOVE DASHED ENCLOSURE
TRUTH TABLE OUTPUT ENABLE SELECT INPUT
DATA INPUTS
OUTPUT
High Voltage Level Voltage Level Don't Care High Impedance, State
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. .±35mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, .±70mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (PDIP) Package (SOIC) Package. Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads -0.02 -0.02 -0.02 High Level Output Voltage Loads Level Output Voltage CMOS Loads -7.8 0.02 0.02 0.02 Level Output Voltage Loads Input Leakage Current 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current Three-State Leakage Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load Three-State Leakage Current NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. (Note -2.1 -0.02 SYMBOL (mA) 25oC ±0.5 -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1
±0.5
Input Loading Table
INPUT Data UNIT LOADS 0.95
NOTE: Unit Load limit specified Electrical Specifications table, e.g., 360µA 25oC.
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257
Switching Specifications
Input TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay
SYMBOL
tPLH, tPHL
50pF
15pF 50pF Propagation Delay tPLH, tPHL 50pF
15pF 50pF Propagation Delay tPLZ, tPHZ, tPZL, tPZH 50pF 50pF 15pF 50pF Output Transition Times tTLH, tTHL 50pF
Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes TYPES Propagation Delay Propagation Delay Propagation Delay Output Transition Times Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes NOTES:
tPLH, tPHL
50pF 15pF
tPZL, tPZH
50pF 15pF
tPLZ, tPHZ
50pF 15pF
tTLH, tTHL
50pF
used determine dynamic power consumption, multiplexer. VCC2 (CPD where Input Frequency, Output Load Capacitance, Supply Voltage.
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Test Circuits Waveforms
INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V
tTHL
INVERTING OUTPUT
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
OUTPUT DISABLE tPZL tPHZ OUTPUT HIGH OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED tPZH
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
OUTPUT DISABLE tPLZ OUTPUT tPHZ OUTPUT HIGH OUTPUTS ENABLED tPZL
tPLZ OUTPUT
tPZH
1.3V
1.3V OUTPUTS DISABLED OUTPUTS ENABLED
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM
OTHER INPUTS TIED HIGH OUTPUT DISABLE
WITH THREESTATE OUTPUT
OUTPUT 50pF
tPLZ tPZL tPHZ tPZH
NOTE: Open drain waveforms tPLZ tPZL same those three-state shown left. test circuit Output VCC, 50pF. FIGURE THREE-STATE PROPAGATION DELAY TEST CIRCUIT
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
0.775 (19,69) 0.745 (18,92)
0.775 (19,69) 0.745 (18,92)
0.920 (23,37) 0.850 (21,59)
1.060 (26,92) 0.940 (23,88)
0.260 (6,60) 0.240 (6,10)
MS-100 VARIATION
0.070 (1,78) 0.045 (1,14)
0.045 (1,14) 0.030 (0,76)
0.020 (0,51)
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
0.430 (10,92)
14/18 ONLY vendor option
4040049/E 12/2002
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width.
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20)
Gage Plane 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,75) 0.337 (8,55)
0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements.
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Copyright 2003, Texas Instruments Incorporated

November 1997 Revised 2003 High-Speed CMOS Logic Quad 2-Input Mul

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