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HE80000 SERIES A.HE83760S Introduction HE83760S member Jess


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HE83760S
HE80000 SERIES
A.HE83760S Introduction
HE83760S member Jess Tech HE80000 series 8-bit CMOS micro-controller. This 3072-dot driver Port. built-in internal Op-Amp, 7-bit converter, DTMF generator output module provide speech output interface. built-in 2MByte 16Kbyte store around large volume data including voice, graphics data. HE83760S provides very simple effective instruction set, each instruction byte occupies only clock cycle time, therefore, suitable apply high performance systems.
B.HE83760S Features
2.4V 3.6V 8MHz 3.6V 4MHz 2.4V size: Bytes Program ROM+1984K Data ROM) size: Bytes Dual Clock: Normal(Fast) clock: 32.768K 8MHz Slow clock: 32.768KHz Operating Mode: DUAL FASTSLOWIDLESLEEP Built-in WATCH TIMER bi-directional pins, PUSH-PULL OPEN DRAIN output selected mask option Built-in internal Op-Amp 3072 driver Built-in DTMF generator Built-in 7-bit Converter Built-in output circuit Provides three internal external interrupt Provides 16-bit timer, time base timer Instruction Instructions, types Addressing Mode, individual Pointer (21-bit) (14-bit) table access. Operating Voltage: Operation frequency Range:
C.HE83760S Application
Interface Light, Sound, Temperature Humidity sensor controlling application. Suitable games, education toys, data-bank, translator some mid-to-high electronic products.
2002
Preliminary V1.3
HE83760S
HE80000 SERIES
Assignment
Name Function Description External Fast Clock pin. Mask Option settings connect Crystal MO_FCK/SCKN=00Slow Clock only oscillation generate 01Illegal 32.768KHz 8MHz 10Dual Clock system clock. 11Fast Clock only External Slow Clock MO_FOSCE=0Internal fast oscillation connect 32.768KHz 1External fast oscillation oscillator generate MO_FXTAL=0R,C oscillation Fast Clock stable frequency Slow 1Crystal oscillation Fast Clock Mode Timer clock source. MO_SXTAL=0R,C oscillation 32.768K Clock 1X'tal oscillation 32.768K Clock Program value OP1and change operating modes (Normal, Slow, Idle Sleep). Dual Clock modethe system runs Fast Clock, only Timer 32.768K clock source. Pull this level reset system. Besides, Select Mask Option (MO_PORE=1) enable HE83760S internal Power-on Reset function. System reset signal addition, MO_WDTE used Watch Timer setting MO_WDTE =0Disable Watch Timer =1Enable Watch Timer Test Pin. Please bond this test point debugging. Leave this floating Mask Option MO_CPP[7:0] preset output type: Port bi-directional MO_CPP=1 Push-pull output pins) Open-drain output. When assigned port input pin, send read result input value. Port bi-directional Mask Option MO_DPP[7:0] preset output type: pin, pins). PRTD[7:2] MO_DPP=1 Push-pull output also Wake-up Open-drain output. PRTD[7:6] used When assigned port input pin, send read interrupt input pin. result input value. Mask Option MO_10PP[7:0] output type Port bi-directional MO_10PP ='1'then Push-pull output pin, pins). ='0'then Open-drain output When assigned port input pin, send read result input value. Mask Option MO_11PP[7:0] output type Port bi-directional MO_11PP ='1'then Push-pull output pin, pin). ='0'then Open-drain output When assigned port input pin, send read result input value.
FXI,
SXI,
RSTP_N
TSTP_P
PRTC[7:0]
PRTD[7:0]
109. PRT10[7:0]
117. PRT11[7:0]
2002
Preliminary V1.3
HE83760S
HE80000 SERIES
143.128 44.59 144.196 1.43
COM[31:0] SEG[95:0]
COMmon Output SEGment Output Bias Voltage Bias Voltage Bias Voltage Bias Voltage Bias Voltage Fill data from Page refer map. LVP>LV5>LV4>LV3>LV2>LV1. LVP-0.5>LV5 sure keep volt between lease.)
LGS1 LGS2 LCAP4A LCAP2B LCAP2A LCAP1A LCAP1B LCAP3A VREG PWMP
Adjust Resistor (R2) between LGS2 glass. formula (1+R2/80K)*0.9V Regulator Voltage Setting Could adjust LVREG voltage Drive Voltage Setting voltage setting
PWMN OPIN OPIP DTMFO
MUTE KEYTON
LVP=(3,4,5)*LVREG which setting external Capacitor Charge Pump Capacitor Different Capacitor Configuration make Charge Pump Capacitor LVP=(3,4,5)* LVREG Charge Pump Capacitor Charge Pump Capacitor driving circuit here makes regulation first, then Charge Pump Capacitor charge pump LVP. generates bias voltage based Charge Pump Capacitor LVP. Voltage Regulator Output Adjust about Volt Resistor between LGS1 Charge Pump Input) LVREG Reference Voltage Output Fixed Volt pin, directly drive Speaker Preset Bit2 register: =1turn PWM. Buzzer voice output. pin, directly drive Speaker Preset Bit2 register: =1turn PWM. Buzzer voice output. voice output Preset Bit-1 register: DA=1turn Output, OP-Amp Preset Bit-0 register: OP=1; turn DAO. OPAMP Inverting Preset Bit-0 register: OP=1turn OPAMP Non-inverting Individual built-in OP-Amp pin. OPAMP Turn on/off DTMF write data port12 Mask Option MO_DTMFSCK preset clock DTMF Output source: MO_DTMFSCK=0Clock Source=3.579545 =1Clock Source=32768 MUTE Output Dialer Turn on/off MUTE port12. Dialer Application Turn on/off write data port12. 1024 Duty Square Turn on/off KEYTONE port12. wave Positive Power Input Adding 0.1µF capacitor by-pass capacitor between Power Ground Input necessary
Charge Pump Output
2002
Preliminary V1.3
HE83760S
HE80000 SERIES
E.LCD
Page COM0 COM1 COM2 COM29 COM32 COM31 [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [55:48] [63:56]
Page COM0 COM1 COM2 COM29 COM32 COM31
[71:64]
[79:72]
[87:80]
[95:88]
2002
Preliminary V1.3
HE83760S
HE80000 SERIES
Diagram
HE83760S
2002
Preliminary V1.3
HE83760S
HE80000 SERIES
Bonding Location
HE83760S PADLIST
Number Name Coordinate Coordinate 2002 SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 -4077.20 1523.75 1408.75 1293.75 1178.75 1063.75 948.75 833.75 718.75 603.75 488.75 373.75 258.75 143.75 28.75 -86.25 -201.25 -316.25 -431.25 -546.25 -661.25 -776.25 -891.25 -1006.25 -1121.25 -1236.25 -1351.25 -1466.25 -1581.25 Preliminary V1.3
HE83760S
HE80000 SERIES
2002
SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] SEG[0] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] LVL1 LVL2 LVL3 LVL4 LVL5 LGS2 LCAP4A
-4077.20 -4077.20 -3670.75 -3548.80 -3424.10 -3309.10 -3194.10 -3079.10 -2964.10 -2849.10 -2734.10 -2619.10 -2504.10 -2389.10 -2274.10 -2159.10 -2044.10 -1929.10 -1814.10 -1699.10 -1584.10 -1469.10 -1354.10 -1239.10 -1124.10 -1009.10 -894.10 -779.10 -664.10 -549.10 -434.10 -319.10 -204.10 -89.10 25.90 140.90 255.90 370.90 485.90
-1705.95 -1827.90 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 Preliminary V1.3
HE83760S
HE80000 SERIES
2002
LCAP2B LCAP2A LCAP1A LCAP1B LCAP3A LVREG LGS1 LVAG OPIN OPIP RSTP_N TSTP_P MUTE DTMFO KEYTONE PRTD[7] PRTD[6] PRTD[5] PRTD[4] PRTD[3] PRTD[2] PRTD[1] PRTD[0] PRTC[7] PRTC[6] PRTC[5] PRTC[4] PRTC[3] PRTC[2]
600.90 715.90 830.90 945.90 1060.90 1175.90 1290.90 1405.90 1520.90 1635.90 1750.90 1865.90 1980.90 2095.90 2210.90 2325.90 2440.90 2555.90 2711.45 2826.90 2941.90 3056.90 3171.90 3286.90 3401.90 3516.90 3641.60 3787.62 3926.09 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34
-1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1933.95 -1770.65 -1649.60 -1524.90 -1409.90 -1294.90 -1179.90 -1064.90 -949.90 -834.90 -719.90 Preliminary V1.3
HE83760S
HE80000 SERIES
2002
PRTC[1] PRTC[0] PRT10[7] PRT10[6] PRT10[5] PRT10[4] PRT10[3] PRT10[2] PRT10[1] PRT10[0] PRT11[7] PRT11[6] PRT11[5] PRT11[4] PRT11[3] PRT11[2] PRT11[1] PRT11[0] PWMP PWMN VDD_RAM COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] SEG[95] SEG[94]
4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 4048.34 3971.56 3854.13 3738.64 3623.10 3508.10 3393.10 3278.10 3163.10 3048.10 2933.10 2818.10 2703.10 2588.10 2473.10 2358.10 2243.10 2128.10 2013.10
-604.90 -489.90 -374.90 -259.90 -144.90 -29.90 85.10 200.10 315.10 430.10 545.10 660.10 775.10 890.10 1005.10 1120.10 1235.10 1350.10 1465.10 1586.80 1711.74 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 Preliminary V1.3
HE83760S
HE80000 SERIES
2002
SEG[93] SEG[92] SEG[91] SEG[90] SEG[89] SEG[88] SEG[87] SEG[86] SEG[85] SEG[84] SEG[83] SEG[82] SEG[81] SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55]
1898.10 1783.10 1668.10 1553.10 1438.10 1323.10 1208.10 1093.10 978.10 863.10 748.10 633.10 518.10 403.10 288.10 173.10 58.10 -56.90 -214.90 -329.90 -444.90 -559.90 -674.90 -789.90 -904.90 -1019.90 -1134.90 -1249.90 -1364.90 -1479.90 -1594.90 -1709.90 -1824.90 -1939.90 -2054.90 -2169.90 -2284.90 -2399.90 -2514.90
1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45
Preliminary V1.3
HE83760S
HE80000 SERIES
SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43]
-2629.90 -2744.90 -2859.90 -2974.90 -3089.90 -3204.90 -3319.90 -3434.90 -3549.90 -3674.60 -3789.60 -3911.55
1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45 1902.45
2002
Preliminary V1.3
HE83760S
HE80000 SERIES
Electrical Characteristics
Absolute Maximum Rating
Item Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature
Sym. Rating -0.5V -0.5V Vdd+0.5V -0.5V Vdd+0.5V 700C -500C 1000C
Condition
Recommended Operating Conditions
Item Supply Voltage Input Voltage Operating Frequency Operating Temperature Storage Temperature
Sym. Fmax
Rating 2.4V 3.6V 0.0V 0.1Vdd 8MHz 4MHz 700C -500C 1000C
Condition
=5.0V =2.4V
2002
Preliminary V1.3
HE83760S
HE80000 SERIES
Test condition:TEMP=25, VDD=3V+/-10%, GND=0V
PARAMETER CONDITION UNIT
IFast
NORMAL Mode Current System System System
ISlow SLOW Mode Current IIdle IDLE Mode Current
ILCD Extra Current System
ext. 32.768K X'tal Disable 32.769K X'tal Disable Enable, option=300Kohm Voltage-doubler Enable, option=30Kohm, Voltage-doubler
ISleep Sleep Mode Current IPWM Output Drive Current
IoVO Output Current Input High Voltage Input Voltage
System PWMP, PWMN*2 With Loading With Loading With Loading VDD=3V;VO=0~2V, Data=7F pins pins
Vhys Input Hysteresis Width Output Drive Current Output Sink Current IiL_1 Input Current IiL_2 Input Current PARAMETER IFast
I/O, RSTP_N pull-high*1 pull-low*1 RSTP_N
NORMAL Mode Current System Note:
Threshold=2/3VDD(input from high) Threshold=1/3VDD(input from high low) VoL=2.0V VoL=0.4V ViL=GND, pull high Internally ViL=GND, pull high Internally user CONDITION UNIT ext.
Drive Current Spec. Push-Pull port only Sink Current Spec. both Push-Pull Open-Drain port. This Spec. base driver only. There five build-in driver, multiply number driver used driver current total amount current.( IPWM N=0,1,2,3,4,5)
user
just
2002
Preliminary V1.3
HE83760S
HE80000 SERIES
Application Circuit
2002
Preliminary V1.3
HE83760S
HE80000 SERIES
Important Note
accessing address large than 64KB, users must update first, then TPL. Only this order, pre-charge circuit will work correctly. waiting necessary before instruction executed since Data speed ROM. Users emulate this accessing process ICE. delay should added firmware. driving circuit must turn before goes into sleep mode Please bonds TSTP_P, RSTP_N PRTD[7:0] with test point (can soldered probed) can, then JESS some testing PCB. Neither connection necessary TSTP_P. following figure example (Testing point with through hole.)
must small than Volt. Otherwise breakdown.
2002
Preliminary V1.3
HE83760S
HE80000 SERIES
SUPPLEMENTARY SPECIFICATION
HE82/83/89 application
Description: HE83/89 application, following points must bare mind. output direct drive buzzer. direct drive speaker, must above speaker. speaker application, must capacitors between IC's ground output, below figure. Note: capacitor must connected near IC's
2002
Preliminary V1.3

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