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M65827FP
10-TIMES SPEED CD-DSP
PACKAGE
FEATURES
speed times speed playback speed selector doubler correction(C1:2 error correction,C2:4 error correction) control circuit Bilingual swap (L+R)/2) adjustment-free EFM-PLL gain control power consumption radiation 3.3V function internal circuit
Outline 42P2R
APPLICATION
CD-ROM, CD-I, VIDEO-CD, etc.
0.8mm Pitch 450mil SSOP (8.4mm 17.5mm 2.0mm)
RECOMMENDED OPERATING CONDITIONS
Supply voltage range Rated voltage range 3.3V±10% (internal logic,analog circuits,oscillation circuit) 5.0V±10% (I/O buffer) 3.3V (internal logic,analog circuit) 5.0V (I/O buffer
SYSTEM BLOCK DIAGRAM
Subcode Control Digital Channel control DeEMP Subcode Digital
Motor Driver
Optical Pick-up
RF-AMP Pick-up Servo Auto Adjustment
Slicer
De-MOD
Interpolation
DATAOUT
18kSRAM Digital Servo Timing Generator (Speed Control) M65827FP
C1:2errors C2:4errors
System Control Microprocessor
MITSUBISHI ELECTRIC
BUILT FUNCTIONS Block name
Memory
Description
Kbit SRAM frames jitter margin EFM-PLL lock times) data slicer demodulator synchronization detection protection interpolation synchronization monitor register checker synchronous pattern detector flag detector digital de-emphasis filter interface subcode (EIAJ CP-2401) error correction, error correction (C1: error correction, error correction selectable) De-interleave monitor pre-hold interpolation (for CD-DA mode prohibition (for CD-ROM mode control swap (L+R)/2 output independent attenuation control (256 steps) data output CD-DA (DADT) CD-ROM(ROMDT) EIAJ-1201 oscillation accuracy control source number control output disc rotation detector pulse control (256 steps) brake control gain control clock selector (Playback speed control) doubler clock selector servo control mute control attenuating level control control control control back speed control switch control monitor control counter control mask timer control audio interface control sleep clock disable control interface
demodulation
Subcode control
Error correction
Interpolation interface
Digital output
Digital servo
Oscillation circuit
interface
MITSUBISHI ELECTRIC
DESCRIPTION TABLE
Name DVDD5 DVDD3 DVSS AVDD AVSS Clock C423 S846 S423 DXLPF DXRC IREF HPF1 HPF2 defect signal input Current reference EFM-PLL loop filter connect EFM-PLL frequency gain control input High Pass Filter High Pass Filter Data slicer charge pump output DVDD5 AVDD AVDD AVDD AVDD AVDD AVDD AVDD Oscillator input Oscillator output Crystal half clock Crystal system clock Crystal half clock Clock doubler loop filter connect Clock doubler frequency gain control DVDD3 DVDD3 DVDD5 DVDD5 DVDD5 DVDD3 DVDD3 Digital power supply power supply buffer) Digital power supply (3.3V power supply internal circuit) Digital ground Analog power supply (3.3V power supply analog circuit) Analog ground AVDD DVDD5 DVDD3 Description Supply Schmitt Pull-Up
Data output Digital Audio Interface DADT ROMDT LRCK DSCK DOTX Audio data output CD-ROM data output clock Data shift clock Digital audio interface output DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
MITSUBISHI ELECTRIC
DESCRIPTION TABLE (CONTINUED)
Name Subcode SBQS SCAND SBCO EFFK SCCK CRCF PWM1 PWM2 Spindle motor output Spindle motor output DVDD5 DVDD5 Subcode interrupt signal Subcode sync. signal output Subcode data serial output frame clock output Subcode data shift clock flag output DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 Description Supply Schmitt Pull-Up
Track counter TRIN Track cross signal input Interrupting signal output DVDD5 DVDD5
interface ALCR shift clock input data read write control data input ouput latch clock input Reset input DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
Monitor output LOCK/DRD C1/C2 error flag output Lock monitor output disc rotation detect signal output Frame synchronization status (SYCLK) DVDD5 DVDD5
MITSUBISHI ELECTRIC
NUMERICAL LIST
Name DVDD5 DVDD3 DXLPF LOCK/DRD Description Digital power supply power supply buffer) Digital power supply (3.3V power supply internal circuits) Clock doubler loop filter connect Lock monitor output disc rotation detect signal output Frame synchronization status(SYCLK) Subcode interrupt signal output shift clock input data read write control data input output latch clock input Reset input defect signal input Clock doubler frequency gain control Current reference Analog power supply (3.3V power supply analog circuits) EFM-PLL loop filter connect EFM-PLL frequency gain control input High Pass Filter High Pass Filter Data slice charge pump output Analog ground Subcode syncronization status Subcode data serial output frame clock output Subcode readout clock Digital output flag output DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 Supply Schmitt Pull-Up DVDD5 DVDD3 DVDD3 DVDD5
SBQS ALCR DXRC IREF AVDD HPF1 HPF2 AVSS SCAND SBCO EFFK SCCK DOTX CRCF
DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD3 AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD
MITSUBISHI ELECTRIC
NUMERICAL LIST (CONTINUED)
Name DADT LRCK DSCK ROMDT PWM2 PWM1 S846 S423 TRIN C423 DVSS Description Audio data output clock Data shift clock CD-ROM data output Spindle motor output (+signal) Spindle motor output (-signal) Crystal system clock Crystal half clock Track cross signal input Interrupt signal output Crystal half clock C2/C1 error output Oscillator output Oscillator input Digital ground Supply Schmitt Pull-Up DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD3 DVDD3
MITSUBISHI ELECTRIC
CONFIGURATION
DVDD5 DVDD3 DXLPF LOCK/DRD SBQS ALCR DXRC IREF AVDD HPF1 HPF2 AVSS
DVSS C423 TRIN S423
M65827FP
S846 PWM1 PWM2 ROMDT DSCK LRCK DADT CRCF DOTX SCCK EFFK SBCO SCAND
OUTLINE 42P2R (Top view)
MITSUBISHI ELECTRIC
CRCF
SBQS
DVSS
DVDD5
DVDD3
SCCK
SBCO
SCAND LOCK/DRD
AVDD Defect Control Code Serial Checker CIRC Decoder Correction Control SYNC Detector De-Modulator Interpolation Address Generator 18Kbit SRAM Flag Control System Clock Selector Timing Generator De-EMP Digital Audio Interface Micro Computer Track Counter
AVSS
Syndrome Register
BLOCK DIAGRAM
Code Sync Det. SUBQ Register
Slicer
HPF1
CIRC Sequencer
HPF2
Current Control
IREF
Flag Control
Clock Doubler Det. Control S846 S423 C423 DOTX PWM1 PWM2
EFFK
Timing Generator SYNC Protector
Channel Control
MITSUBISHI ELECTRIC
Timing Generator
Attenuate Control
Oscillator
DXLPF
DXRC
Freq. Det.
Block diagram
Phase Det.
TRIN
LRCK
ALCR
DADT
DSCK
ROMDT
ABSOLUTE MAXIMUM RATING
(Ta=25°C unless otherwise noted) Symbol DVDD5-DVSS DVDD3-DVSS AVDD-AVSS Topr Tstg Parameter Power supply voltage Power supply voltage Power supply voltage Input voltage Output voltage Power consumption Ambient temperature Storage temperature Condition Limit -0.3 -0.3 ~+4.5 -0.3 ~+4.5 VSS-0.3ViVDD+0.3 VSSVoVDD ~+70 ~+125 Unit
RECOMMENDED OPERATING CONDITIONS
Symbol DVDD5 DVDD3 AVDD Parameter digital power supply voltage 3.3V digital power supply voltage Analog supply voltage output voltage input voltage Oscillation frequency (X'tal) Single speed Double speed Quad speed times speed times speed Condition 0.7DVDD DVSS 8.4672 16.9344 33.8688 50.8032 67.7376 8.6436 17.2872 34.5744 51.8616 69.1488 Limit DVDD5 0.3DVDD Unit
fOSC
fVCO
Oscillation frequency (VCO)
Single speed Double speed Quad speed times speed times speed
MITSUBISHI ELECTRIC
ELECTRICAL CHARACTERISTICS
(Ta=25°C,DVDD5=5V, DVDD3=3.3V, AVDD=3.3V unless otherwise noted) Symbol Parameter Condition DVDD5 Operating voltage (5V, digital) Ta=-10~+70°C 8X~10X AVDD Operating voltage (3.3V, analog) Ta=-10~+70°C 8X~10X Operating current osc=8.4672MHz vco=8.6436MHz VDD=4.5V,| OH=-0.8mA VDD=4.5V,| OL=0.8mA VIH=4.5V VIL=0.5V Limit Unit
DVDD3 Operating voltage (3.3V, digital) Ta=-10~+70°C
PLL1 PLL2 PLL3
output voltage output voltage input current input current
condition output current VOH=4.5V condition output current VOL=0.5V (EFFK) free frequency (RIREF=110k,RRC=91k) VLPF=1.0V VLPF=1.5V VLPF=3.0V Clock Doubler (S423) free VLPF=1.0V frequency VLPF=1.5V (RIREF=110k,RRC=91k) VLPF=3.0V Pull resistance
MITSUBISHI ELECTRIC
DETAILED DESCRIPTION
interface (1)Connection M65827FP
Signal name
Contents serial data input output shift clock input data latch clock input Data read write control Read, Write)
(2)Mode description
Address
Address
Data control servo, ATT, mute control Configuration Attenuation (Lch) control Attenuation (Rch) control Channel control Playback speed control Analog switch control Monitor output select Track counter (LSB) Track counter (MSB) Track counter interrupt value (LSB) Track counter interrupt value (MSB) Interrupt mask Kick timer Digital audio interface control Reset Sleep Clock disable control Test Mode (For shipping test mode)
MITSUBISHI ELECTRIC
(3)Write timing When write mode. Address(1st byte) data(2nd byte) input with first. Address data captured rising edge latched internal register rising edge MLA. Symbol Term Shift clock pulse width Shift clock time Shift clock hold time Latch clock time Latch clock pulse width Write time Write hold time Unit nsec nsec nsec nsec nsec nsec nsec
Address(1st byte)
Data(2nd byte)
(4)Read timing (Subcode register interface) When subcode register read mode. Subcode data output from falling edge MCK. Refer subcode
Symbol
Term Shift clock pulse width Read time Read hold time
Unit nsec nsec nsec
MITSUBISHI ELECTRIC
Write mode
Address
Register name Reserved BCON BRAK MUTE TRST Reserved
servo, Mute control Default
(STOP) Automatic brake mode Manual brake MUTE Kick timer
(START) Manual brake mode Manual brake MUTE Kick timer
Reserved Don't care. (Start Stop) BCON (Automatic brake control) BRAK (Brake) Disc start When register changes from kick pulse that kick control register address output. After kick mode, disc rotation switched mode automatically. PWM1 (-Signal) PWM2 (+Signal) Disc stop (2-1) BCON=0 (Automatic brake mode) When register changes from "0", brake pulse that calculated internal circuit output time automatically. After brake mode, switches mode. time defined time that internal circuit detect rotation after register changes time detecting rotation monitored signal LOCK/DRD pin. PWM1 (-Signal) PWM2 (+Signal) tmax Detect rotation Kick time* *Kick timer controlled kick control register.
BRAKE (26.4sec max.)
MITSUBISHI ELECTRIC
(2-2) BCON=1 (Manual brake mode) When register change from "0", output brake pulse while BRAK register "1". This mode used stop disc rotation manual operation. PWM1 (-Signal) PWM2 (+Signal) BRAK (Attenuate) ATT=0: Attenuation ATT=1: output data DADT ROMDT attenuated address 03h. MUTE MUTE=0: Mute DADT ROMDT. MUTE=1: Mute DADT ROMDT. TRST (kick timer reset) TRST=0: Kick timer active TRST=1: Kick timer stopped Reserved Don't care BRAKE
MITSUBISHI ELECTRIC
Address
Register name
Configuration Interpolation enable (Audio mode) C1:2 errors correction C2:4 errors correction False-lock protection circuit upper limiter enable Normal gain mode gain mode Interpolation disable (CD-ROM mode) C1:2 errors correction C2:2 errors correction Quasi-lock protection circuit upper limiter disable gain select mode gain mode Inhibit Default
NONAUDIO ECCMOD
FLPDIS PFHEN HFDDIS GAINCNT GAINSEL Reserved NONAUDIO
NONAUDIO=0: Interpolation enabled flag from output audioword unit. NONAUDIO=1: Interpolation disabled, prohibit interpolation. flag from output data byte unit. ECCMOD (Error correction mode) ECCMOD=0: C1:2 error correction,C2:4 errors correction ECCMOD=1: C1:2 error correction,C2:2 errors correction FLPDIS (False lock protection circuit disable) FLPDIS=0: False lock protection circuit FLPDIS=1: False lock protection circuit (Refer address 07h) PFHEN (VCO oscillation frequency upper limiter enable) PFHEN=0: oscillation frequency limiter stopped PFHEN=1: oscillation frequency limiter active Limiter value 8.6436MHz (S:Playback speed) HFDDIS (HFD disable) HFDDIS=0: input enable HFDDIS=1: input disable D5:GAINCNT(CLV gain control) D6:GAINSEL(CLV gain select) GAINCNT=0: Normal gain mode. GAINCNT=1: gain control mode. gain selected normal gain GAINSEL register.
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Normal gain mode (GAINCNT=0) PWM2 PWM1 gain mode (GAINCNT=1,GAINSEL=0) PWM2 PWM1 Mode PWM1=PWM2 Mode PWM1=PWM2 Mode
gain mode (GAINCNT=1,GAINSEL=1) PWM2 PWM1 Mode PWM1=PWM2 PWM1=PWM2 PWM1=PWM2 Mode
MITSUBISHI ELECTRIC
Address
Address Default
Attenuation level control
Coefficience Attenuation Default value
Lcoe=
-(8-n)
Rcoe=
-(8-n)
LATT=20 LOG(Lcoe) LATT=RATT= -12dB
RATT=20 LOG(Rcoe)
When register address "1", output data from DADT ROMDT attenuated attenuation level control register.
MITSUBISHI ELECTRIC
Address
Register name DACIF DDEPASS SFLD AUTOLD
Channel control Default interface mode Automatic de-emphasis mode Software load Automatic load interface mode De-emphasis pass mode Software load Automatic load
Channel control register (Refer Table
(Channel control (Channel control (Channel control (Channel control Table Channel control table output MUTE MUTE MUTE MUTE (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2 output MUTE (L+R)/2 MUTE (L+R)/2 MUTE (L+R)/2 MUTE (L+R)/2 MONAURAL STEREO SWAP Note MUTE
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DACIF (DAC interface) DACIF=0 (DAC interface mode When LRCK "H", selected LRCK DSCK DADT ROMDT
NONAUDIO=0
(Upper)
NONAUDIO=1
(Lower) Upper Lower
DACIF=1 (DAC interface mode LRCK DSCK DADT ROMDT
NONAUDIO=1
When LRCK "H", selected
(Upper)
(Lower)
NONAUDIO=0
Upper Lower
DDEPASS (Digital de-emphasis pass) DDEPASS When emphasis flag detected, internal digital de-emphasis circuit work automatically. DDEPASS Internal digital de-emphasis pass mode. SFLD (Software Load) SFLD When PLCKSEL register address counter value that frames jitter margin. SFLD address counter influenced this resister AUTOLD (Automatic Load) AUTOLD address counter influenced lock status. AUTOLD :When PLCKSEL register address counter value that frames jitter margin LOCK point.
MITSUBISHI ELECTRIC
Address
Register name PLCKSEL CKSEL0 CKSEL1 CKSEL2 PLSEL0 PLSEL1 DXSEL DX24SEL
Play back speed selector mode Default
Xtal mode Master clock selector (Refer Table
clock selector (Refer Table Clock doubler select Clock doubler select
PLCKSEL (PLCK select) PLCKSEL=0: circuit worked Xtal clock. PLCKSEL=1: circuit worked clock. CKSEL0 (Clock select) CKSEL1 (Clock select) CKSEL2 (Clock select) CKSEL2 CKSEL1 CKSEL0 Divide ratio 1/10 1/12 Table Master clock selector
PLSEL0 (PLL clock select) PLSEL1 (PLL clock select) PLSEL1 PLSEL0 Divide ratio Playback speed Don't 2X,4X Table clock selector Recommend value
DXSEL (Clock doubler select) DXSEL=0: Clock doubler does select DXSEL=1: Clock doubler select DX24SEL (Clock doubler select) DX24SEL=0: Double clock Xtal generated. DX24SEL=1: Quad clock Xtal generated. MITSUBISHI ELECTRIC
Address
Register name IREF Reserved HPF1 HPF2 Reserved Reserved Reserved Reserved
Analog switch control Default
IREF (Current reference control resistance select Table Current reference control IREF Sleep Current reference supply
Function
RIREF
IREF
Current Reference Supply
IREF=L: analog block change sleep mode stopping reference current analog circuit. Almost analog circuit stop function, internal does stop oscillation. Because loop filter discharge. need stop oscillation sleep mode, please send command address:CEh, data:01h EFM-PLL charge pump output change power supply mode using analog sleep mode digital sleep mode. IREF=H: reference current analog circuit external resistor. HPF1 (HPF select HPF2 (HPF select Table High Pass Filter HPF2 HPF1 External resistance value
Comparator
RTLC0 RTLC0 RTLC0 RTLC2 RTLC0 RTLC1 RTLC2
HPF1 HPF2 Charge Pump
These resisters used control frequency high pass filter that composed RTLC. This high pass filter used reject defect Example: Finger print )that detected defect signal from SERVO
MITSUBISHI ELECTRIC
RTLC1 RTLC2
RTLC0 RTLC1
PLAYBACK SPEED ANALOG SWITCH CONTROL BLOCK DIAGRAM
CKSEL0~2 Clock Doubler DXSEL 1/10 DXLPF DXRC 1/12 PLCKSEL
CDX1
C423
CDX2
RDXRC
S423 S846
Detector
signal
RTLC0
RTLC1 RTLC2
Comp. HPF2 HPF1
Detector
Frequency Comparator Phase Comparator
CTLC RLPF
Charge Pump
Charge Pump
PLSEL0~1
CLPF
Charge Pump
From Servo Current reference Supply
RIREF
IREF
Fig. Playback speed control analog switch control block diagram MITSUBISHI ELECTRIC
Address
Register name ERM0 ERM1 ERM2 LOCKSEL0 LOCKSEL1 LOCKMOD FLSEL0 FLSEL1
Monitor control Error monitor select (Refer Table6 Default Lock monitor select (Refer Table7) Ignore disc rotation Depend disc rotation
False-lock protection clock duty select register (Refer Table8)
ERM0 (Error monitor select ERM1 (Error monitor select ERM2 (Error monitor select Table Error monitor output error correction mode ERM2 ERM1 ERM0 output(error monitor) C1,C2 decoder discorrectable
decoder detects more than errors decoder detects more than errors decoder detects more than errors decoder detects more than errors decoder detects more than errors decoder detects more than errors decoder detects more than errors
error correction mode ERM2 ERM1 ERM0 output(error monitor) C1,C2 decoder discorrectable Disable Disable
decoder detects more than errors decoder detects more than errors decoder detects more than errors decoder detects more than errors decoder detects more than errors
When ERM0, ERM1 ERM0 "L", error signal synchronize with data from DADT ROMDT pins. other mode used error monitor. LOCKSEL0 (Lock monitor select LOCKSEL1 (Lock monitor select Table LOCK/DRD output
LOCK SEL1 LOCK SEL0
LOCK/DRD output LOCK/DRD SYCLK LOCK
Description BRAK register=0: LOCK monitor BRAK register=1: output Frame LOCK status output Lock, Unlock) LOCK monitor output Lock, Unlock) disc rotation detect Less than 2/3, More than 2/3) MITSUBISHI ELECTRIC
LOCKMOD (Lock mode) LOCKMOD=0: Independent disc rotation, LOCK/DRD becomes when locked frame unit. LOCKMOD=1: LOCK/DRD becomes when disc rotation gets close target, perform mode locked frame unit.
Accelerating Disc rotation LOCK/DRD S/S=0
state
When LOCKMOD after locked frame/16 unit disc rotation mode, LOCK/DRD outputs
When LOCKMOD locked frame/16 unit, LOCK/DRD outputs FLSEL0 (False-lock protection clock duty control register FLSEL1 (False-lock protection clock duty control register Table False-lock protection clock duty control register FLSEL1 FLSEL0 Duty 1/16 1/32 Duty
tFL2 tFL1 tFL1 tFL2
tFL1 tFL1 tFL2 557msec (1/S)
(S:Playback speed)
When mute data continue long time, sometimes become hard lock When FLPDIS register address "L", false-lock protection circuit adds stimulation control terminal which causes lock False-lock protection circuit operates while false-lock protection clock (tFL1) increase oscillation frequency. This effect selected FLSEL1,0 register. This action stopped FLPDIS register address 01h.
MITSUBISHI ELECTRIC
Address
Address (LSB) (MSB) Track counter value=
Track counter control
Default 0000h
2^16 track cross signals counted internal track corss counter. After target track cross number register byte data, track cross counter counted down rising edge track cross signal from servo LSI. Three kinds counter status output interrupt signal from interrupt mask register address 0Ch.
Track counter COUNTER TRIN Optional value target track cross setting address register
1/2N 1/2N-1 1/4N 1/4N-1
N:Target track cross number
Count complete
MITSUBISHI ELECTRIC
Address
Address (LSB) (MSB)
Track counter interrupt value control
CT15CT14 CT13 CT12CT11 CT10
Default 0000h
Track counter interrupt value
optional interrupt value byte track counter interrupt register. Interrupt signal outputs from pin. prohibited interrupt mask register address 0Ch.
MITSUBISHI ELECTRIC
Address
Register name JPEND JPHAF JPCMP TRINO MOVF CLVDOWM CLVUP Reserved
Interrupt mask
Default
interrupt mode Interrupt mode when track counter reches interrupt mode Interrupt mode when track counter reches value interrupt mode Interrupt mode Interrupt mode when track counter reches optional value address Track cross signal output directly
interrupt mode Interrupt mode when over frames jitter margin Rough servo Rough servo Rough servo Rough servo Prohibit
JPEND (Jump end) JPHAF (Jump half) JPCMP (Jump comp) When JPEND register interrupt signal that output counter reaches masked. When JPHAF register interrupt signal that output counter reaches target track jump number masked. When JPCMP register interrupt signal that output counter reaches value interrupt register address 0Ah/0Bh masked. Track counter N:Target track jump number Counter Value TRIN changed track counter setting TRINO (TRIN out) JPCMP JPHAF ttc=1/ftc ftc=track cross frequency L;hold JPEND
1/2N 1/2N-1 1/4N 1/4N-1
TRINO=0: Interrupt signal which D0~D2,D4 outputs pin. TRINO=1: Track cross signal input TRIN outputs pin. this time, interrupt signal D0~D2,D4 output. MOVF (Memory Over Flow) MOVF=0: interrupt signal doesn't generated. MOVF=1: interrupt signal, which generated when memory overflows exceeds frames jitter margin, masked. Interrupt signal becomes when frames detected returns after frames pass. frames detection frames frames µsec MITSUBISHI ELECTRIC S:Playback speed times)
SPMDOWN (Spindle motor down) SPMUP (Spindle motor Rough servo mode realized CLVDOWN CLVUP register. Table Rough servo mode SPMUP SPMDOWN PWM1(-) PWM2(+) Description Normal mode Rough servo mode Rough servo mode Prohibit
D7:Reserved this register. Command advantage about servo follows. Rough servo mode Automatic mode disable mode (Address 0Ch) (Address 00h) (Address 0Ch)
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Address
Kick timer control Default
Address
kinds Kick pulse time data. Kick time calculated follows:
Kick Time
Playback speed
Tkick =8.71 msec (1/S)
Register initial state (=32), kick time single speed (S=1) follows:
Tkick =8.71 msec (1/1) =278.72 msec.
MITSUBISHI ELECTRIC
Address
Register name ACCK0 ACCK1 SOURCE0 SOURCE1 SOURCE2 SOURCE3 DAOSEL Reserved
Digital audio interface control
Cbit Cbit Cbit Cbit Cbit Cbit After channel control
Cbit Cbit Cbit Cbit Cbit Cbit Before channel control
Default
ACCK0 (Crystal accuracy control ACCK1 (Crystal accuracy control ACCK1 SOURCE0 SOURCE1 SOURCE2 SOURCE3 ACCK0 (Source (Source (Source (Source Description Level Level Level Prohibited NO.0) NO.1) NO.2) NO.3) Description Default Source NO.1 Source NO.2 Source NO.3 Table Crystal accuracy control
SOURCE3 SOURCE2 SOURCE1 SOURCE0
Source NO.16 Table Source control
DAOSEL (Digital audio interface select)
DAOSEL=0: Digital influenced channel control attenuation circuit. DAOSEL=1: Digital influenced channel control attenuation circuit.
MITSUBISHI ELECTRIC
Address
Register name SRST HRST TXDIS C4DIS S8DIS S4DIS
Soft reset sleep clock disable control
Soft reset Hard reset Sleep Digital output C432 S846 S423 (PLCKSEL=1) Soft reset Hard reset Sleep Digital output S423 S846 C432
Default
(PLCKSEL=1)
SRST (Soft reset) SRST=0: Soft reset SRST=1: Default value write register soft reset. This register returns after soft reset. HRST (Hard reset) HRST=0: Hard reset HRST=1: resets carried out. Reset state continued while HRST register "1". Reset canceled sending HRST register. (Sleep) SLP=0: Sleep SLP=1: Internal digital circuits into sleep mode reduce power consumption while use. Sleep mode canceled external reset hard reset using HRST register. Using address 06h, analog circuits also into sleep mode TXDIS (Digital disable) TXDIS=0: Digital data output from DOTX pin. TXDIS=1: Digital disabled DOTX fixed C4DIS (C423 disable) C4DIS=0: Crystal system clock output from C423 C4DIS=1: C423 disabled fixed S8DIS (S846 disable) S8DIS=0: S846 output crystal master clock. S8DIS=1: S846 disabled fixed S4DIS (S423disable) S4DIS=0: S423 output crystal system clock. S4DIS=1: S423 disabled fixed (APC ENABLE) APCEN=0: Automatic phase control circuit servo disabled APCEN=1: Automatic phase control circuit servo enabled When PLCKSEL register "1", APCEN register influence function When PLCKSEL register "0", APCEN register ignored. MITSUBISHI ELECTRIC
Read mode
Subcode
SBQS
(Reading completion<10msec recommended)
Bite
Subcode data which stored internal register read serial clock MCU. When signal "H", settled output. inputting between rising edges SBQS pin, output subcode data falling edge MCK. Subcode data output reversed MSB, unit. SBQS output "L", when next condition satisfied internal register read.
<Condition that SBQS outputs "L"> a)CRC flag b)Subcode synchronization signals S0,S1 both detected fixed position. When conditions both satisfied, SBQS outputs "L". SBQS outputs 75Hz (=13.3msec) single speed playback. case S-times speed playback, outputs 75Hz (13.3msec please notice when design. Subcode register valid from rising edge SQBS next rising edge. actual design, please read subcode (Normal speed playback: recommend less than 10msec readout completion)
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2.Subcode interface Among data which converted from bits signals bits symbols, subcode P,Q,R,S,T,U,V output from SBCO inputting shift clock SCCK pin. input frequency SCCK more than 8ck, SBCO becomes "L". SUBCODE FRAME EFFK SCAND S0,S1:SUBCODE SYNC
SF97
SF96 SF97
SBCO SCCK EFFK
Subcode data synchronization status SCAND outputs only when subcode synchronization patterns both detected within both fixed area internal synchronization protection circuit. Subcode check outputs CRCF pin. When CRCF changes "H", when CRCF becomes "L". SCAND CRCF
Correspondence with EIAJ CP-2401 follows: M65827FP SCAND EFFK SCCK SBCO CP-2401 SBSY SFSY CLCK DATA Signal variation Subcode block synchronization Subcode frame synchronization Shift clock Output data
Table Subcode serial interface corresponding table
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3.EFM-PLL CIRCUIT Data slicing M65827FP analog front-end incoming HF(EFM) signal. Using CMOS Analog technology, front comprised automatic slice level control circuit EFM-PLL circuit with internal adjust free VCO. Under figure shows block diagram analog front end. signal sliced comparator level back from through some external becomes because defect disc, then becomes state holds level. extracting clock signal from signal. circuit phase frequency comparator M65827FP wide capture lock range there need adjust VCO. charge-pump output same-time control voltage input VCO.LPF becomes state becomes "H". M65827FP analog switch which exchanges analog external constants playback speed (Refer address 06h). When frequency higher than target frequency, high frequency limiter suppress frequency. High frequency limiter disabled address 01h. frequency limiter used stopping oscillation; controlled this from outside. Sync loss counter becomes active when synchronization signal can't detected, prevent from carrying frequency comparator instant synchronization pattern omission generated from disc defection. IREF reference current input used determine current charge pumps, operating point comparator, free frequency. IREF connected noisy power supply through resistor, would modulated error rate would increase. Therefore, power supply noise IREF must held minimum.
HPF2
HPF1
Charge Pump
Comparator Signal defect Signal
Vref
Charge Pump
Phase Comparator
Charge Pump Comparator 3T/11T Detector Reference clock Freq. Comparator Timer
IREF
Current source control
Limiter
Limiter
demodulation circuit
Frame Sync Detection Block
Sync loss counter
Fig. BLOCK DIAGRAM MITSUBISHI ELECTRIC
Slice level control signal RTLC0 RTLC1 RTLC2 slice level control circuit formed connecting resistors capacitors HF(High frequency signal input) (Slice level control output) pins.
M65827FP
HPF1 HPF1
(Recommend value) CHF= 0.0022µF CTLC= 0.022µF RTLC0= RTLC1= RTLC2= Vin= more than 0.5Vp-p
CTLC
circuit Since adjustment free built adjustment free circuit formed connecting resistor capacitors LPF(Low Pass Filter) pin. (Recommend value) CLPF= RLPF= RPD= 470pF 0.068µF 1.8K 560K
CLPF RLPF
M65827FP
Reference current control Resistors must connected between IREF order reference current used determining current values pin, comparator operating current slice level control circuit, free frequency. (Recommend value) RIREF=
RIREF
M65827FP
IREF
MITSUBISHI ELECTRIC
frequency gain control frequency gain EFM-PLL controlled connecting external resistor between GND.
M65827FP
(Recommend value) RRC=
Oscillation frequency (Hz)
Oscillation frequency (Hz)
RIREF
gain oscillation frequency controlled external resistor minimum oscillation frequency controlled external resistor RIREF. frequency divider ratio internal EFM-PLL also controlled address resister each playback speed. external resistor RIREF decide characteristics free-run frequency internal reference current analog circuit. range free wide, error rate characteristics influenced. range free narrow, characteristics access time influenced. minimum oscillation frequency high, disc rotation detector detect less than normal rotation. minimum oscillation frequency need less than play back frequency. oscillation internal EFM-PLL confirmed EFFK pin. oscillation frequency EFM-PLL EFFK frequency 1176 (8.6472MHztyp (7.35KHztyp (S:Play back speed)
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4.EFM demodulation signal that been converted logic level, clock that been extracted from signal input de-modulator converted symbol. de-modulation depends table book. demodulate, demodulator must synchronized signal each frame. frame synchronization protection circuit holds synchronization spire some lack synchronization pattern, prevents false synchronization demodulator bit-slipping mis-synchronization occurs. frame synchronization control block diagram show fig.4.
Edge Detection
Symbol Conversion Timing Generation 1/17 1/35
Sync Detection
1/588
Reset Window Signal Generation
Sync
Sync Control Window
Lock Detection
Sync loss counter
Control
SYCLK
Fig. Frame synchronize control part block diagram this figure, generation condition counter reset signal timing generation block follows. Reset Sync Sync Window logical multiplication, logical addition)
where Sync, Window mean synchronization signal, detection signal synchronization signal blank, window signal ±7ck. synchronous state, Sync generate simultaneously Sync comes center window. this time, output SYCLK pin, signal synchronized frame unit. Frame sync. status monitored SYCLK mode LOCK/DRD pin. other hand, SYCLK signal includes some bounce even during sync. state when there lack sync. pattern because defect disc. Hence there need debouncing sync. status signal, order monitored MCU. This debouncing accomplished M65827FP monitoring frame sync. status 1/16 frame clock intervals (normal speed: 2.13msec) then outputting result LOCK/DRD pin. monitored status "locked" then output "H", after continuous intervals "unlocked" observed, output becomes "L". Also, when disc rotation does reach target speed, lock monitor become "LOCK" state because wide lock range. such state, when audio disc plays, noise generated releasing mute state when LOCK signal become "H". LOCK signal output when disc rotation mode order prevent noise generation. Output condition LOCK signal address 07h.
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5.CLV servo control control servo control circuit operates using signals. first frequency difference between clock X'tal clock, second phase difference between write frame address read frame address internal RAM. Motor control signals output wave form PWM1 (-signal) PWM2 (+signal) pins. Because these signals internally phase compensated, servo control circuit composed easily using current drivers pins PWM1 PWM2. Kick pulse, Brake pulse, Start/Stop output PWM1 PWM2 under control. When becomes (when signal detected), PWM1 PWM2 automatically fixed duty pulse width prevent disc from overrun. When difference between writing address reading address internal exceeds frames because disc rotation jitter, address crystal loaded address counter reset that jitter margin become maximum. result memory overflow from disc rotation jitter monitored from pin. result expanded frames. Address Reset Frames Timer Phase Compensation
X'tal Address (Reading Address) Address (Writing Address) Crystal Clock Clock
Phase Comparator Frequency Comparator Kick
frames Detection
Disc Control Brake
PWM1 PWM2
Start/Stop
Kick Timer
Brake Timer
Control Fig. block diagram
MODE
KICK
BRAKE
STOP
PWM2 (+signal) PWM1 signal)
Table output state each mode
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Fig.6 shows wave form duty. Disc motor driven waveforms directly, driven analog signal that generated integration waveforms. using analog signal, possible adjust servo loop gain varying direct external component values, case waveforms, servo loop gain determined motor torque, rotating moment disc, turntable, disc clamper.
22.7 µsec PWM2 PWM1 µsec µsec (S:PlayBack Speed)
Duty
WPWM2-WPWM1 WPWM2+WPWM1
frames frames frame
Fig. waveform
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defect signal input) Inputting when signal defect detected prevents disc from incorrect behavior caused scratches dust fastens re-lock after signal recovery. enable inputting input when signal defect. Internal function follows: Internal action when Charge pump both phase comparator frequency comparator state, control voltage held Slice level held output fixed duty Described function canceled inputting HFDDIS register address 01h.
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7.Error correction Correctability C1:2 error correction, C2:4 error correction. C1:2 error correction, C2:2 error correction eraser correction mode) chose address 01h. Error monitor output Error states which detected during decoding output setting register address D7h. When ERM2, ERM1, ERM0 "0", error flag output pin. other case, unit error flag output current frame unit. CD-ROM mode selected NONAUDIO register address 01h, output data interpolated, error status decoder output every data byte that corrected. When NONAUDIO register address01h selects audio mode, every interpolating word byte) outputs error status decoder. Frame unit error monitor output (except ERM2=ERM1=ERM0=L) Frame Frame which error detected Data unit error monitor output (b-1) Audio mode (NONAUDIO register "0") LRCK DADT ROMDT Interpolated word Both DADT ROMDT same output. (b-2) CD-ROM mode (NONAUDIO register "1") LRCK ROMDT Data with error DADT ROMDT output CD-ROM data. DADT output mute data. frame unit error monitor mode check decode condition. When error flag used CD-ROM decoder, needs register address ERM2=ERM1=ERM0=L. Data with error (Mute data) Data with error
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Interpolation When error word judged uncorrectable decoding, average interpolation pre-hold interpolation performed noise product prevented. When error detected word, previous subsequent words error-free, average interpolation attempted. previous subsequent word error, pre-hold tried. When CD-ROM mode selected NONAUDIO register address 01h, interpolation management performed. LRCK
Average Interpolation
Pre-hold
Average Interpolation
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8.Digital audio interface output digital audio interface signal according EIAJ regulation CP-1201 "digital audio interface" output DOTX pin. Validity flag automatically when interpolated word transmitted. data that read from subcode interface block transmitted user data. Channel status clock accuracy source number using interface.
Audio Data
Shift Register Shift Register
Preamble Generator
Bi-phase Mark Modulation
DOTX
Parity Generator
Timing Generator
Source Clock Accuracy (MCU I/F)
Channel Status Register
Shift Register SBCQ~W
Fig. Digital block diagram
Parity L-channel, head blocks L-channel, head blocks R-channel SYNC Extended Audio DATA Channel status User data Validity flag
frame format Subframe Subframe R-channel L-channel Frame
L-channel
R-channel
L-channel
Frame Frame format
Frame
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Source Coding
Channel Coding (Bi-phase mark)
Channel coding (Bi-phase mark modulation) order prevent radiation when digital output used, DOTX output fixed setting address 0Fh. Channel status follows:
from Subcode
COPY
SOURCE0 SOURCE1 SOURCE2 SOURCE3
ACCK0 ACCK1
ID1,COPY,EMP when flag subcode sync S0,S1 detected fixed position. case condition previous data held. validity flag copied with flag audio mode.
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9.Digital de-emphasis M65827FP digital de-emphasis circuit composed first order filter. When internal circuit defect emphasis state, de-emphasis circuit automatically becomes active. When DDEPASS register address "1", de-emphasis pass mode selected. Figure shows characteristics internal de-emphasis filter.
Gain (dB)
Frequency characteristics
5000
10000
Frequency (Hz)
15000
20000
-120 -150 -180 5000
Phase characteristics
Phase (DEG)
10000
Frequency (Hz)
15000
20000
Frequency 0~18kHz 18~20kHz
Deviation* less than±0.2dB less than±0.5dB Gain deviation from imaginary equation follows:
Fig. De-emphasis characteristics
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10.DOscillation circuit Timing generator Internal oscillation mode oscillation circuit formed connecting crystal oscillator, load resistance load capacitors pins
M65827FP
Oscillator 8.4672MHz 16.9344MHz 33.8688MHz
(cf.) 30pF 15pF
(cf.) (Recommend value)
External clock mode When system contains clock, clock input capacitor without using crystal oscillator. input signal logic level, capacitor necessary.
M65827FP
External clock External clock 1000pF AMPLITUDE 2VP-P DVSS DVDD3
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Clock doubler circuit M65827FP clock doubler, double quad frequency master clock generated composing loop filter DXLPF pin. Clock doubler selected address resister. gain internal clock doubler controlled connecting external resistor RDXRC between DXRC GND. minimum frequency determined reference current control resistor RIREF. (Recommend value) CDX1 DXLPF 1.8K CDX1 0.15µF CDX2 470pF RDXRC
M65827FP
RDXRC CDX2 DXRC
Clock output M65827FP various master clock dividers order realize many playback speeds. clocks given master clock divider, system clock half clock output from special pin. C423 output half clock crystal oscillator. C423 used master clock. S846 S423 output clock which synchronized with M65827FP internal system clock. S846 S423 used external digital filter CD-ROM decoder. When PLCKSEL system clock M65827FP will clock generated PLL, clocks S846 S423 synchronized with clock. When PLCKSEL system clock M65827FP will clock generated X'tal, clocks S846 S423 synchronized X'tal clock.
C423 (MCU system clock) C423 outputs half clock oscillator's clock. clock independent playback speed selector clock doubler. used system clock.
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Clock output timing 1.PLCKSEL 0,EXSEL 0,DXSEL MASTER CLOCK 1/3* S846 S423 S846 S423 S846 S423 S846 S423 S846 S423 1/10 1/12 S846 S423 S846 S423 S846 S423 2.PLCKSEL 0,EXSEL 0,DXSEL MASTER CLOCK 1/3* S846 S423 S846 S423 S846 S423 S846 S423 S846 S423 S846 S423 S846 S423 1/12 S846 S423 *When selected, output C846 S846 duty.
1/10
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3.PLCKSEL When PLCKSEL register S846 intervals frame that output clock 588/576 conversion. Other clock data that synchronized with S846 have same interval. Sleep mode
Start Clock doubler unselect. clock doubler mode selected, this step needed. address Digital sleep mode. system clock stop supply internal logic internal SRAM change disable mode. C423 output signal used sleep condition, please only resister address 0Fh. C423 output signal needed, please resister address 05h. Analog sleep mode. reference current analog circuit stopped.
address
address
address
address
Stop oscillation EFM-PLL. charge pump EFM-PLL output internal stop oscillation.
Sleep complete
Start
address
address
initialized hard reset command sleep mode canceled This command same with inputting reset pulse ALCR pin.
Sleep cancel
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Playback speed control selector each clock frequency DXCK C423 96fs 96fs 96fs 64fs 48fs 32fs 24fs 19.2fs 9.6fs 96fs 48fs 32fs 24fs 16fs 12fs 24fs 19.2fs 16fs 9.6fs 16fs 192fs 96fs 64fs 48fs 32fs 12fs 4.8fs 48fs 24fs 16fs 12fs 4.8fs 16fs 24fs 12fs 32fs 16fs 96fs 96fs 96fs 96fs 96fs 96fs 48fs 48fs 48fs 48fs 48fs 48fs 48fs 48fs 48fs 24fs (1/2)fs (1/3)fs (1/4)fs (1/6)fs (1/8)fs (1/10)fs (1/12)fs (1/2)fs (1/3)fs (1/4)fs (1/6)fs (1/8)fs (1/10)fs (1/12)fs 192fs 96fs 48fs PLCKSEL S846 S423 DSCK LRCK
Master clock
CKSEL2 CKSEL1 CKSEL0
192fs
192fs
192fs
192fs
192fs
192fs
192fs
192fs
96fs
96fs
96fs
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96fs
96fs
96fs
96fs
96fs
44.1kHz,S:Playback speed (S-times)
Master clock CKSEL2 CKSEL1 CKSEL0 DXCK 48fs 48fs 48fs 24fs 16fs 48fs 32fs 48fs 48fs 48fs 64fs 48fs 96fs 48fs 96fs 16fs 96fs 96fs 24fs 12fs 96fs 32fs 16fs 96fs 48fs 96fs 64fs 96fs 96fs 192fs 96fs 48fs 96fs PLCKSEL C423 S846 S423 DSCK LRCK
192fs
192fs
48fs 24fs (1/2)fs 32fs 16fs (1/3)fs 24fs 12fs (1/4)fs (1/6)fs (1/8)fs (1/12)fs
192fs
192fs
192fs
192fs
192fs
19.2fs 9.6fs 4.8fs (1/10)fs 192fs 96fs 48fs
192fs
96fs
96fs
48fs 24fs (1/2)fs 32fs 16fs (1/3)fs 24fs 12fs (1/4)fs 16fs 12fs (1/6)fs (1/8)fs (1/12)fs
96fs
96fs
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96fs
96fs
96fs
19.2fs 9.6fs 4.8fs (1/10)fs
96fs
44.1kHz,S:Playback speed (S-times)
PLCKSEL=1, C846 C423 synchronized master clock, S846, S423, DSCK, LRCK synchronized PLL. S846, S423, DSCK, LRCK represent typical state frequency which disc rotation reaches target playback speed.
APPLICATION CIRCUIT
0.1µF 2SC710 4.3k 470PF 0.15µF 1.8k 0.1µF
DVDD3 DXLPF LOCK/DRD SBQS C423 DVDD5 DVSS
33.8688MHz Error monitor System clock Interrupt output MCU) Track cross signal System clock
M65827FP
TRIN S423 S846 PWM1 PWM2 ROMDT DSCK LRCK DADT CRCF DOTX SCCK EFFK SBCO SCAND
interface
ALCR
Spindle motor control
input 0.068µF 1.8k 470PF 0.0022µF signal
DXRC IREF AVDD HPF1 HPF2
(CD-ROM I/F)
Digital audio interface Subcode
0.022µF
AVSS
(Recommend value)
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