(2-Bank 524288-Word 16-Bit) Synchronous DRAM Single ±0.3 power su

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(2-Bank 524288-Word 16-Bit) Synchronous DRAM Single ±0.3 power su

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GLT5160L16
(2-Bank 524288-Word 16-Bit) Synchronous DRAM
Single ±0.3 power supply Clock frequency MHz/ Fully synchronous operation referenced clock rising edge Dual bank operation controlled (Bank Address) latency- (programmable) Burst length- Full Page (programmable) Burst type- sequential interleave (programmable) Industrial grade available Byte control DQMU DQML Column access random Auto precharge bank precharge controlled A[10] Auto refresh Self refresh 4096 refresh cycles LVTTL Interface 400-mil, 50-Pin Thin Small Outline Package (TSOP with lead pitch 60-Ball, 6.4mmx10.1mm VFBGA package with 0.65mm Ball pitch 0.35mm Ball diameter.
GENERAL DESCRIPTION
GLT5160L16 2-bank 524288-word 16-bit Synchronous DRAM, with LVTTL interface. inputs outputs referenced rising edge CLK. GLT5160L16 achieves very high speed data rate MHz, suitable main memory graphic memory computer systems.
May. 2003 (Rev.2.4)
FUNCTIONAL BLOCK DIAGRAM
A[10:0] DQML DQMU Control Signal Buffer Address Buffer Mode Register Memory Array Bank Buffer Memory Array Bank DQ[15:0]
Clock Buffer
Figure (2-Bank 524288-Word 16-Bit) Synchronous DRAM
Signal Description
Signal Type Input Input Description Master Clock: other inputs referenced rising edge CLK. Clock Enable: controls internal clock. When low, internal clock following cycle ceased. also used select auto self refresh. After self refresh mode started, becomes asynchronous input. Self refresh maintained long low. Chip Select: When high, command means Operation. Combination RAS, CAS, defines basic commands. A[10:0] specify Column Address conjunction with Address specified A[10:0]. Column Address specified A[7:0]. A[10] also used indicate precharge option. When A[10] high read write command, auto precharge performed. When A[10] high precharge command, both banks precharged. Bank Address: simply A[11]. specifies bank which command applied. must with ACT, PRE, READ, WRITE commands. Data Data referenced rising edge CLK. Lower Din[7:0] Mask Lower Output[7:0] Disable: When DQML high burst write, lower Din[7:0] current cycle masked. When DQML high burst read, lower Dout[7:0] disabled next cycle. Upper Din[15:8] Mask Upper Output[15:8] Disable: When DQMU high burst write, upper Din(8-15) current cycle masked. When DQMU high burst read, upper Dout[15:8] disabled next cycle. Power Supply memory array peripheral circuitry. VDDQ VSSQ supplied Output Buffers only.
RAS, CAS, A[10:0]
Input Input Input
DQ[15:0] DQML
Input Input Output Input
DQMU
Input
VDD, VDDQ, VSSQ
Power Supply Power Supply
G-LINK Technology
May. 2003 (Rev. 2.4)
Control Circuitry
FUNCTIONAL DESCRIPTION
GLT5160L16 provides basic functions, bank (row) activate, burst read write, bank (row) precharge, auto self refresh. Each command defined control signals RAS, rising edge. addition signals, A[10] used chip select, refresh option, precharge option, respectively. know detailed definition commands, please command truth table.
A[10] Chip Select: L=select, h=deselect ComComComRefresh option @refresh command Precharge Option precharge read/write command Define Basic Com-
Read (READ) [RAS
READ command starts burst read from active bank indicated First output data appears after latency. When A[10] this command, bank deactivated after burst read (auto-precharge, READA).
Write (WRITE) [RAS
WRITE command starts burst write active bank indicated Total data length written burst length. When A[10] this command, bank deactivated after burst write (auto-precharge, WRITEA).
Precharge (PRE) [RAS
command deactivates active bank indicated This command also terminates burst read write operation. When A[10] this command, both banks deactivated (precharge all, PREA).
Activate (ACT) [RAS
command activates idle bank indicated
Auto-Refresh (REFA) [RAS
REFA command starts auto-refresh cycle. Refresh address including bank address generated internally. After this command, banks precharged automatically. other command should asserted until met.
Command Truth Table
Command Deselect Operation Address Entry Bank Activate Single Bank Precharge Precharge Banks Column Address Entry Write Column Address Entry Write with Auto-Precharge Column Address Entry Read Column Address Entry Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Mnemonic DESEL PREA WRITE WRITEA READ READA REFA REFS REFSX Burst Terminate Mode Register TBST A[10 A[9:
High Level, Level, Valid, Don't Care, cycle number
G-LINK Technology
May. 2003 (Rev.2.4)
Function Truth Table
Current State IDLE ACTIVE READ WRITE A[10] A[10] Op-Code, Mode-Add A[10] A[10] A[10] Op-Code, Mode-Add A[10] A[10] A[10] Op-Code, Mode-Add A[10] A[10] A[10] Op-Code, Mode-Add Address Command DESEL TBST READ WRITE PREA REFA DESEL TBST READ READA WRITE WRITEA PREA REFA DESEL TBST READ READA WRITE WRITEA PREA REFA DESEL TBST READ READA WRITE WRITEA PREA REFA ILLEGAL ILLEGAL Bank Active, Latch Auto-Refresh Mode Register Begin Read, Latch Determine AutoPrecharge Begin Write, Latch Determine AutoPrecharge Bank Active ILLEGAL Precharge Precharge ILLEGAL ILLEGAL (Continue Burst END) (Continue Burst END) Terminate Burst Terminate Burst, Latch Begin Read, Determine Auto-Precharge Terminate Burst, Latch Begin Write, Determine Auto-Precharge Bank Active ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL (Continue Burst END) (Continue Burst END) Terminate Burst Terminate Burst, Latch Begin Read, Determine Auto-Precharge Terminate Burst, Latch Begin Write, Determine Auto-Precharge Bank Active ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL Action
G-LINK Technology
May. 2003 (Rev. 2.4)
Function Truth Table (Continued)
Current State READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE -CHARGING ACTIVATING WRITE RECOVERING A[10] A[10] A[10] Op-Code, Mode-Add A[10] A[10] A[10] Op-Code, Mode-Add A[10] A[10] Op-Code, Mode-Add A[10] A[10] Op-Code, Mode-Add A[10] A[10] Op-Code, Mode-Add Address Command DESEL TBST READ READA WRITE WRITEA PREA REFA DESEL TBST READ READA WRITE WRITEA PREA REFA DESEL TBST READ WRITE PREA REFA DESEL TBST READ WRITE PREA REFA DESEL TBST READ WRITE PREA REFA Action (Continue Burst END) (Continue Burst END) ILLEGAL ILLEGAL ILLEGAL Bank Active ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Continue Burst END) (Continue Burst END) ILLEGAL ILLEGAL ILLEGAL Bank Active ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Idle after tRP) (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL (Idle after tRP) ILLEGAL ILLEGAL (Row Active after tRCD (Row Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
G-LINK Technology
May. 2003 (Rev.2.4)
Function Truth Table (Continued)
Current State REFRESHING MODE REGISTER SETTING
Address
Command DESEL TBST READ WRITE PREA REFA DESEL TBST READ WRITE PREA REFA
Action (Idle after tRC) (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Idle after tRSC) (Idle after tRSC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
A[10] A[10] Op-Code, Mode-Add A[10] A[10] Op-Code, Mode-Add
High Level, Level, Don't Care. entries assume that High during preceding clock cycle current clock cycle. Bank Address, Address, Column Address, OPeration. ILLEGAL Device operation and/or data-integrity guaranteed. ILLEGAL bank specified state; function legal bank indicated depending state that bank. bank precharging idle state. precharge bank indicated ILLEGAL bank idle. Must satisfy contention, turn around, write recovery requirements.
G-LINK Technology
May. 2003 (Rev. 2.4)
Function Truth Table
Current State SELF-REFRESH POWER DOWN BANKS IDLE STATE other than listed above
INVALID
Action
Exit Self-Refresh (Idle after Exit Self-Refresh (Idle after ILLEGAL ILLEGAL ILLEGAL (Maintain Self-Refresh) INVALID Exit Power Down Idle (Maintain Self-Refresh) Refer Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer Current State Power Down Refer Function Truth Table Begin Suspend Next Cycle Exit Suspend Next Cycle Maintain Suspend
High Level, Level, Don't Care. High transition will re-enable other inputs asynchronously. minimum setup time must satisfied before command other than EXIT. Power-Down Self-Refresh entered only from Banks Idle State. Must legal command.
G-LINK Technology
May. 2003 (Rev.2.4)
Power Sequence
Before starting normal operation, following power sequence necessary prevent damage malfunction. Apply power start clock. Attempt maintain high, DQMU DQML high condition inputs. Maintain stable power, stable clock, input conditions minimum
Issue precharge commands banks. (PRE PREA) After banks become idle state (after RP), issue more auto-refresh commands. Issue mode register command initialize mode register. After this sequence, SDRAM idle state ready normal operation.
SELF REFRESH
REFS MODE REGISTER
IDLE
AUTO REFRESH
SUSPEND
POWER DOWN
TBST WRIT WRITE WRITE SUSPEND READE READ SUSPEND TBST
WRITE
READ WRITE
READ
WRITE WRITE READE
READE
WRITE SUSPEND
WRITE
READ
READ SUSPEND
POWER APPLIED
POWER
PRECHARGE Automatic Sequence Command Sequence
Figure Simplified State Diagram
G-LINK Technology
May. 2003 (Rev. 2.4)
Mode Register
Burst Length, Burst Type Latency programmed setting mode register (MRS). mode register stores these data until next command, which issued when both banks idle state. After tRSC from command, SDRAM ready command.
LTMODE
LATENC MODE
BURST TYPE
A[10:0]
BURST LENGT
Full Page
Write Burst Length (WBL) Length specified Single
SEQUENTIAL INTERLEAVED
Command Address READ Burst Length WRITE Burst Length
Burst Type Initial Address Sequential
Column Addressing Interleaved
G-LINK Technology
May. 2003 (Rev.2.4)
OPERATIONAL DESCRIPTION
Bank Activate
SDRAM independent banks. Each bank activated command with bank address (BA). indicated address A[10:0] minimum activation interval between bank other bank tRRD.
Precharge
command deactivates bank indicated When both banks active, precharge command (PREA, A[10] available deactivate them same time. After from precharge, command issued.
Command A[9:0] A[10] tRRD tRAS
Precharge
Figure Bank Activation Precharge (BL=4, CL=3)
G-LINK Technology
May. 2003 (Rev. 2.4)
Read
After tRCD from bank activation, READ command issued. output data available after Latency from READ, followed (BL-1) consecutive data when Burst Length start address specified A[7:0], address sequence burst data defined Burst Type. READ command applied active bank, precharge time
(tRP) hidden behind continuous output data case interleaving dual banks. When A[10] high READ command, auto-precharge (READA) performed. command (READ, WRITE, PRE, ACT) same bank inhibited till internal precharge complete. internal precharge start timing depends Latency. next command issued after from internal precharge timing.
Command A[9:0] A[10] Latency tRCD
Burst Length
Figure Dual Bank Interleaving READ (BL=4, CL=3)
Command A[9:0] A[10] tRCD READ
Internal Precharge begins
Figure READ with Auto-Precharge (BL=4, CL=3)
Command CL=3 CL=2 READ Internal Precharge Start Timing
Figure READ Auto-Precharge Timing (BL=4)
G-LINK Technology
May. 2003 (Rev.2.4)
Write
After tRCD from bank activation, WRITE command issued. input data same cycle WRITE. Following (BL-1) data written into RAM, when Burst Length start address specified A[7:0], address sequence burst data defined Burst Type. WRITE command applied active bank, precharge time (tRP) hidden behind continuous input data case
interleaving dual banks. From last input data command, write recovery time RDL) required. When A[10] high WRITE command, auto-precharge (WRITEA) performed. command (READ, WRITE, PRE, ACT) same bank inhibited till internal precharge complete. internal precharge begins after last input data cycle. next command issued after from internal precharge timing.
Command A[9:0] A[10] tRCD Burst Length WRITE tRCD tRDL WRITE
Figure Dual Bank Interleaving WRITE (BL=4)
Command A[9:0] A[10] tRCD tRDL Internal Precharge Begins WRITE
Figure WRITE with Auto-Precharge (BL=4)
G-LINK Technology
May. 2003 (Rev. 2.4)
Burst Interruption
[Read Interrupted Read]
burst read operation interrupted read same other bank. GLT5160L16 allows random column access. READ READ interval minimum.
Command A[9:0] A[10] READ READ
Internal Precharge Start Timing
Figure READ Interrupted READ (BL=4, CL=3)
[Read Interrupted Write]
Burst read operation interrupted write same other bank. Random column access allowed. this case, should controlled adequately using DQMU DQML prevent contention. output disabled automatically cycles after WRITE assertion.
Command A[9:0] A[10] DQMU, DQML control Write control WRITE
Figure READ Interrupted WRITE (BL=4, CL=3)
G-LINK Technology
May. 2003 (Rev.2.4)
[Read Interrupted Precharge]
Burst read operation interrupted precharge same bank. READ interval minimum CLK. command disables data output, depending Latency. figure below shows examples, when data-out terminated.
Command CL=3 Command Command Command CL=2 Command Command
Figure READ Interrupted Precharge (BL=4)
G-LINK Technology
May. 2003 (Rev. 2.4)
[Read Interrupted Burst Terminate]
Similarly precharge, burst terminate command interrupt burst read operation disable data output. READ TBST interval minimum CLK. figure below shows examples, when data-out terminated.
Command CL=3 Command Command Command CL=2 Command Command TBST TBST TBST TBST TBST TBST
Figure READ Interrupted Burst Terminate (BL=4)
G-LINK Technology
May. 2003 (Rev.2.4)
[Write Interrupted Write]
Burst write operation interrupted write same other bank. Random column access allowed. WRITE WRITE interval minimum CLK.
Command A[9:0] A[10] WRIT WRIT WRITE WRITE
Figure WRITE Interrupted WRITE (BL=4)
[Write Interrupted Read]
Burst write operation interrupted read same other bank. Random column access allowed. WRITE READ
interval minimum CLK. input data interrupting READ cycle "don't care". Using DQMU DQML prevent contention optional.
Command A[9:0] A[10] DQMU, WRITE READ WRITE READ
Figure WRITE interrupted READ (BL=4, CL=3)
G-LINK Technology
May. 2003 (Rev. 2.4)
[Write Interrupted Precharge]
Burst write operation interrupted precharge same bank. Random column access allowed. Because write recovery time (tRDL) required between last input data next PRE, data should masked with DQMU DQML shown below.
Command A[9:0] A[10] DQMU, This data should masked satisfy tRDL requirement. WRITE
Figure WRITE Interrupted Precharge (BL=4) [Write Interrupted Burst Terminate]
Burst terminate command terminate burst write operation. this case, write recovery time required bank remains active. figure below shows case words data written. Random column access allowed. WRITE TBST interval minimum CLK.
Command A[9:0] A[10] DQMU, WRITE TBST
Figure WRITE Interrupted Burst Terminate (BL=4)
G-LINK Technology
May. 2003 (Rev.2.4)
Auto Refresh
Single cycle auto-refresh initiated with REFA command. refresh address generated internally. 4096 REFA cycles within refresh Mbit
memory cells. auto-refresh performed each bank alternately (ping-pong refresh). Before performing auto-refresh, both banks must idle state. Additional commands must supplied device before from REFA command.
Deselect A[10:0] Auto Refresh Bank Auto Refresh Bank
Minimum
Figure Auto Refresh
Self Refresh
Self-refresh mode entered issuing REFS command Once self-refresh initiated, maintained long kept low. During selfrefresh mode, asynchronous only enabled input (but asynchronous), other inputs including disabled ignored, power consumption synchronous inputs
saved. exit self-refresh, supplying stable inputs, asserting DESEL command then asserting (REFSX). After from REFSX both banks idle state command issued after tRC, DESEL commands must asserted till then.
Stable command A[10:0] minimum recovery Self Refresh Entry Self Refresh Exit
Figure Self-Refresh
G-LINK Technology
May. 2003 (Rev. 2.4)
Suspend
controls internal following cycle. Figure Figure show works. negating CKE, next internal suspended. purpose suspend power
down, output suspend input suspend. synchronous input except during self-refresh mode. suspend performed either when banks active idle, command following cycle ignored.
ext. int.
Command Command Standby Power Down
Active Power Down
Figure Power Down
Command WRITE
Figure Suspend
G-LINK Technology
May. 2003 (Rev.2.4)
DQMU DQML Control
DQMU DQML dual function signal defined data mask writes output disable reads. During writes, DQMU DQML masks upper lower input data word word. DQMU
DQML write mask latency During reads, DQMU DQML forces upper lower output Hi-Z word word. DQMU DQML output Hi-Z latency
Command DQML DQ[7:0] DQMU DQ[15:8] Masked DQML Disabled DQML WRITE
Disabled DQMU
Masked DQMU
Figure DQMU DQML Function
G-LINK Technology
May. 2003 (Rev. 2.4)
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Symbol VDDQ TOPR TSTG Supply Voltage Supply Voltage Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature comsumer Industrial Storage Temperature Parameter Conditions with respect with respect VSSQ with respect with respect VSSQ Ratings -1.0 -1.0 -1.0 -1.0 1000 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Recommended Operating Conditions +70°C, unless otherwise noted)
Symbol VDDQ Supply Voltage Supply Voltage Output High-Level Input Voltage inputs Low-Level Input Voltage inputs Parameter -0.3 VDDQ Unit
(max) pulse width less than (min) -2.0 pulse width less than
Characteristics +70°C, VDDQ ±0.3V, VSSQ unless otherwise noted)
Symbol Parameter High-Level Output Voltage Low-Level Output Voltage Off-state Output Current Input Current Test Conditions floating VDDQ Unit
Capacitance +70°C, VDDQ ±0.3 VSSQ unless otherwise noted)
Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address Input Capacitance, control Input Capacitance, Input Capacitance, mVrms Test Condition Unit
G-LINK Technology
May. 2003 (Rev.2.4)
Average Supply Current from +70°C, VDDQ ±0.3 VSSQ unless otherwise noted)
Rating (Max) Symbol ICC1S ICC1D ICC2H ICC2L ICC3H ICC3L ICC4 ICC5 ICC6 Parameter Operating Current, Single Bank Operating Current, Dual Bank Standby Current, Standby Current, Active Standby Current, Active Standby Current, Burst Current Auto-Refresh Current Self-Refresh Current Test Conditions min, tCLK min, min, tCLK min, both banks idle, min, both banks idle, min, both banks active, tCLK min, both banks active, tCLK min, tCLK min, both banks active min, tCLK Power Unit
Characteristics +70°C, VDDQ ±0.3 VSSQ unless otherwise noted)
Symbol tCLK tRCD tRAS tCCD tRRD tRSC tRDL tREF Parameter Cycle Time CL=2 CL=3 High Pulse Width Pulse Width Transition Time Input Setup Time (all inputs) Input Hold Time (all inputs) Cycle Time Column Delay Active Time Precharge Time Column Address Column Adress Delay Delay Time Mode Register Cycle Time Last Data-In Precharge Delay Refresh Interval Time 65.6 100k 65.6 100k 65.6 100k 65.6 100k Unit
Input Pulse Levels: with tr/tf +1/+1 Input Timing Measurement Level:
timing referenced input signal crossing
Signal
G-LINK Technology
May. 2003 (Rev. 2.4)
Switching Characteristics +70°C, VDDQ ±0.3 VSSQ unless otherwise noted)
Symbol tOLZ tOHZ Parameter Access Time from CL=2 CL=3 Output Hold Time from Delay Time, Output Impedance from Delay Time, Output High Impedance from CL=2 CL=3 Unit
1.4V VREF VOUT tOLZ tOHZ
Output Timing Measurement Reference Point
GLT5160L16-6/7, Output Load
Figure Output Load Condition
G-LINK Technology
May. 2003 (Rev.2.4)
tRCD tRAS tRDL
DQMU,
A[9:0]
A[10]
WRITE
Figure WRITE Cycle (single bank) BL=4
G-LINK Technology
May. 2003 (Rev. 2.4)
tRDL tRCD tRAS tRCD
tRDL
tRRD
tRAS
DQMU,
A[9:0]
A[10]
WRIT
WRIT
Figure WRITE Cycle (Dual Bank) BL=4
G-LINK Technology
May. 2003 (Rev.2.4)
tRCD tRAS
DQMU,
A[9:0]
A[10]
READ
Figure READ Cycle (Single Bank) BL=4, CL=3
G-LINK Technology
May. 2003 (Rev. 2.4)
tRCD tRRD tRAS
tRCD
tRAS
DQMU,
A[9:0]
A[10]
READ
READ
Figure READ Cycle (Dual Bank) BL=4, CL=3
G-LINK Technology
May. 2003 (Rev.2.4)
tRCD tRAS
DQMU,
A[9:0]
A[10]
WRITE
READ
Figure WRITE READ (Single Bank) BL=4, CL=3
G-LINK Technology
May. 2003 (Rev. 2.4)
tRCD tRRD tRAS
tRCD
tRAS
DQMU,
A[9:0]
A[10]
WRITE
Figure WRITE READ (Dual Bank) BL=4, CL=3
G-LINK Technology
May. 2003 (Rev.2.4)
tRCD tRAS
DQML
DQMU
A[9:0]
A[10]
DQ[7:0]
DQ[15:8]
WRITE
READ
Figure Byte Control WRITE READ (Single Bank) BL=4, CL=3
G-LINK Technology
May. 2003 (Rev. 2.4)
tRCD tRAS tRDL
output disable DQMU,
A[9:0]
A[10]
READ
WRITE
Figure READ WRITE (Single Bank) BL=4, CL=3
G-LINK Technology
May. 2003 (Rev.2.4)
tRCD tRRD tRAS
tRCD
tRAS
tRDL
output disable DQMU,
A[9:0]
A[10]
READ
WRITE
Figure READ WRITE (Dual Bank) BL=4, CL=3
G-LINK Technology
May. 2003 (Rev. 2.4)
tRCD tRDL+
DQMU,
A[9:0]
A[10]
WRITE
Internal Precharge starts this timing depends
Figure Write with Auto-Precharge BL=4
G-LINK Technology
May. 2003 (Rev.2.4)
tRCD
DQMU,
A[9:0]
A[10]
READ
Internal Precharge start CL=3, BL=4 this timing depends
Figure Read with Auto-Precharge BL=4, CL=3
G-LINK Technology
May. 2003 (Rev. 2.4)
High
DQMU,
A[9:0]
A[10]
bank active, must precharged
Figure Auto-Refresh
G-LINK Technology
May. 2003 (Rev.2.4)
DQMU,
A[9:0]
A[10]
bank active, must precharged
Figure Self-Refresh Entry
G-LINK Technology
May. 2003 (Rev. 2.4)
desel
tSRX
DQMU,
A[9:0]
A[10]
Internal Re-start
Figure Self-Refresh Exit
G-LINK Technology
May. 2003 (Rev.2.4)
tRSC tRCD
DQMU,
A[9:0]
Mode
A[10]
bank active, must precharged
READ
Figure Mode Register BL=4, CL=3
G-LINK Technology
May. 2003 (Rev. 2.4)
PACKAGING INFORMATION
VSSQ VDDQ VSSQ VDDQ DQML View DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ VDDQ DQMU
Figure 50-Pin TSOP Assignment
DQ15
DQ14
VSSQ
VDDQ
DQ13
VDDQ
VSSQ
DQ12
DQ11
DQ10
VSSQ
VDDQ
VDDQ
VSSQ
UDQM
LDQM
RAS#
CAS#
Figure 38-1. 60-Ball VFBGA Ball
G-LINK Technology
May. 2003 (Rev.2.4)
21.35max. 20.95±0.1
0.125
+0.05 -0.02
10.6±0.1
Detail
1.0±0.10 0.125±0.075 00~100 Detail 0.5±0.1
0.3+0.1/-0.05
Figure 50-Pin Plastic TSOP Package Dimensions
G-LINK Technology
May. 2003 (Rev. 2.4)
0.08 0.15
CORNER
0.35~0.40(60X)
10.10 0.10
9.10
0.65
0.65 0.15(4X) 0.20 0.21 0.04 3.90 6.40 0.10 1.00 SEATING PLANE 0.27 0.05 0.45 0.03 0.20
60-Ball VFBGA BOTTOM VIEW
G-LINK Technology
May. 2003 (Rev.2.4)
ORDERING INFO
GLT5160L16
Part Number GLT5160L16-10TC GLT5160L16-8TC GLT5160L16-7TC GLT5160L16-6TC GLT5160L16-10FJ GLT5160L16-8FJ GLT5160L16-7FJ GLT5160L16-6FJ GLT5160L16I-10TC GLT5160L16I-8TC GLT5160L16I-7TC GLT5160L16I-6TC GLT5160L16I-10FJ GLT5160L16I-8FJ GLT5160L16I-7FJ GLT5160L16I-6FJ GLT5160L16P-10TC GLT5160L16P-8TC GLT5160L16P-7TC GLT5160L16P-6TC GLT5160L16P-10FJ GLT5160L16P-8FJ GLT5160L16P-7FJ GLT5160L16P-6FJ Mode Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Cycle Time Frequency Interface LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Package 50-Pin Plastic TSOP 50-Pin Plastic TSOP 50-Pin Plastic TSOP 50-Pin Plastic TSOP 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA 50-Pin Plastic TSOP 50-Pin Plastic TSOP 50-Pin Plastic TSOP 50-Pin Plastic TSOP 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA 50-Pin Plastic TSOP 50-Pin Plastic TSOP 50-Pin Plastic TSOP 50-Pin Plastic TSOP 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA 60-Ball VFBGA
G-LINK Technology
May. 2003 (Rev. 2.4)
Parts Numbers (Top Mark) Definition SDRAM SGRAM
Synchronous DRAM SGRAM
SPEED
SDRAM 5ns/200 5.5ns/183 6ns/166 7ns/143 8ns/125 10ns/100
DENSITY
32M,4Bank 1280 128M
CONFIG.
PACKAGE
TSOP(Type sTSOP(Type TSOPll TQFP 60Ball VFBGA
VOLTAGE
Blank 3.3V 2.5V 2.0V
Environmental Option
Pb-free part
Temperature Range POWER
Blank Standard Power Power Extended Temperature Industrial Temperature Blank Commercial Temperature
G-LINK Technology
May. 2003 (Rev.2.4)
G-LINK Technology Corporation, Taiwan
www.glink.com.tw sales@glink.com.tw
TEL: 886-2-2659-9658
1998 G-LINK Technology rights reserved. part this document copied reproduced form means transferred third party without prior written consent G-LINK Technology. Circuit diagrams utilizing G-LINK products included means illustrating typical semiconductor applications. Complete information sufficient design purposes necessarily given. G-LINK Technology reserves right change products specifications without notice. information contained this document does convey license under copyrights, patent rights trademarks claimed owned G-LINK subsidiaries. G-LINK assumes liability G-LINK applications assistance, customer's product design, infringement patents arising from semiconductor devices such systems' designs. does G-LINK warrant represent that patent right, copyright, other intellectual property right G-LINK covering relating combination, machine, process which such semiconductor devices might used. G-LINK Technology's products authorized life support devices systems. Life support devices systems device systems which are: intended surgical implant into human body designed support sustain life; when properly used according label instructions, reasonably expected cause significant injury user event failure. information contained this document believed entirely accurate. However, G-LINK Technology assumes responsibility inaccuracies.

(2-Bank 524288-Word 16-Bit) Synchronous DRAM Single ±0.3 power su

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