GENERAL DESCRIPTION CS5824 receives four sets 7-bit data CMOS logic le

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GENERAL DESCRIPTION CS5824 receives four sets 7-bit data CMOS logic le

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CS5824 28:4 LVDS Transmitter
GENERAL DESCRIPTION CS5824 receives four sets 7-bit data CMOS logic level converts them into four lowvoltage differential signaling (LVDS) serial channels. 7-bit input data referenced CKIN signal. selects either rising falling edge trigger CKIN. Parallel serial conversion performed internal generated clock reference using onchip using CKIN. copy CKIN phaselocked output serial streams, CLKOUT, also converted fifth LVDS channel. CS5824 offers reliable communication media using LVDS signaling provides dealing with wide, high-speed interfaces. This especially attractive interfaces between controller display systems such panels SVGA/XGA/SXGA applications. FEATURES Four 7-bit serial clock LVDS channels. Compatible with ANSI TIA/EIA-644 LVDS standard. Wide CKIN ranges from 31MHz 68MHz. Fully integrated on-chip that provides CKIN serial shift clock. selectable rising falling edge trigger. Support power-down mode. 5V/3.3V tolerant data input. Single 3.3V supply operation. CMOS power consumption. Functional compatible with DS90C385. Available 56-pin TSSOP package.
BLOCK DIAGRAM
D0,D1,D2,D3, D4,D6,D7
SHIFT/LOAD_N
PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER
D8,D9,D12,D13, D14,D15,D18
SHIFT/LOAD_N
PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER
D19,D20,D21,D22, D24,D25,D26
SHIFT/LOAD_N
PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER
D27,D5,D10,D11, D16,D17,D23
SHIFT/LOAD_N
PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER
CKIN
7xCLK PHASE LOCK LOOP SHIFT/LOAD_N
CKOP CKON
SHTDN
CONTROL LOGIC
CS5824
Myson Century, Inc. Taiwan: Industry East III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349
USA: 4020 Moorpark Avenue Suite Jose, 95117 Tel: 408-243-8388 Fax: 408-243-3188
Sales@myson.com.tw www.myson.com.tw Rev.1.4 August 2002 page
CS5824
CONNECTION DIAGRAM
LVDS_VSS LVDS_VDD LVDS_VSS CKOM CKOP LVDS_VSS PLL_VSS PLL_VDD PLL_VSS SHTDN CKIN
CS5824
Figure-1 56-pin TSSOP
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CS5824
DESCRIPTION Name
D0,D1,D2,D3,D4, D6,D7 D8,D9,D12,D13, D14,D15,D18 D19,D20,D21,D22 ,D24,D25,D26 D27,D5,D10,D11, D16,D17,D23 CKIN SHTDN
Description
Parallel data input LVDS channel. D[0] D[7] MSB. shifted first. Parallel data input LVDS channel. D[8] D[18] MSB. Parallel data input LVDS channel. D[19] D[26] MSB. Parallel data input LVDS channel. D[27] D[23] MSB. Parallel input clock.This clock signal used parallel data reference. also used on-chip generate shift clock parallel serial conversion. Rise/fall select. This selects polarity CKIN edge data input. selects CKIN rise edge, selects CKIN fall edge. Shutdown control (low active). When SHTDN low, internal into inhibit mode LVDS output channels shut off. This also resets internal registers. normal operation, SHTDN should high. LVDS channel output. These differential LVDS outputs channel corresponds LVDS channel output. These differential LVDS outputs channel corresponds D12, D13, D14, D15, D18. LVDS channel output. These differential LVDS outputs channel corresponds D19, D20, D21,D22, D24, D25, D26. LVDS channel output. These differential LVDS outputs channel corresponds D27, D10, D11, D16, D17, D23. Clock LVDS channel output. These differential LVDS output replica CKIN signal. CKOP CKON derived from internal phase lock loop phase aligned with serial data output used LVDS receiver reference edge. Power supply circuit. Power ground circuit. Power supply output buffer circuits. Power ground output buffer circuits. Power supply internal circuits. Power ground internal circuits.
Y0P, Y1P, Y2P, Y3P, CKOP, CKON
PLL_VDD PLL_VSS LVDS_VDD LVDS_VSS
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CS5824
FUNCTIONAL DESCRIPTION Control logic There modes this circuit. normal mode, another power down mode. modes controlled control signal "SHTDN". SHTDN high, circuit normal mode, else low, circuit power down mode. power down mode, every block make sure least power consumption. PLL, which phase lock loop, generates seven times clock CKIN. signal "RF" indicates that input data D27) rising edge falling edge trigger CKIN. RF=1, rising edge trigger, else RF=0, falling trigger. This seven times clock CKIN used Parallel LOAD shift Register. also generate control signal "SHIFT/LOAD". This signal also used Parallel LOAD Shift Register indicate when load data shift data. Parallel LOAD shift Register This block transfers bits parallel data into series data out. controlled SHIFT/LOAD. this control signal low, data loaded into shift registers. Next, SHIFT/LOAD turns high shift data from shift register output buffer seven times. load then seven shift. Ref: There properties this block. that supports reference voltage fine output's common mode voltage. Another that generates about (4ns ~6ns) pulse width's power reset signal. When power block would reset power reset signal make sure that circuit would stuck-at some situation care. Output buffer There four data output buffers clock output buffer. Output buffer generates differential pair output that swing under 900mV, common-mode voltage under 1.125V 1.375V.
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CS5824
RECOMMENDED OPERATING CONDITIONS
Symbol Supply voltage High-level input voltage Low-level input voltage Differential load impedance Operating free-air temperature Parameter Unit
TIMING REQUIREMENTS
Symbol Input clock period Pulse duration, high-level input clock Transition time, Input signal Setup time, data, D0~D27 valid before CKIN CKIN(RF Hold time, data, D0~D27 valid after CKIN CKIN(RF Parameter 14.7 0.4tC 32.4 0.6tC Unit
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CS5824
CHARACTERISTICS Symbol
VOC(SS) VOC(PP)
Parameter
Input threshold voltage Differential steady-state output voltage magnitude Change steady-state differential output voltage magnitude between opposite binary states Steady-state common-mode output voltage Peak-to-peak common-mode output voltage High-level input current
Condition
1.375
Unit
1.125
IIH-SHTDN High level input current SHTDN ICC(AVG) Low-level input current Short-circuit output current High-impedance output current Quiescent supply current (average) VO(Yn) Power down SHTDN Enabled, places) Gray_scale pattern 3.3V, 15.38ns Enabled, places) Worst_case pattern 15.38ns
Input capacitance
Note: typical values 3.3V, 25°C.
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CS5824
CHARACTERISTICS Symbol
tskew tc(o) tenable tdisable
Parameter
Output skew Cycle time, Output clock jitter Pulse duration, high-level output clock Transition time, differential output voltage Enable time, SHTDN phase lock valid) Disable time, SHTDN state (CKO low)
Condition
15.38
-0.2 1/7tc-0.2 2/7tc-0.2 3/7tc-0.2 4/7tc-0.2 5/7tc-0.2 6/7tc-0.2
1/7tc+0.2 2/7tc+0.2 3/7tc+0.2 4/7tc+0.2 5/7tc+0.2 6/7tc+0.2
Unit
±100 4/7tc
-0.2
1500
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CS5824
CKIN (RF=0) CKIN (RF=1) Note: Maximum value
Figure-2 Setup Hold Time Definition
49.9±1%(2 Places)
CL=10pF Places)
SCHEMATIC
100% VOD(H) VOD(L)
VOC(PP)
VOC(SS)
VOC(SS)
WAVEFORMS Figure-3 Test Load Voltage Definitions LVDS Outputs
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CS5824
TEST PATTERN
CKIN
D4-7, 12-15, 20-23 D24-27
Figure-4 16-Grayscale Testing Pattern Waveforms
CKIN Even
Figure-5 Worst-case Testing Pattern Waveforms
Figure-6 Timing Waveform's Definitions
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CS5824
TYPICAL CHARACTERISTICS
CKIN
SHTDN
tenable
Invalid
valid valid valid
Note: RF=1 Figure-7 Enabled Time Waveforms
CKIN
tdisable
SHTDN
Note: RF=1 Figure-8 Disabled Time Waveforms
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CS5824
PACKAGE OUTLINE (56-pin TSSOP)
Symbol
Dimensions Millimeters 1.05 0.05 0.17 0.09 13.90 7.80 6.00 0.50 0.90 0.20 0.15 14.00 8.10 6.10 0.50 1.20 0.15 0.27 0.20 14.10 8.40 6.20 0.75
Dimensions Inches 0.041 0.002 0.007 0.004 0.547 0.307 0.236 0.020 0.035 0.008 0.006 0.551 0.319 0.240 0.0197 0.047 0.006 0.010 0.008 0.555 0.330 0.244 0.030
Note: Ordering information; units tube, 2500 units tape reel. Note: CS5824 products keep using original Century logo.
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CS5824
PACKAGING SPECIFICATION
R0.3MAX
Section Chamfer R0.1
R0.3 Typical
Section
Dimension
Symbol Unit:
14.5
+0.1
1.75 ±0.1
11.5 ±0.05
±0.2
12.0 ±0.1
±0.05
±0.05
24.0 ±0.3
Standard Packing Quantity Carrier Tape Width
24mm
Reel Size
330mm
Pocket Pitch
Leader Pockets
Pockets
Quantity (Pcs/Reel)
2500
Reel Taping
Unit:
±0.1
+0.5 -0.2
20.2 ±0.8
±0.5
24.8 +0.3 -0.2
30.2
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CS5824
Leader Part Taped
Leader Part Tape Pin1
Vacant position
cover tape
Vacant position Unwinding Direction
Approval Supplier Packing Material Item
Carrier Tape Cover Tape Plastic Reel
Supplier
ADVANTEK ADVANTEK ADVANTEK
Ordering Information Part Number Prefix
Part Type
5824
Package Type
N:TSSOP
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GENERAL DESCRIPTION CS5824 receives four sets 7-bit data CMOS logic le

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