November 1997 Revised 2003 High-Speed CMOS Logic Dual Monostable

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November 1997 Revised 2003 High-Speed CMOS Logic Dual Monostable

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CD54HC221, CD74HC221, CD74HCT221
November 1997 Revised 2003
High-Speed CMOS Logic Dual Monostable Multivibrator with Reset
Description
'HC221 CD74HCT221 dual monostable multivibrators with reset. external resistor (RX) external capacitor (CX) control timing accuracy circuit. Adjustment provides wide range output pulse widths from terminals. Pulse triggering input occurs particular voltage level related rise fall time trigger pulse. Once triggered, outputs independent further trigger inputs output pulse terminated level Reset pin. Trailing Edge triggering leading-edge-triggering inputs provided triggering from either edge input pulse. power reset. either Mono used each input unused device) must terminated either high low. minimum value external resistance, typically 500. minimum value external capacitance, 0pF. calculation pulse width RXCX 4.5V.
Features
Overriding RESET Terminates Output Pulse
/Title (CD74 HC221 CD74 HCT22 /Subject (High Speed CMOS Logic Dual Monos table Multi-
Triggering from Leading Trailing Edge Buffered Outputs Separate Resets Wide Range Output-Pulse Widths Schmitt Trigger Inputs Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Ordering Information
PART NUMBER CD54HC221F3A CD74HC221E CD74HC221M CD74HC221M96 CD74HC221NSR TEMP. RANGE (oC) PACKAGE CERDIP PDIP SOIC SOIC TSSOP TSSOP PDIP SOIC SOIC
Pinout
CD54HC221 (CERDIP) CD74HC221 (PDIP, SOIC, SOP, TSSOP) CD74HCT221 (PDIP, SOIC) VIEW
2CXRX 1CXRX
CD74HC221PW CD74HC221PWR CD74HCT221E CD74HCT221M CD74HCT221M96
NOTE: When ordering, entire part number. suffixes denote tape reel.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC221, CD74HC221, CD74HCT221 Functional Diagram
2CXRX MONO MONO 1CXRX
TRUTH TABLE INPUTS (Note (Note OUTPUTS
High Voltage Level, Voltage Level, Irrelevant, Transition from High Level, Transition from High Level, High Level Pulse, Level Pulse NOTE: this combination reset input must following sequence must used: must high low; then must high. reset input goes from lowto-high device will triggered.
CD54HC221, CD74HC221, CD74HCT221 Logic Diagram
(10) (11) RESET MIRROR VOLTAGE MASK MAIN PULLDOWN (12) (13)
RXCX
CD54HC221, CD74HC221, CD74HCT221
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. .±25mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, .±50mA
Thermal Information
Package Thermal Impedance, (see Note (PDIP) Package 67oC/W (SOIC) Package. 73oC/W (SOP) Package 64oC/W (TSSOP) Package 108oC/W Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time, Inputs 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max) Input Rise Fall Time, Input Unlimited (Max) 4.5V. Unlimited (Max) Unlimited (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC221, CD74HC221, CD74HCT221
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Device Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. (Note -2.1 -0.02 SYMBOL (mA) 25oC ±0.1 -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1
Input Loading Table
INPUT Inputs UNIT LOADS
NOTE: Unit Load limit specified Electrical Table, e.g., 360µA 25oC.
Prerequisite Switching Function
25oC PARAMETER TYPES Input Pulse Width Input Pulse Width SYMBOL -40oC 85oC -55oC 125oC UNITS
CD54HC221, CD74HC221, CD74HCT221
Prerequisite Switching Function
PARAMETER Input Pulse Width Reset SYMBOL (Continued) 25oC Recovery Time Output Pulse Width 0.1µF Output Pulse Width 28pF, 1000pF, 1000pF, TYPES Input Pulse Width Input Pulse Width Input Pulse Width Reset Recovery Time Output Pulse Width 0.1µF Output Pulse Width 28pF, 1000pF, 1000pF, -40oC 85oC -55oC 125oC UNITS
Switching Specifications Input
TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay, Trigger
SYMBOL
tPLH
50pF 50pF 50pF 15pF
Propagation Delay, Trigger
tPHL
50pF 50pF 50pF 15pF
CD54HC221, CD74HC221, CD74HCT221
Switching Specifications Input
(Continued) 25oC Propagation Delay, tPHL 50pF Output Transition Time tTLH, tTHL 50pF Input Capacitance Pulse Width Match Between Circuits Same Package 1000pF, Power Dissipation Capacitance (Notes TYPES Propagation Delay, Trigger Propagation Delay, Trigger Propagation Delay, Propagation Delay, Output Transition Time tPLH 50pF 15pF tPHL 50pF 15pF tPLH tPHL tTLH, tTHL 50pF 50pF 50pF Input Capacitance Pulse Width Match Between Circuits Same Package 1000pF, Power Dissipation Capacitance (Notes NOTES: used determine dynamic power consumption, multivibrator. (CPD VCC2 where input frequency, output frequency, output load capacitance, supply voltage. -40oC 85oC -55oC 125oC UNITS
PARAMETER Propagation Delay,
SYMBOL tPLH
TEST CONDITIONS 50pF
CD54HC221, CD74HC221, CD74HCT221 Test Circuits Waveforms
trCL CLOCK tfCL CLOCK trCL tfCL 2.7V 0.3V 1.3V 0.3V 1.3V 1.3V
NOTE: Outputs should switching from accordance with device truth table. fMAX, input duty cycle 50%. FIGURE CLOCK PULSE RISE FALL TIMES PULSE WIDTH
NOTE: Outputs should switching from accordance with device truth table. fMAX, input duty cycle 50%. FIGURE CLOCK PULSE RISE FALL TIMES PULSE WIDTH
INPUT
INPUT 2.7V 1.3V 0.3V
tTLH
tTHL
tTLH tPHL tPLH
tTHL
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
1.3V
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
CD54HC221, CD74HC221, CD74HCT221 Typical Performance Curves
PULSE WIDTH (µs) FACTOR 25oC
AMBIENT TEMPERATURE (oC)
VCC, SUPPLY VOLTAGE
FIGURE HC/HCT221 OUTPUT PULSE WIDTH TEMPERATURE
FIGURE HC/HCT221 FACTOR SUPPLY VOLTAGE
PULSE WIDTH (µs) 100K PULSE WIDTH (µs)
4.5V TIMING CAPACITANCE (pF) TIMING CAPACITANCE (pF) 100K
FIGURE HC221 OUTPUT PULSE WIDTH
FIGURE HC/HCT221 OUTPUT PULSE WIDTH
CD54HC221, CD74HC221, CD74HCT221
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
0.775 (19,69) 0.745 (18,92)
0.775 (19,69) 0.745 (18,92)
0.920 (23,37) 0.850 (21,59)
1.060 (26,92) 0.940 (23,88)
0.260 (6,60) 0.240 (6,10)
MS-100 VARIATION
0.070 (1,78) 0.045 (1,14)
0.045 (1,14) 0.030 (0,76)
0.020 (0,51)
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
0.430 (10,92)
14/18 ONLY vendor option
4040049/E 12/2002
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width.
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20)
Gage Plane 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,75) 0.337 (8,55)
0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements.
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Copyright 2003, Texas Instruments Incorporated

November 1997 Revised 2003 High-Speed CMOS Logic Dual Monostable

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