September 1997 Revised 2003 High-Speed CMOS Logic 4-Bit Parallel
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CD54HC195, CD74HC195
September 1997 Revised 2003
High-Speed CMOS Logic 4-Bit Parallel Access Register
Description
device useful wide variety shifting, counting storage applications. performs serial, parallel, serial parallel, parallel serial data transfers very high speeds. modes operation, shift right (Q0-Q1) parallel load, controlled state Parallel Enable (PE) input. Serial data enters first flip-flop (Q0) inputs when input high, shifted direction Q0-Q1-Q2-Q3 following each High clock transition. inputs provide flexibility JKtype input special applications tying pins together, simple D-type input general applications. device appears four common-clocked flip-flops when input Low. After High clock transition, data parallel inputs (D0-D3) transferred respective Q0-Q3 outputs. Shift left operation (Q3-Q2) achieved tying outputs Dn-1 inputs holding input low. parallel serial data transfers synchronous, occurring after each High clock transition. 'HC195 series utilizes edge triggering; therefore, there restriction activity inputs logic operations, other than set-up hold time requirements. asynchronous Master Reset (MR) input sets outputs Low, independent other input condition.
Features
Asynchronous Master Reset
/Title (CD74 HC195 /Subject (High Speed CMOS Logic 4-Bit Parallel Access Register) /Autho
Inputs First Stage Fully Synchronous Serial Parallel Data Transfer Shift Right Parallel Load Capability Complementary Output From Last Stage Buffered Inputs Typical fMAX 50MHz 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, 30%of
Ordering Information PInout
CD54HC195 (CERDIP) CD74HC195 (PDIP, SOIC, SOP, TSSOP) VIEW
PART NUMBER CD54HC195F3A CD74HC195E CD74HC195M CD74HC195NSR CD74HC195PW CD74HC195PWR
TEMP. RANGE (oC)
PACKAGE CERDIP PDIP SOIC TSSOP TSSOP
NOTE: When ordering, entire part number. suffixes denote tape reel.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC195, CD74HC195 Functional Diagram
TRUTH TABLE INPUTS OPERATING MODES Asynchronous Reset Shift, First Stage Shift, Reset First Stage Shift, Toggle First Stage Shift, Retain First Stage Parallel Load
OUTPUT
High Voltage Level Voltage Level, Don't Care Transition from High Level Voltage Level Set-up Time Prior High Clock Transition Voltage Level Set-up Time prior High Clock Transition, (qn) Lower Case Letters Indicate State Referenced Input output) Set-up Time Prior High Clock Transition.
CD54HC195, CD74HC195
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, IGND .±50mA
Thermal Information
Package Thermal Impedance, (see Note (PDIP) Package 67oC/W (SOIC) Package. 73oC/W (SOP) Package 64oC/W (TSSOP) Package 108oC/W Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range (TA) -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER High Level Input Voltage SYMBOL (mA) Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 25oC 1.35 0.26 0.26 ±0.1 -40oC 85oC -55oC 125oC 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 UNITS
CD54HC195, CD74HC195
Prerequisite Switching Function
PARAMETER Clock Frequency SYMBOL fMAX TEST CONDITIONS Pulse Width Clock Pulse Width Set-up Time Clock Hold Time Clock Removal Time, Clock tREM 25oC -40oC 85oC -55oC 125oC UNITS
Switching Specifications
PARAMETER TYPES Propagation Delay, Output
Input TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
SYMBOL
tPLH, tPHL
50pF
Propagation Delay, toOutput
tPLH, tPHL
50pF
Output Transition Times (Figure
tTLH, tTHL
50pF
Input Capacitance Propagation Delay Maximum Clock Frequency Power Dissipation Capacitance (Notes NOTES:
tPLH, tPHL tPHL fMAX
15pF 15pF 15pF 15pF
used determine dynamic power consumption, flip-flop. VCC2 VCC2 where Input Frequency, Output Frequency, Output Load Capacitance, Supply Voltage.
CD54HC195, CD74HC195 Test Circuit Waveforms
RESET CLOCK l/fMAX tPLH tPHL tTLH tTHL CLOCK tPHL tREM tPLH
FIGURE CLOCK PREREQUISITE PROPAGATION DELAYS OUTPUT TRANSITION TIMES
FIGURE MASTER RESET PREREQUISITE PROPAGATION DELAYS
VALID CLOCK
FIGURE PARALLEL ENABLE PREREQUISITE TIMES
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
0.775 (19,69) 0.745 (18,92)
0.775 (19,69) 0.745 (18,92)
0.920 (23,37) 0.850 (21,59)
1.060 (26,92) 0.940 (23,88)
0.260 (6,60) 0.240 (6,10)
MS-100 VARIATION
0.070 (1,78) 0.045 (1,14)
0.045 (1,14) 0.030 (0,76)
0.020 (0,51)
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
0.430 (10,92)
14/18 ONLY vendor option
4040049/E 12/2002
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width.
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20)
Gage Plane 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,75) 0.337 (8,55)
0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
POST OFFICE 655303
DALLAS, TEXAS 75265
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Copyright 2003, Texas Instruments Incorporated
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