User's Guide Order Number C14064 Document DB15-000096-01, Se

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TinyRISC® BDMR4102 Evaluation Board
User's Guide
Order Number C14064
Document DB15-000096-01, Second Edition (January 2000). This document describes revision Logic Corporation's TinyRISC® BDMR4102 Evaluation Board User's Guide will remain official reference source revisions/releases this product until rescinded update. receive product literature, visit http://www.lsilogic.com. Logic Corporation reserves right make changes products described herein time without notice. Logic does assume responsibility liability arising application product described herein, except expressly agreed writing Logic; does purchase product from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties. Copyright 1998-2000 Logic Corporation. rights reserved. TRADEMARK ACKNOWLEDGMENT Logic logo design, TinyRISC, MiniRISC registered trademarks SerialICE trademark Logic Corporation. other brand product names trademarks their respective companies.
Contents
Preface Chapter Introduction Product Summary Product Features Debug Environment Overview Block Diagram Installation Procedures Quick Check 2.1.1 Checking Board 2.1.2 Resolving Problems Jumper Settings 2.2.1 Select PLLN (JP1) 2.2.2 Divide (JP2) Divide (JP3) 2.2.3 Divide (JP4) Divide (JP5) 2.2.4 Endian Selection (JP6) 2.2.5 Probe Enable (JP7) 2.2.6 Alternate Boot Program Selection (JP8) 2.2.7 Boot Device Selection (JP9) 2.2.8 Connect Power (JP10) 2.2.9 Connect Ring Power (JP11) 2.2.10 Connect Core Power (JP12) 2.2.11 Core Voltage Selection (JP13) 2.2.12 Clock Source Selection (JP14) 2.2.13 SerialICE-1 Input Data Selection (JP15) 2.2.14 SerialICE-1 Clock Selection (JP16) 2.2.15 EDO/SDRAM Selection (JP17)
Chapter
2-10 2-11 2-11 2-11 2-11 2-12 2-12 2-12 2-13 2-13 2-13 2-13 2-14
Contents
Chapter
Board Design Layout Board Layout External Interfaces 3.2.1 Expansion Connector (J2) 3.2.2 DIMM Connector (J3) 3.2.3 Serial Port Connector (J10) 3.2.4 RS-232 Serial Connector SerialICE-1 (J9) 3.2.5 SerialICE-1 Connector (J8) 3.2.6 Ethernet Connector (J7) 3.2.7 EJTAG Connectors 3.2.8 Programming Connector (J11) 3.2.9 Power Supply Connector (J1) Indicators 3.3.1 Power 3.3.2 Ethernet LEDs 3.3.3 Debug 3.3.4 7-Segment Display System Memory 3.4.1 Synchronous DRAM Dual Inline Memory Module (SDRAM DIMM) 3.4.2 Static (SRAM) 3.4.3 Boot EPROMs Memory Two-Wire Serial Peripheral Devices 3.6.1 Real-Time Clock (RTC) 3.6.2 EEPROM 3.6.3 Serial Presence Detect (SPD) 3.6.4 LR4102 Interrupts Device Registers 3.7.1 PC16550D UART Registers 3.7.2 Am79C970A Ethernet Controller Equations Schematics Microprocessor Clock Circuitry ROMs, SRAMs, Address Latches Ethernet DRAM Circuitry
Contents
3-10 3-11 3-12 3-13 3-18 3-19 3-20 3-20 3-21 3-21 3-22 3-23 3-23 3-23 3-23 3-24 3-26 3-26 3-28 3-28 3-29 3-29 3-30 3-31
Chapter Chapter
Chapter
Miscellaneous Circuitry Connectors Expansion Connector Boot Device Selection Circuitry Power Reset Circuitry EJTAG Connectors
5-10 5-12 5-14
Bill Materials Customer Feedback
Figures 3.10 3.11 3.12 3.13 3.14 BDMR4102 Block Diagram View BDMR4102 Quick Check Components Jumper Positions Jumper Locations BDMR4102 Evaluation Board BDMR4102 Evaluation Board Layout Expansion Connector DIMM Connector Numbers Serial Port Connector RS-232 SerialICE-1 Connector SerialICE-1 Connector Ethernet 10BASE-T Connector EJTAG Connector EJTAG Connector Programming Connector Power Supply Connector Indicator Positions Ethernet Indicator Positions 7-Segment Display Microprocessor Clock Circuitry ROMs, SRAMs, Address Latches Ethernet DRAM Circuitry Miscellaneous Circuitry Connectors Expansion Connector Boot Device Selection Circuitry Power Reset Circuitry EJTAG Connectors 3-10 3-11 3-12 3-14 3-15 3-18 3-19 3-20 3-21 3-22 5-11 5-13 5-15
Contents
Tables 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 Default Jumper Settings Jumper Settings Jumper Settings Jumper Settings Summary LR4102 Interface Connector Functions Expansion Connector Designations DIMM Connector Assignments Serial Port Connector Assignments RS-232 SerialICE-1 Connector Assignments SerialICE-1 Header Assignments Ethernet Connector Assignments EJTAG Connector Assignment EJTAG Connector Assignments Programming Connector Assignments Ethernet Indicator Functions 7-Segment Display Settings Boot EPROM Addressing Physical Memory Real-Time Clock Addressing Registers EEPROM Addressing EEPROM Addressing BDMR4102 Interrupts UART Registers Ethernet Controller User Registers BDMR4102 Bill Materials 2-10 2-10 2-12 3-10 3-11 3-12 3-14 3-15 3-19 3-21 3-22 3-24 3-25 3-27 3-27 3-28 3-28 3-29 3-30 3-31
Contents
Preface
This book primary reference user's guide TinyRISC® BDMR4102 Evaluation Board. This guide describes basic features evaluation board, including hookup procedures system configuration. additional information that relates board components, refer "Related Publications," page viii.
Audience This document assumes that familiar with microprocessors related support devices. people benefit from this book are:
Organization
Engineers managers evaluating EZ4102 EasyMACRO microprocessor possible system Engineers designing microprocessor into system
This document following chapters:
Chapter Introduction, gives overview BDMR4102 Evaluation Board describes features. Chapter Installation Procedures, explains connect power BDMR4102 Evaluation Board, through quick board check procedure, install jumpers. Chapter Board Design Layout, describes design layout BDMR4102 Evaluation Board. Chapter Equations, provides equations BDMR4102 Evaluation Board. Chapter Schematics, contains schematics BDMR4102 Evaluation Board.
Preface
Chapter Bill Materials, lists bill materials BDMR4102 Evaluation Board.
Related Publications
TinyRISC® EZ4102 EasyMACRO Microprocessor FBusMacro Technical Manual, Logic Corporation, Order Number C14068. TinyRISC® LR4102 Microprocessor Technical Manual, Logic Corporation, Document Number DB14-000081-00. TinyRISC® BDMR4102 Evaluation Getting Started, Logic Corporation, Document Number DB15-000095-00. MIPS PROM Monitor Run-Time Library User's Guide, Logic Corporation, Order Number C14017.A. MIPS SerialICEDebugging Environment User's Guide, Logic Corporation, Order Number C14045. Programming Language, edition 1988, Kerringhan Ritchie, Prentice Hall. PC16550D Universal Asynchronous Receiver Transmitter with FIFOs, National Semiconductor Corp. Am79C970A PCnet-PCI Single-Chip Full-Duplex Ethernet Controller Local Product, Advanced Micro Devices. DS1307/DS1308 Serial Real Time Clock, DALLAS Semiconductor.
Conventions Used This Manual word assert means drive signal true active. word deassert means drive signal false inactive. Hexadecimal numbers indicated prefix "0x"-for example, 0x32CF. Binary numbers indicated prefix "0b"-for example, 0b0011.0010.1100.1111. signals with names ending active LOW; otherwise, signals active HIGH.
viii
Preface
Abbreviations following abbreviations used this manual. Note that abbreviated signal names listed:
CPLD DIMM DRAM EEPROM EJTAG EPROM FAPI JEDEC JTAG Kbyte Mbyte Application Specific Extension Complex Programmable Logic Device Dual Inline Memory Module Deutsches Institut Normung Dual In-line Package Direct Memory Access Dynamic Random Access Memory Extended Data Output Electronically Erasable Programmable Read Only Memory Enhanced Joint Test Action Group Erasable Programmable Read Only Memory FBus Advanced Peripheral Interface FBusMACRO Field Effect Transistor In-Circuit Emulation Instruction Architecture In-System Programmable Joint Electrical Device Engineering Committee Joint Test Action Group Kilo-ohm Kilobyte Light Emitting Diode Megaohm Megabyte
Preface
PBGA PLCC PROM QSOP SDRAM SOIC SPST SRAM SSOP TQFP TSOP TSSOP UART
Programmable Array Logic Plastic Ball Grid Array Peripheral Component Interface Plastic Leaded Chip Carrier Programmable Logic Device Phase-Locked Loop Programmable Read Only Memory Quarter Size Outline Package Right Angle Real Time Clock Synchronous DRAM Small Outline Integrated Circuit Small Outline J-bend Single-Pole Single-throw Static Shrink Small Outline Package Test Access Port Test Point Thin Quad Flat Package Thin Small Outline Package Thin Shrink Small Outline Package Universal Asynchronous Receiver Transmitter Ultra High Speed Microfarad
Preface
Chapter Introduction
This chapter gives overview BDMR4102 Evaluation Board. Topics covered chapter include:
Section 1.1, "Product Summary" Section 1.2, "Product Features" Section 1.3, "Debug Environment Overview" Section 1.4, "Block Diagram"
Product Summary
BDMR4102 Evaluation Board designed with Logic TinyRISC LR4102 reference device. evaluation board
Develop application software before parallel with) designing system chip Evaluate memory system design price/performance trade-off running actual benchmark program
Together with UNIX host, evaluation board provides with complete environment hardware software development debugging. Access off-board logic through 150-pin expansion connector capability download software through communication ports allows verify functionality your system before protoyping hardware.
TinyRISC® BDMR4102 Evaluation Board User's Guide
Product Features
features BDMR4102 Evaluation Board are:
TinyRISC LR4102 processor that provides evaluation target Kbytes on-board SRAM plug-in DRAM DIMM (dual inline memory module); DIMM connector accepts standard 100-pin JEDEC (Joint Electrical Device Engineering Committee) DIMM; Mbyte SDRAM DIMM supplied with board Mbyte Flash EPROM; EPROM contains powerful monitor debugger downloading debugging user programs Kbyte EEPROM configuration parameters Real-Time Clock (RTC) on-board 16550 UART (universal asynchronous receiver/transmitter) with RS-232C serial port SerialICE-1 debugging capabilities EJTAG debugging capabilities 7-segment display status display debug on-board AM79C970A PCnet Ethernet controller with 10BASE-T interface 150-pin expansion connector that provides easy access evaluation board Support devices
Introduction
Debug Environment Overview
BDMR4102 evaluation board offers debug support through PROM monitor-based debug environment (PMON SerialICE-1) EJTAG, nonintrusive on-chip MIPS standard debug environment. more information setting three debug environments, please refer TinyRISC BDMR4102 Evaluation Getting Started. 1.3.0.1 PROM-Based Debug Environments PMON conventional assembly-level PROM-based debug monitor. PMON supports stand-alone operation operation backend source-level debugger. principal disadvantage PMON memory usage. PMON takes approximately Kbyte target memory. BDMR4102 evaluation board shipped with PMON stored lower Kbyte region flash memory U12. Communication done through RS-232 serial port downloaded through RS-232 connector Ethernet connector BDMR4102 evaluation board also offers SerialICE-1 debug environment. SerialICE-1 provides same debug features PMON, does with less than Kbyte target memory. SerialICE-1 with either assembly-level source-level debugger. Communication download provided through SerialICE-1 RS-232 serial port (J9) TTL-level 10-pin header (J8). 1.3.0.2 EJTAG Debug Environment EJTAG (Extended Joint Test Action Group) standard on-chip MIPS debugging environment. EJTAG does require target system memory. EJTAG, user needs memory BDMR4102 evaluation board since programmable memory controller. user either accomplish this application code sample bootup code provided upper Kbyte region Flash EPROM memory. user must this bootup code before downloading application programs evaluation board using assembly-level source-level debugger. Communication download occurs through EJTAG connector
Debug Environment Overview
Block Diagram
Figure shows high level block diagram BDMR4102 evaluation board. Figure BDMR4102 Block Diagram
Mbyte EPROM Mbytes SDRAM Kbytes SRAM Mbyte Flash EPROM
SerialICE-1 Circuitry
EJTAG Connectors Debug
LR4102 Microprocessor
Address
Data
EEPROM
Devices
16550 UART
Ethernet Control
7-Segment Display
150-Pin Expansion Connector Serial Port 10BASE-T Ethernet Connector
Introduction
Chapter Installation Procedures
This chapter describes installation procedure BDMR4102 Evaluation Board. Topics covered chapter include:
Section 2.1, "Quick Check" Section 2.2, "Jumper Settings"
Quick Check
Figure shows simplified view BDMR4102 board with components referenced this section. Figure 3.1, page 3-2, shows more detailed view board. Major connectors LR4102 processor shown Figure provide orientation.
TinyRISC® BDMR4102 Evaluation Board User's Guide
Figure
View BDMR4102 Quick Check Components
SerialICE-1 Header Reset Button
Ethernet (RJ45) Port
SerialICE-1 RS232 Port
Serial Port Mbyte
Oscillator
Mbyte Flash EPROM
EPROM Microprocessor mproc
Power
Power Supply Connector mproc Crystal
Core Power
LR4102 Reference Device Kbyte EEPROM
Pins
100-Pin DIMM Connector
Pins
150-Pin Connector
2.1.1 Checking Board
check evaluation board booting EPROM monitor program. BDMR4102 board shipped with monitor program burned into AM29F080 Flash EPROM location U12. following procedure check board:
Installation Procedures
Using standard RS-232C cable, connect serial port (J10) following: terminal console. workstation running terminal emulator program. Standard VT100-type terminals AT-compatible operating VT100 emulation mode suitable. emulate VT100 terminal Hyperterminal application Microsoft Windows.
terminal software following: 9600 baud data bits parity stop
Section 3.2.3, "Serial Port Connector (J10)," page describes serial port connector. following jumpers: (Refer Figure 2.3) Remove select Flash EPROM location boot device. Remove select correct boot program within Flash EPROM. Remove select big-endian addressing mode.
Logic provides adapter with BDMR4102 board. Power from adapter supplied board means standard power connector location Figure shows position connector evaluation board. Section 3.2.9, "Power Supply Connector (J1)," page 3-19, describes connector. apply power board, plug power connector adapter into on-board power connector (J1) plug three-pin connector adapter into main building power. power supply provided with board will operate with power range V-240 50/60 When power applied board, power lights
Quick Check
following events then occur: terminal screen displays banner. monitor prompt appears screen. terminal displays start-up message.
After start-up message, monitor displays following prompt: PMON> This prompt vary slightly depending terminal display type settings. When prompt, system ready use.
2.1.2 Resolving Problems
nothing appears screen when power board, check following: power adapter plugged into BDMR4102 board into building supply? lit? RS-232C cable correctly installed location J10? jumpers correct operation, described Section 2.1.1, step using operating standard VT100 terminal emulation mode? problems persist, contact your Logic sales representative further assistance.
Installation Procedures
Jumper Settings
BDMR4102 board both two- three-pin jumpers. shown Figure 2.2, two-pin jumpers described being either (installed) (not installed), three-pin jumpers described being positions 1-2, positions 2-3, out. Figure
Jumper Positions
Positions Positions
Two-Pin Jumpers
Three-Pin Jumpers
jumpers identified number form JPnn (JP1, JP2, forth) BDMR4102 board. Figure page shows locations jumpers evaluation board. Connectors shown Figure page provide proper orientation. Table page summarizes jumper functions indicates defaults (factory settings). Sections 2.2.1 through 2.2.15 provide more detailed information about jumper settings. After performing Quick Check Section 2.1, disconnect power connection from board jumpers.
Jumper Settings
Figure
Jumper Locations BDMR4102 Evaluation Board
Boot Device Selection JP16 SerialICE-1 Clock Selection JP15 SerialICE-1 Input Data Selection Used Factory Testing Endian Selection Divide Control PCLK Freq. Divide Divide Clock Control PBCLK Freq. Divide Clock PLLN Selection JP14 Clock Source Selection
Alternate Boot Program Selection
JP16
JP15
When installed, these jumpers related input LR4102 microprocessor low.
LR4102 Microprocessor
JP13 JP12 JP11 JP10 JP17
JP13 Core Voltage Selection JP12 Connect/ Disconnect LR4102 Core Power JP11 Connect/Disconnect LR4102 Power
JP10 Connect/Disconnect Power
JP17 Address Line Configuration SDRAM DRAM
Installation Procedures
Table
Jumper
Default Jumper Settings
Jumper Name Select PLLN Setting (Default) Default: Table Default: Table (Default) Function Implemented Selects (phase-locked loop) circuit clock source LR4102. Selects input clock clock source LR4102. Control PBCLK frequency. default settings select PBCLK frequency equal PCLK. Control PCLK frequency. default settings select PCLK frequency equal input clock. Selects endian mode. Selects little endian mode. Used only during factory testing. install. Reference Section 2.2.1, page
Divide C[1:0]
Section 2.2.2, page
Divide A[1:0]
Section 2.2.3, page 2-10
Endian Selection
Section 2.2.4, page 2-11 Section 2.2.5, page 2-11 Section 2.2.6, page 2-11
Probe Enable
(Default)
Alternate Boot Program Selection
Inverts input boot device allow selection alternate boot program. input boot device inverted. Selects EPROM boot device. Selects Flash EPROM boot device. Connects power onboard devices. Disconnects power from onboard devices test purposes.
(Default) Boot Device Selection (Default) JP10 Connect (Default)
Section 2.2.7, page 2-11
Section 2.2.8, page 2-12
(Sheet
Jumper Settings
Table
Jumper JP11
Default Jumper Settings (Cont.)
Jumper Name Connect Power Setting (Default) (Default) Core Power Selection (Default) Oscillator/ Crystal Clock Selection Positions Positions (Default) Positions (Default) Positions Function Implemented Connects power LR4102 VDDIO pins. Disconnects power from LR4102 VDDIO pins test purposes. Connects power LR4102 VDD_CORE pins. Disconnects power from LR4102 VDD_CORE pins test purposes. Sets VDD-CORE power supply voltage Sets VDD-CORE power supply voltage Enables oscillator provide clock input LR4102 microprocessor. Enables crystal provide clock input LR4102 microprocessor. connector provides data. Reference Section 2.2.9, page 2-12
JP12
Connect Core Power
Section 2.2.10, page 2-12
JP13
Section 2.2.11, page 2-13
JP14
Section 2.2.12, page 2-13
JP15
SerialICE-1 Input Data Selection
Section 2.2.13, page 2-13
connector provides data. on-board oscillator (U6) supplies SerialICE-1 clock. connector provides SerialICE1 clock. Address lines configured SDRAM. Section 2.2.15, page 2-14 Section 2.2.14, page 2-13
SerialICE-1 Clock Selection
Positions (Default) Positions
JP17
SDRAM/EDO Selection- Controls Address Input DRAM DIMM Module
Positions (Default) Positions
Address lines configured (extended data output) DRAM.
(Sheet
Installation Procedures
2.2.1 Select PLLN (JP1)
This jumper selects clock source LR4102 microprocessor. default setting installed. When installed, SELECT_PLLN input clock circuitry microprocessor tied low. This means that reset, CLKSEL SCR2 register LR4102 cleared, thus selecting (phase-locked loop) circuit clock source LR4102. When installed, SELECT_PLLN input clock circuitry microprocessor tied high. This means that reset, CLKSEL SCR2 register LR4102 chip set, thus selecting input clock clock source LR4102. software time overwrite CLKSEL SCR2 register originally this jumper.
2.2.2 Divide (JP2) Divide (JP3)
These jumpers control PBCLK frequency. PBCLK used clock devices connected LR4102 microprocessor. When jumpers installed, they inputs clock circuitry microprocessor low. When they installed, inputs high. reset, values these jumpers loaded into CLKDC[1:0] bits LR4102 SCR2 register. TinyRISC EZ4102 EasyMACRO Microprocessor FBusMacro Technical Manual more information. frequency PBCLK derived dividing PCLK value CLKDC[1:0]. Table shows CLKDC values provided jumper settings clock frequencies derived from these values.
Jumper Settings
software time overwrite DIVC[1:0] values these jumpers SCR2 register. Table
Setting (Default)
Jumper Settings
Setting (Default) CLKDC[1:0] Values 0b00 0b01 0b10 0b11 PBCLK Frequency PCLK divided PCLK divided PCLK divided PCLK divided
2.2.3 Divide (JP4) Divide (JP5)
These jumpers control PCLK frequency setting multiplication value LR4102 circuit. PCLK processor core clock, synthesized multiplying input clock value jumpers JP5. Table shows DIVA[1:0] inputs provided jumpers lists PCLK frequencies derived from these inputs. Table Jumper Settings
DIVA[1:0] Inputs 0b00 0b01 0b10 0b11 Max. PCLK Frequency1 Input*21 Input*41 Input*81 Input*161
Setting (Default)
Setting (Default)
Values
maximum value value derived after reset. values shown right-hand column maximum values possible. lower value PCLK obtained using software program CLKDB[3:0] SCR2 register LR4102. cannot control DIVA value using software.
2-10
Installation Procedures
2.2.4 Endian Selection (JP6)
Jumper selects between endian little-endian addressing mode. When jumper installed, endian input board, BIG_ENDIANP, tied low, meaning board little-endian mode. When jumper installed, BIG_ENDIANP tied high, causing board function big-endian mode. default big-endian mode.
2.2.5 Probe Enable (JP7)
Jumper used only factory testing. install
2.2.6 Alternate Boot Program Selection (JP8)
When installed, inverts most significant address (A19) input boot device. When installed, inverted. default installed. This jumper used select between boot programs installed same Mbyte EPROM. Each boot EPROM accommodate boot programs, provided that neither program larger than Kbytes. alternate program should programmed address 0x80000 boot EPROM memory. Setting most significant address EPROM HIGH (that installing JP8) allows alternate program selected.
2.2.7 Boot Device Selection (JP9)
BDMR4102 Evaluation Board accommodates boot devices: EPROM socket location U25, onboard Flash EPROM location U12. Jumper selects between system boot devices. default setting installed, causing system boot from Flash EPROM location U12.
Jumper Settings
2-11
maps address selected boot device MIPS boot vector address (0x1FC0 0000). Table shows address spaces each boot device. Table
Setting
Jumper Settings
Boot Device (Board Location) EPROM (U25) Boot Device Address Space 0x1FC00000- 0x1FCFFFFF 0x1FC00000- 0x1FCFFFFF Alternate Device (Board Location) Flash EPROM (U12) EPROM (U25) Alternate Device Address Space 0x1FD00000- 0X1FDFFFFF 0x1FD00000- 0X1FDFFFFF
(Default)
Flash EPROM (U12)
2.2.8 Connect Power (JP10)
When jumper JP10 installed, power supplied on-board devices. When jumper installed, there power supply these devices. This jumper allows measure current used devices. this, remove jumper connect current meter between terminals. default setting installed.
2.2.9 Connect Ring Power (JP11)
When jumper JP11 installed, power supplied LR4102 VDDIO pins. When jumper installed, there power supply these pins. This jumper allows measure current used LR4102 devices. this, remove jumper connect current meter between terminals. default setting installed.
2.2.10 Connect Core Power (JP12)
When jumper JP12 installed, power supplied LR4102 VDD_CORE pins. When jumper installed, power supplied these pins. This jumper allows measure current used LR4102 internal logic. this, remove jumper connect current meter between terminals. default setting installed. VDD_CORE provides power everything LR4102 ring.
2-12
Installation Procedures
2.2.11 Core Voltage Selection (JP13)
Jumper JP13 selects power input microprocessor core. When installed, JP13 selects When installed, supplied core. default setting installed. Note that LR4102 chip designed operation does function when VDD_CORE VDD_CORE jumper JP14 must positions 1-2, oscillator with times desired PCLK frequency must installed location must also remove deselect circuit when board reset.
2.2.12 Clock Source Selection (JP14)
three-position jumper, JP14, selects clock input LR4102 microprocessor. When this jumper installed positions 1-2, oscillator location supplies clock. When installed positions 2-3, crystal supplies clock. default positions 2-3.
2.2.13 SerialICE-1 Input Data Selection (JP15)
three-position jumper, JP15, selects source SerialICE-1 input data. When this jumper installed positions 1-2, data input comes from connector When jumper positions 2-3, data comes from connector default positions 1-2.
2.2.14 SerialICE-1 Clock Selection (JP16)
three-position jumper, JP16, selects source SerialICE-1 clock. When this jumper installed positions 1-2, on-board oscillator location supplies clock. clock supplied should desired baud rate. When jumper installed positions 2-3, clock signal supplied from connector location default positions 1-2.
Jumper Settings
2-13
2.2.15 EDO/SDRAM Selection (JP17)
Jumper JP17 enables configure address lines that either SDRAM DRAM devices DIMM installed DIMM slot location This accomplished routing correct signal DIMM. SDRAM devices, defined bank address (BA0); DRAM devices, defined address (A11). configure BDMR4102 board SDRAM, jumper installed positions 1-2, routing address FADDRP27 DIMM socket. configure BDMR4102 board DRAM, jumper installed positions 2-3, routing address FADDRP11 default positions 1-2.
2-14
Installation Procedures
Chapter Board Design Layout
This chapter describes board design layout BDMR4102 Evaluation Board well elements design architecture. Topics covered chapter include:
Section 3.1, "Board Layout" Section 3.2, "External Interfaces" Section 3.3, "Indicators" Section 3.4, "System Memory" Section 3.5, "Memory Map" Section 3.6, "Two-Wire Serial Peripheral Devices" Section 3.7, "Device Registers"
TinyRISC® BDMR4102 Evaluation Board User's Guide
Board Layout
Figure shows placement major components BDMR4102 Evaluation Board. Note that board drawn scale figure should used manufacturing aid. Figure BDMR4102 Evaluation Board Layout
Ethernet 10BASE-T SerialICE-1 Connector Header SeriaIICE-1 RS232 Port Serial Port
Ethernet Status Lights Debug Probe Factory Only
Battery Real-Time Oscillator Clock Real-Time Clock Prog. Mbyte Flash EPROM
Ethernet Transformer Debug
JP16 JP15
16550 UART
Microprocessor
mproc
Mbyte EPROM 7-Segment Display Power Supply Connector JP12 JP11
Power
EJTAG
AM79C970A PCnet
Ethernet Controller
JP14 µproc Crystal
JP13
Core Power
LR4102 Reference Device
Kbyte EEPROM Kbytes SRAMs JP17 100-pin DIMM Connector
JP10
Kbytes SRAMs
Voltage Regulators
150-Pin Connector
Board Design Layout
External Interfaces
This section describes external interfaces BDMR4102 Evaluation Board. connectors that implement interfaces connect external logic, download software, connect Ethernet, debug board, program PAL, forth. This section describes connectors listed Table 3.1. Figure (page 3-2) shows positions connectors board.
Table Summary LR4102 Interface Connector Functions
Board Location
Connector Name Power Supply Expansion
Description Standard power connector 150-pin connector
Application Connects board power supply. Connects external modules board; expands design debug capabilities.
Main Ref. Page 3-19 Page
DIMM
100-pin DIMM connector Allows DIMM module installed board, either SDRAM (Synchronous DRAM) (Extended Data Output). 16-pin connector Provides basic break control. Allows download programs data memory. this connector connector debug board. Provides same debugging capabilities plus trace capability. Used only factory testing. this connector.
Page
EJTAG
Page 3-13
EJTAG
52-pin connector
Page 3-15
Debug Probe
20-pin connector
External Interfaces
Table Summary LR4102 Interface Connector Functions (Cont.)
Board Location
Connector Name Ethernet 10BASE-T
Description RJ45 connector
Application Connects board Ethernet using standard 10BASE-T plug. Provides logic level SerialICE-1 interface. need special equipment this interface. Provides standard RS232 serial connector SerialICE-1. Allows connect standard terminal RS232 serial communication. Allows program (U42).
Main Ref. Page 3-12
SerialICE-1
10-pin header
Page 3-11
RS232 SerialICE-1
DB-9 connector
Page 3-10 Page
Serial Port
DB-9 connector
Programming Port 8-pin header
Page 3-18
3.2.1 Expansion Connector (J2)
150-pin connector (J2) lets expand your design debugging capability include external logic. Figure page shows numbers expansion connector Table page lists assignments. TinyRISC CW4102 Reference Device Technical Summary document provides signal definitions. Note that expansion connector signals buffered BDMR4102 Evaluation Board. should buffer these signals when using them evaluation board.
Board Design Layout
Figure
Expansion Connector
Position Position Indicator
Table
Expansion Connector Designations
Signal Name Ground Ground FADDR12 FADDR13 FADDR14 FADDR15 FADDR16 FADDR17 FADDR18 FADDR19 Ground FADDR20 FADDR21 FADDR22 FADDR23 AFADDR24 FADDR25 FADDR26 Signal Name Ground Ground FADP00 FADP01 FADP02 FADP03 FADP04 FADP05 FADP06 FADP07 FADP08 FADP09 FADP10 FADP11 FADP12 FADP13 FADP14 FADP15
Signal Name Ground Ground Ground INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 T0_OUTN T1_OUTN Ground BOOTCFG0 BOOTCFG1
External Interfaces
Table
Expansion Connector Designations (Cont.)
Signal Name Ground SDCASN SDDDMP0 SDCSN0 FADDR01 FADDR03 FADDR05 FADDR07 FADDR09 FADDR11 FADDR28 SDCSN1 SDDMP2 SDDMP3 Ground FRAMEN IRDYN TRDYN STOPN DEVSELN PBCLK Ground CEBEN0 CEBEN1 CEBEN2 Signal Name Ground SDWEN SDDMP1 SDRASN FADDRP00 FADDRP02 FADDRP04 FADDRP06 FADDRP08 FADDRP10 FADDRP27 SDCLK0 Ground FADP16 FADP17 FADP18 FADP19 FADP20 FADP21 FADP22 FADP23 Ground FADP24 FADP25 FADP26
Signal Name BOOTCFG2 CWAITP RSTOUTN RESETN Ground Ground GPWEN0 GPWEN1 GPWEN2 GPWEN3 GPRDN Ground GPI00 GPI01 GPI02 GPI03
Board Design Layout
Table
Expansion Connector Designations (Cont.)
Signal Name CEBEN3 SDONEP FALEP EXP_GNTN EXP_REQN Ground Ground Signal Name FADP27 FADP28 FADP29 FADP30 FADP31 Ground Ground
Signal Name Ground Ground Ground +3.3 +3.3 +3.3
connected
3.2.2 DIMM Connector (J3)
100-pin DIMM connector (J3), allows install DIMM (Dual Inline Memory Module) board. connector accommodates DIMMs populated with SDRAM devices. Figure shows numbers this connector Table lists assignments. Table page 3-8, "NC" Signal Name column signifies Connection listed pin. Figure
Pins
DIMM Connector Numbers
Pins
Keys
External Interfaces
Table DIMM Connector Assignments
Signal Name Ground FADP00 FADP01 FADP02 FADP03 +3.3 FADP04 FADP05 FADP06 FADP07 SDDMP0 Ground FADDRP00 FADDRP02 FADDRP04 FADDRP06 FADDRP08 FADDRP10 FADDRP28 +3.3 SDCLK0 Signal Name Ground +3.3 SDWEN SDCSN0 SDCSN0 +3.3 Ground SDDMP2 FADP16 FADP17 FADP18 FADP19 +3.3 FADP20 FADP21 FADP22 FADP23 Ground GPI01 GPI00 +3.3 Signal Name Ground FADP08 FADP09 FADP10 FADP11 +3.3 FADP12 FADP13 FADP14 FADP15 SDDMP1 Ground FADDRP01 FADDRP03 FADDRP05 FADDRP07 FADDRP09 FADDRP27 (BA0) FADDRP11 (A11) FADDRP11 +3.3 SDRASN SDCASN SDCLK0
Signal Name Ground +3.3 SDCASN SDCSN1 SDCSN1 +3.3 Ground SDDMP3 FADP24 FADP25 FADP26 FADP27 +3.3 FADP28 FADP29 FADP30 FADP31 Ground Ground Ground Ground
signal depends upon setting JP17. Refer Section 2.2.15, "EDO/SDRAM Selection (JP17)," page 2-14.
Board Design Layout
3.2.3 Serial Port Connector (J10)
9-pin serial port connector (J10) provides connections serial port devices. Figure shows numbers this connector Table lists assignments. PROM Monitor initializes serial port operate 9600 baud with eight bits data, parity bit, stop bit. Figure Serial Port Connector
Transmitted Data Received Data Data Carrier Detect Data Ready Request Send connected Clear Send Data Terminal Ready Ground
Table Serial Port Connector Assignments
Signal Name Description Data Carrier Detect (Not Connected) Received Data Transmitted Data Data Terminal Ready (Not Connected) Ground Data Ready (Not Connected) Request Send Clear Send Connected
External Interfaces
3.2.4 RS-232 Serial Connector SerialICE-1 (J9)
DB-9 connector (J9) allows debug board using SerialICE-1 through RS-232 cable. Pins jumper JP15 need shorted route RS-232 signal ICERXP LR4102 ICEport. Figure shows numbers this connector Table lists signal assignments. Figure RS-232 SerialICE-1 Connector
Transmitted Data Received Data Data Carrier Detect Data Ready Request Send connected Clear Send Data Terminal Ready Ground
Table RS-232 SerialICE-1 Connector Assignments
Signal Name Description Data Carrier Detect (Not Connected) Received Data Transmitted Data Data Terminal Ready (Not Connected) Ground Data Ready (Not Connected) Request Send (Not Connected) Clear Send (Not Connected) Connected
3-10
Board Design Layout
3.2.5 SerialICE-1 Connector (J8)
10-pin header (J8) allows debug board using SerialICE-1. Pins jumper JP15 need shorted route CONN_RXP signal ICERXP LR4102 ICEport. Figure shows numbers this connector Table lists signal assignments. Figure SerialICE-1 Connector
Ground ICECLKP Ground
CONN_RXP ICE_TXP Input
Input from Oscillator Ground Ground
SI_RESET
Table SerialICE-1 Header Assignments
Signal Name CLK_OUT CLK_IN SI_RESET CONN_RXP ICE_TXP Description Supplies clock output from oscillator (U6). Ground. Ground. Provides clock source LR4102 ICEport Ground Ground System Reset Received Serial Data Transmitted Serial Data
External Interfaces
3-11
3.2.6 Ethernet Connector (J7)
Ethernet 10BASE-T connector (J7) standard RJ45 connector that allows connect board Ethernet. Figure shows numbers this connector Table lists assignments. Figure
connected Received Data Transmitted Data Return Transmitted Data
Ethernet 10BASE-T Connector
connected Received Data Return connected connected
RJ45
Table Ethernet Connector Assignments
Name Description Transmitted Data Transmitted Data Return Received Data Connected Connected Received Data Return Connected Connected
3-12
Board Design Layout
3.2.7 EJTAG Connectors
BDMR4102 EJTAG connectors used debug board. connectors locations This section provides overview EJTAG functions describes EJTAG connectors. 3.2.7.1 Overview EJTAG Functions EJTAG on-chip debug solution from MIPS licensees/partners. EJTAG provides nonintrusive leading-edge debug tool Logic MiniRISC TinyRISC microprocessors workstation environments. EJTAG intended establish debug standard among MIPS partners simplify development systems based MIPS microprocessors. EJTAG allows debug user code MIPS16 (application specific extension) MIPS I/II/III (instruction architecture). revision EJTAG specification implemented Logic EJTAG Revision 1.5.3. EJTAG functions associated with BDMR4102 evaluation board implemented hardware. These functions include:
EJTAG interface memory Software breakpoints Single stepping support Instruction, data, processor breakpoints trace Profiling
3.2.7.2 EJTAG Connector (J4) 16-pin EJTAG connector (J4) allows subset EJTAG functions, including downloading data programs memory control. connector does support trace. Figure shows numbers this EJTAG connector Table lists assignments.
External Interfaces
3-13
Figure
EJTAG Connector
Table EJTAG Connector Assignment
Signal Name Input/Output Description (test data output) performs different functions, depending whether trace mode turned Connector does support trace, functions this signal same those when trace mode turned off. That serial output data shifted from JTAG instruction data register (TDO) falling edge test clock, TCK. When data shifted out, this three-state (high impedance) condition. connected. (test data input)/DINT(debug interrupt) also performs functions with respect state trace mode. trace mode off: Serial input data (TDI, test data input) shifted into JTAG Instruction register Data register rising edge clock, depending (test access port) controller state. trace mode active-low level this (DINT, debug interrupt) used interrupt switch trace mode. This signal sampled positive edge asynchronous TCK. TRST TRST (test reset) active-low, asynchronous, reset signal that resets EJTAG module independently processor logic. power. (test clock) input clock used shift data into instruction register data register. (test mode select) decoded controller control test operation. signal sampled rising edge TCK.
TDI/DINT
3-14
Board Design Layout
Table EJTAG Connector Assignment (Cont.)
EJTAG_RESET Signal Name Input/Output Description Ground This signal board level reset signal.
3.2.7.3 EJTAG Connector (J5) 52-pin EJTAG connector (J5) supports same EJTAG functions connector addition, supports trace. Figure shows numbers connector Table lists assignments. Figure EJTAG Connector
Table
EJTAG Connector Assignments
Signal Name TRST Input/Output Description TRST (test reset) active-low, asynchronous, reset signal that resets EJTAG module independently processor logic. trace mode off: Serial input data (TDI, test data input) shifted into JTAG Instruction register Data register rising edge clock, depending (test access port) controller state. trace mode active-LOW level this (DINT, debug interrupt) used interrupt switch trace mode. This signal sampled positive edge asynchronous TCK.
TDI/DINT
External Interfaces
3-15
Table
EJTAG Connector Assignments (Cont.)
Signal Name TDO/TPC Input/Output Description trace mode off: Serial output data (TDO) shifted from JTAG instruction data register this falling edge test clock, TCK. When data shifted out, this 3-state (off) condition. trace mode This provides nonsequential program counter (TPC) each DCLK clock.
(test mode select) decoded controller control test operation. signal sampled rising edge TCK. (test clock) input clock used shift data into instruction register data register. This signal board level reset signal. During trace mode, status encoded every cycle, using this group three status bits. PCST1_[2:0] contain most recent status bits. status trace status trace status trace
EJTAG_RESE PCST1_[2:0]
PCST1_ PCST1_1 PCST1_2 DCLK
trace clock output. This clock qualifies address status information contained PCST pins. trace This provides nonsequential program counter (TPC) each DCLK when (where number address bits output each DCLK) greater than one. During trace mode, status encoded every cycle, using this group three status bits. When DCLK processor clock) greater than PCST2_[2:0] contain second most recent status bits. status trace status trace status trace
TPC2
PCST2_[2:0]
PCST2_ PCST2_1 PCST2_2
3-16
Board Design Layout
Table
EJTAG Connector Assignments (Cont.)
Signal Name TPC3 Input/Output Description trace This provides nonsequential program counter (TPC) each DCLK, when (where number address bits output each DCLK) greater than During trace mode, status encoded every cycle using this group three status bits. When DCLK processor clock) greater than PCST3_[2:0] contain third most recent status bits. status trace status trace status trace trace This provides nonsequential program counter (TPC) each DCLK, when (where number address bits output each DCLK) greater than During trace mode, status encoded every cycle using this group three status bits. When DCLK processor clock) equals PCST4_[2:0] contain fourth most recent status bits. status trace status trace status trace trace This provides nonsequential program counter (TPC) each DCLK, when (where number address bits output each DCLK) equals trace This provides nonsequential program counter (TPC) each DCLK, when (where number address bits output each DCLK) equals trace This provides nonsequential program counter (TPC) each DCLK, when (where number address bits output each DCLK) equals
PCST3_[2:0]
PCST3_ PCST3_1 PCST3_2 TPC4
PCST4_[2:0]
PCST4_ PCST4_1 PCST4_2 TPC5
TPC6
TPC7
External Interfaces
3-17
Table
EJTAG Connector Assignments (Cont.)
Signal Name TPC8 Input/Output Description trace This provides nonsequential program counter (TPC) each DCLK, when (where number address bits output each DCLK) equals
following pins ground:
3.2.8 Programming Connector (J11)
8-pin connector (J11) allows program (U42). Figure 3.10 shows numbers this connector Table 3.10 lists assignments. Figure 3.10 Programming Connector
Edge Board
3-18
Board Design Layout
Table 3.10
Pins
Programming Connector Assignments
Signal Name ISP_EN Connected ISP_MODE Ground ISP_SCLK Description Power Input Serial Data Serial Data Program Enable In-System Programmable Mode Ground Program Clock Input
3.2.9 Power Supply Connector (J1)
BDMR4102 Evaluation Board standard power supply connector (Figure 3.11), location Figure 3.11 Power Supply Connector
Ground
Logic supplies switching adapter with standard power inlet that lets connect board power. adapter takes inputs from 100-240 50-60 outputs amps. (D5) comes when power applied board.
External Interfaces
3-19
Indicators
This section describes following indicators BDMR4102 board:
Power Ethernet LEDs Debug 7-segment display
Figure 3.12 shows positions these indicators board. Figure 3.12 Indicator Positions
Ethernet LEDs (D1-D4)
Yellow Debug (D6)
7-Segment Display (U35) Power (D5)
3.3.1 Power
power (D5) comes when power applied board, stays long power being applied.
3-20
Board Design Layout
3.3.2 Ethernet LEDs
There four LEDs edge evaluation board, left Ethernet connector, shown Figure 3.13. These indicators come during Ethernet activity. Table 3.11 summarizes Ethernet indicator functions Figure 3.13 Ethernet Indicator Positions
Ethernet Indicators Ethernet 10BASE-T Connector Edge Evaluation Board
Green
Green
Yellow
Table 3.11 Ethernet Indicator Functions
Indicator Location Function Activated indicate data being transmitted. Activated indicate data being received. Activated when Ethernet link integrity good. Activated when collision occurs; that when Ethernet devices trying transmit same time. (This default function this LED2 output from AM79C970. Ethernet controller initialization code should enable this function.)
3.3.3 Debug
yellow (D6) indicates board debug mode. lights when debug register EZ4102 set. part EJTAG debugging system. Refer Section 3.2.7.1, "Overview EJTAG Functions," page 3-13.
Indicators
3-21
3.3.4 7-Segment Display
7-segment display (U35) shown Figure 3.14 attached memory-mapped latch (register), location U34. read operation register returns current value stored register displayed segment display. write operation register changes value shown segment display. Table 3.12 lists data assignments each segment. When related `0,' segment turns when related `1,' segment turns off. 7-segment display address 0x1E00 0020 system memory must accessed with byte operations. Figure 3.14 7-Segment Display
Example
decimal
(D0)
(D5) (D6)
(D1)
(D4)
(D2) (D7) Decimal Point
Decimal Point
(D3)
Segment Segment
Table 3.12
Data
7-Segment Display Settings
Segment Decimal point
3-22
Board Design Layout
System Memory
BDMR4102 Evaluation Board accommodates variety memory devices, including SDRAM DIMM, SRAM (static RAM), boot PROM. This section describes different memory types usage. Figure page shows position different memory modules board.
3.4.1 Synchronous DRAM Dual Inline Memory Module (SDRAM DIMM)
BDMR4102 Evaluation Board uses Mbyte SDRAM DIMM installed DIMM socket main system memory. software Logic provides initializes (FbusMACRO) address SDRAM DIMM memory location 0x0000 0000. provides glueless interface SDRAM DIMM. LR4102 microprocessor supports other SDRAM DIMM configurations, well DRAM. DRAM other than Mbyte SDRAM DIMM, must modify configuration code. external master needs access SDRAM, SDRAM clock must MHz. SDRAM accesses also occur this case.
3.4.2 Static (SRAM)
evaluation board also contains Kbytes SRAM. software Logic provides initializes address SRAM memory location 0x0E00 0000. Ethernet controller uses SRAM devices hold transmit receive buffers. This memory used external interface store temporary values without constraining SDRAM clock MHz. also SRAM store programs data.
3.4.3 Boot EPROMs
BDMR4102 board shipped with AM29F080, Mbyte, Flash EPROM installed location U12. board also contains socket, location U25, which optional 32-pin EPROM installed. socket accommodates EPROMs Mbyte, EPROM installed this socket sits over Flash EPROM location U12.
System Memory
3-23
boot EPROMs addressed MIPS boot vector address, which 0x1FC0 0000. order which boot EPROMs addressed decides which EPROM acts boot EPROM. This determined jumper JP9. installed, AM29F080 selected boot device. installed, EPROM selected boot device. maps addresses EPROMs select boot alternate device. Installing jumper inverts address (A19), most significant address bit, boot EPROM. This allows install boot programs same Mbyte boot EPROM. Each boot program must less than Kbytes. addressing nonboot EPROM affected jumper JP8. Table 3.13 lists boot EPROM addresses with installed installed.
Table 3.13
Boot EPROM Addressing
Boot EPROM Address with Installed 0x80000 0x00000 Boot EPROM Address with Installed 0x00000 0x80000
LR4102 Address 0x1FC0 0000 0x1FC0 8000
Memory
Table 3.14 shows BDMR4102's memory map. Note that LR4102 microprocessor contains programmable memory controller, known FBusMACRO, that address mappings shown Table 3.14 altered software. However, addresses shown Table 3.14 those that Logic uses software delivered with BDMR4102 Evaluation Board. memory peripheral devices BDMR4102 board accessed either user kernel mode. user mode, addresses programs (virtual addresses) must kuseg, that range 0x0000 0000 0x7FFF FFFF. Kernel-mode programs typically virtual addresses kseg0 (0x8000 0000 0x9FFF FFFF) cacheable locations, kseg1 (0xA000 0000 0xBFFF FFFF) noncacheable locations.
3-24
Board Design Layout
Some device selects partially decoded chip, using general purpose chip select, gp[5:0], address offset. These selects noted gpx+offset. This method decoding chip selects used leave some gp[x] selects free expansion.
Table 3.14
Physical Memory
Controlling Chip Select FAPI
Address Range 0x1FE0 0020 0x1FE0 0000 0x1FD0 0000 0x1FDF FFFF 0x1FC0 0000 0x1FCF FFFF
Device Name AM79C970A Ethernet Controller
0x10 0000
Mbyte EPROM (U25) Flash EPROM (U12) (EPROM type depends setting jumper JP9) Mbyte EPROM (U25) Flash EPROM (U12) (EPROM type depends setting jumper JP9) Unused
0x1E00 003F 0x1E00 0030 0x1E00 002F 0x1E00 0020 0x1E00 001F 0x1E00 0000
0x30
Interrupt Clear
0x20
7-Segment Display
16550 UART
Unused 0x0E01 FFFF 0x0E00 0000 Kbyte SRAM
Unused 0x00FF FFFF 0x0000 0000 Mbyte SDRAM
Memory
3-25
Two-Wire Serial Peripheral Devices
BDMR4102 board contains three peripheral devices that standard two-wire serial bus. They
real-time clock (U37) Kbyte EEPROM (U13) serial presence detect (SPD), which DRAM DIMM
LR4102 microprocessor does contain dedicated two-wire serial support hardware, instead communicates with two-wire serial peripheral devices using general purpose pins, gpIO[1:0], which driven software. This section describes each peripheral devices. supported devices bidirectional two-wire data transmission protocol. Devices sending data onto described transmitters devices receiving data receivers. device that controls message master devices controlled master slaves. slave devices must controlled master device that generates serial clock (SCL), controls access, generates start stop conditions.
3.6.1 Real-Time Clock (RTC)
BDMR4102 board equipped with DALLAS Semiconductor 1307 real-time clock U37. This provides battery-backed clock date function evaluation board. also program supply periodic interrupt LR4102. falling edge (Square Wave) output from used latch (programmable logic device), which then asserts interrupt (int5) LR4102 microprocessor. interrupt cleared writing location 0x30 (0x1E00 0030).
3-26
Board Design Layout
Table 3.15 shows address space RTC. Table 3.15
Device 1101
Real-Time Clock Addressing
Address 0b000 Read/Write Read Write
Table 3.16 shows registers. Table 3.16
Register Name
Registers
Register Bits
Address Seconds Minutes Hour Hour
Range
Seconds 0x00 Minutes Hours 0x01 0x02
Seconds Minutes 12/24 10/AM
00-59 00-59 01-12 AM/PM 00-23
Date
0x03 0x04
Date
Date
01-28/29 01-30 01-31 01-12
Month
0x05
Month
Month
Year Control
0x06 0x07 0x08- 0x3F
Year OUT2
Year SQWE3
00-99
8-bit registers
Clock Halt. When HIGH, oscillator disabled. When LOW, oscillator enabled. Output control. This controls output level SQW/OUT when oscillator disabled. SQWE LOW, level SQW/OUT HIGH HIGH LOW. Square Wave Enable. When HIGH, enables oscillator output. Frequency controlled Rate Select bits Control register (RS[1:0]). Available frequencies (RS[1:0] 00), 4.096 (RS[1:0] 01), 8.192 (RS[1:0] 10), 32.768 (RS[1:0] 11).
Two-Wire Serial Peripheral Devices
3-27
detailed information about RTC, refer DALLAS Semiconductor datasheet DS1307/DS1308 Serial Real Time Clock.
3.6.2 EEPROM
BDMR4102 Evaluation Board equipped with NM24C08 Kbyte EEPROM that provides nonvolatile storage board identification configuration information. Table 3.17 shows address EEPROM.
Table 3.17
Device 1010
EEPROM Addressing
Address 0b1xx Read/Write Read Write
3.6.3 Serial Presence Detect (SPD)
100-pin DIMM installed DIMM socket (J3) equipped with EEPROM. EEPROM contains information about types configuration memory devices installed DIMM. information EEPROM configure BDMR4102 board operate with different types DIMMs. Table 3.18 shows address EEPROM.
Table 3.18
Device 1010
EEPROM Addressing
Address 0b000 Read/Write Read Write
3-28
Board Design Layout
3.6.4 LR4102 Interrupts
Table 3.19 shows interrupts from evaluation board connected LR4102 microprocessor. Table 3.19
Interrupt Number
BDMR4102 Interrupts
Source LR4102 DBE/FBDSTOP
Cleared Writing SCR1 FBDSTOP SCR2 LR4102. Writing Timer Writing Clearing source UART writing Timer Clearing source Ethernet Controller Writing 0x30 (0x1E000030)
LR4102 Timer SerialICE-1 16550 UART LR4102 Timer Ethernet Controller
Real-Time Clock
Device Registers
This section describes BDMR4102 Evaluation Board devices that have registers. They are:
PC16550D UART (U24) Am79C970A Ethernet Controller (U19)
real-time clock (U37) also registers, which described Table 3.16, page 3-27.
Device Registers
3-29
3.7.1 PC16550D UART Registers
Table 3.20 lists registers National Semiconductor UART location U24. detailed information about UART, refer PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet from National Semiconductor Corporation.
Table 3.20
UART Registers
Address Register Name Receiver Buffer Register Transmitter Holding Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register Divisor Latch Register (LS) Divisor Latch Register (MS) Access1
0x1E00 0000 0x1E00 0000 0x1E00 0001 0x1E00 0002 0x1E00 0002 0x1E00 0003 0x1E00 0004 0x1E00 0005 0x1E00 0006 0x1E00 0007 0x1E00 0000 0x1E00 0001
Read Only, Read/Write, Write Only
3-30
Board Design Layout
3.7.2 Am79C970A Ethernet Controller
Table 3.21 describes user registers Am79C970A Ethernet Controller. configuration registers accessed with configuration cycles. Am79C970A Ethernet Controller responds configuration cycle with Table 3.21 Ethernet Controller User Registers
Access1 Register Name
Address A[31:0] Configuration Registers 0x1FE9 0000 0x1FE9 0002 0x1FE9 0004 0x1FE9 0006 0x1FE9 0008 0x1FE9 0009 0x1FE9 000A 0x1FE9 000B 0x1FE9 000C 0x1FE9 000E 0x1FE9 0010 0x1FE9 0014 0x1FE9 0030 0x1FE9 003C 0x1FE9 003D 0x1FE9 003E 0x1FE9 003F
Vendor Device Command Status Revision Programming Interface Subclass Base-Class Latency Timer Header Type Base Address Memory Mapped Base Address Expansion Base Address Interrupt Line Interrupt MIN_GNT MAX_LAT
Device Registers
3-31
Table 3.21
Ethernet Controller User Registers (Cont.)
Access1 Register Name
Address A[31:0] Registers2 0x1FE0 0010 0x1FE0 0014 0x1FE0 0018 0x1FE0 001C
Register Data Port Register Address Port Reset Data Port
Read Only, Read/Write should memory access from (FBusMACRO) access registers. device addresses determined values programmed configuration registers.
Refer AM79C970A PCnet-PCI Single-Chip Full Duplex Ethernet Control Local Product datasheet from Advanced Micro Devices Inc., more information about Ethernet Controller registers.
3-32
Board Design Layout
Chapter Equations
This chapter provides code listing Programmable Array Logic (PAL) location BDMR4102 Evaluation Board. numbers equations refer pins package shipped BDMR4102 Evaluation Board. performs following tasks:
Decodes controls external addresses devices Both EPROMs evaluation board (the EPROM Flash EPROM U12) connect chip select selected signal A20. Jumper selects boot device addressing order each EPROM. Additionally, jumper sets which boot program (regular alternate) selected EPROM uses. installed, inverted alternate boot program selected. setting does affect nonboot ROM. Refer Section 2.2, "Jumper Settings," more information.
Decodes external addresses devices connected chip select Devices connected include UART, seven-segment display, real-time clock interrupt register. address offset required these devices. Refer Section 3.5, "Memory Map," each device's offset value.
Combines reset signals gathers reset signals from other sources combines them into single board-level reset request.
TinyRISC® BDMR4102 Evaluation Board User's Guide
Sets interrupts from sets latch using falling edge RTC's square ware output. latch used interrupt LR4102. Write latch clear
Arbitrates allows multiple masters connect LR4102. only connect master LR4102.
code this chapter date time publication. verify that have latest code, should contact Logic Corporation.
Equations
module core_logic title 'lr4102 core logic' device 'ispLSI'; PROPERTY 'PART ispLSI2032v-100LT44';
PLSI
"define pins nodes
pbclk jmp0 jmp1 addr20 addr19 addr05 addr04 resetn flash_sel dip_sel rom_a19 bd_sel uart_sel read_display write_display
"CLK"
"used select between eprom/flash" "invert allow boot "programs rom" "used select between uart/display" "used select between rtc_int/display" "uart/display select" "eprom/flash select"
"buffered data select"
"7-seg display "7-seg display
"***
Arbiter signals
***"
enet_req enet_gnt exp_req exp_gnt
istype 'reg_D'; istype 'reg_D'; istype 'reg_D';"system req" "system gnt"
sqw_out intp5 arb0 arb1 arb2 si_reset ejtag_reset pb_reset rtc_sync1 rtc_sync2 rtc_sync3 rtc_intff
node node node
"square wave from "interrupt
istype 'buffer, reg_D'; istype 'buffer, reg_D'; istype 'buffer, reg_D';
node node node node istype istype istype istype 'reg_D'; 'reg_D'; 'reg_D'; 'reg_SR';
Equations
PLSI
PROPERTY 'OPENDRAIN
pb_reset';
"constants state definitions
h,l,x,ck,z 1,0,.X.,.C.,.Z.; ARBITER [arb2,arb1,arb0]; [0,0,0]; [0,0,1]; [1,0,0]; [1,0,1]; [0,1,0]; [0,1,1];
IDLE_ENET IDLE_EXP REQ_ENET REQ_EXP GNT_ENET GNT_EXP RESET
!resetn;
equations ARBITER.clk pbclk; req.clk pbclk; enet_gnt.clk= pbclk; exp_gnt.clk= pbclk; rtc_sync1.clk= pbclk; rtc_sync2.clk= pbclk; rtc_sync3.clk= pbclk; rtc_intff.clk= pbclk;
!flash_sel !gp0 !addr20 (!jp9 addr20)); !dip_sel rom_a19 !bd_sel !gp0 addr20 (!jp9 !addr20)); ((jp8 addr20) addr19) ((!jp8 !addr20) !addr19); !gp0 !gp4);
!uart_sel (!gp4 !addr05); !read_display (!gp4 addr05 !addr04 !rdn !write_display (!gp4 addr05 !addr04 !we0) (RESET);
!pb_reset !si_reset !ejtag_reset; pb_reset.en !si_reset !ejtag_reset; rtc_sync1 sqw_out; rtc_sync2 rtc_sync1; rtc_sync3 rtc_sync2; rtc_intff.s !rtc_sync2 rtc_sync3);"set falling edge rtc_intff.r !gp4 addr05 addr04 (RESET); intp5 rtc_intff; STATE_DIAGRAM ARBITER state IDLE_ENET: (!enet_req) then REQ_ENET with enet_gnt :=1; exp_gnt :=1; endwith; else (!exp_req) then REQ_EXP with enet_gnt :=1; exp_gnt :=1; endwith; else IDLE_ENET with enet_gnt :=1; exp_gnt :=1; endwith; state IDLE_EXP: (!exp_req) then REQ_EXP with enet_gnt :=1; exp_gnt :=1; endwith; else (!enet_req) then REQ_ENET with enet_gnt :=1; exp_gnt :=1; endwith;
Equations
else IDLE_EXP with enet_gnt :=1; exp_gnt :=1; endwith; state REQ_ENET: !gnt !enet_req) then GNT_ENET with enet_gnt :=0; exp_gnt :=1; endwith; else !enet_req )then REQ_ENET with enet_gnt :=1; exp_gnt :=1; endwith; else IDLE_EXP with enet_gnt :=1; exp_gnt :=1; endwith; state REQ_EXP: !gnt !exp_req) then GNT_EXP with enet_gnt :=1; exp_gnt :=0; endwith; else !exp_req )then REQ_ENET with enet_gnt :=1; exp_gnt :=1; endwith; else IDLE_ENET with enet_gnt :=1; exp_gnt :=1; endwith;
else !exp_req )then REQ_ENET with enet_gnt :=1; exp_gnt :=1; endwith; else IDLE_ENET with enet_gnt :=1; exp_gnt :=1; endwith;
state GNT_ENET: (!gnt !enet_req) then GNT_ENET with enet_gnt :=0; exp_gnt :=1; endwith; else IDLE_EXP with enet_gnt :=1; exp_gnt :=1; endwith; state GNT_EXP: (!gnt !exp_req) then GNT_EXP with enet_gnt :=1; exp_gnt :=0; endwith; else IDLE_EXP with enet_gnt :=1; exp_gnt :=1; endwith;
Equations
Chapter Schematics
This section contains following schematics BDMR4102 Evaluation Board:
Microprocessor Clock Circuitry, Figure ROMs, SRAMs, Address Latches, Figure Ethernet DRAM Circuitry, Figure Miscellaneous Circuitry Connectors, Figure Expansion Connector Boot Device Selection Circuitry, Figure Power Reset Circuitry, Figure EJTAG Connectors, Figure
section also provides brief functional descriptions components. Designations parentheses (J9, refer location components board.
TinyRISC® BDMR4102 Evaluation Board User's Guide
Microprocessor Clock Circuitry
microprocessor clock circuitry shown Figure performs following functions:
LR4102 microprocessor (U1) provides full-speed evaluation target. crystal (X1) provides main clock LR4102 microprocessor. oscillator (U5) provides alternate clock microprocessor. This clock used when LR4102 core operating when input frequency other than desired. Jumpers JP1-6, JP14 control various LR4102 functions. Refer Section 2.2, "Jumper Settings" further information about these jumpers.
Schematics
NC7SZ08
SOCKET
25MHZ
CPU_VDDCORE
EXTAL XTAL IRDYN TRDYN STOPN DEVSELN REQN GNTN SDONEP CBEN0 CBEN1 CBEN2 DIVC0 CBEN3 DIVA1 FALEP DIVA0 CWAITP BIG_ENDIANP IDDTN GPIO3 GPIO2 GPIO1 GPIO0 GPRDN GPWEN3 JTAGALSOP GPWEN1 GPWEN0 RESETN TDI_DINT RESET_OUTN TDO_TPC TRST JTAG_TDO FADDRP28 FADDRP27 FADDRP26 DCLK TPC8 TPC7 TPC6 TPC5 TPC4 TPC3 TPC2 PCST4[2] PCST4[1] PCST4[0] PCST3[2] PCST3[1] PCST3[0] PCST2[2] PCST2[1] PCST2[0] PCST1[2] PCST1[1] PCST1[0] DEBUGMP FADDRP25 FADDRP24 FADDRP23 FADDRP22 FADDRP21 FADDRP20 FADDRP19 FADDRP18 FADDRP17 FADDRP16 FADDRP15 FADDRP14 FADDRP13 FADDRP12 FADDRP11 FADDRP10 FADDRP09 FADDRP08 FADDRP07 FADDRP06 FADDRP05 FADDRP04 FADDRP03 FADDRP02 FADDRP01 FADDRP00 ICECLKP ICERXP ICETXP FADP31 FADP30 FADP29 FADP28 FADP27 PENABLEN FADP26 PITRST FADP25 PITCK FADP24 PITMS FADP23 PITDI_DINT FADP22 PITDO_TPC FADP21 PIRST FADP20 PIBREAK FADP19 PTDCLK PTTRIGIN PTTRIGOUT PPNINIT FADP15 PPDATA8 FADP14 PPDATA7 FADP13 PPDATA6 FADP12 PPDATA5 FADP11 PPDATA4 FADP10 PPDATA3 FADP09 PPDATA2 FADP08 PPDATA1 FADP07 PPNSTROBE FADP06 PPBUSY PPNACK PPNSELECTIN PPSELECT PPNAUTOFD FADP18 FADP17 FADP16 FADDRP28 FADDRP27 FADDRP26 FADDRP25 FADDRP24 FADDRP23 FADDRP22 FADDRP21 FADDRP20 FADDRP19 FADDRP18 FADDRP17 FADDRP16 FADDRP15 FADDRP14 FADDRP13 FADDRP12 FADDRP11 FADDRP10 FADDRP09 FADDRP08 FADDRP07 FADDRP06 FADDRP05 FADDRP04 FADDRP03 FADDRP02 FADDRP01 FADDRP00 GPWEN2 CSHTSTP SCAN_RAMWEP SCAN_MODEP SCAN_INP SCAN_ENABLEP PMON_OUTP SCAN_OUTP PLLVDD1 PLLVSS1 PLLVDD2 PLLVSS2 PLLEN PLLENARS SEL_CKOUT1N SELECT_PLLN DIVC1 FRAMEN PBCLKP SDWEN SDRASN SDCLKP SDCASN\SDOEN
20PF
1.5K
CPU_VDDIO
Microprocessor Clock Circuitry
FADDRP[31:00]
FADP[31:00]
ICECLKP,ICERXP,ICETXP
SIZE
INTP[5:0],T[1:0]_OUTN
4.7K
TDI/DINT* TDO/TPC TRST*
DCLK TPC8 TPC7 TPC6 TPC5 TPC4 TPC3 TPC2 PCST4_2 PCST4_1 PCST4_0 PCST3_2 PCST3_1 PCST3_0 PCST2_2 PCST2_1 PCST2_0 PCST1_2 PCST1_1 PCST1_0 DEBUGMP
INTERFACE
SERIAL
ICECLKP ICERXP ICETXP
PITRST PITCK PITMS PITDI_DINT PITDO_TPC PIRST PIBREAK PTDCLK PTTRIGIN PTTRIGOUT
PPNFAULT PPERROR
PAGE
Microprocessor Clock Circuitry
CLOCKS
SDCLK0
Figure
SDCLK SDCSN0 SDCSN1 SDCASN SDDMP0 SDDMP1 SDDMP2 SDDMP3 SDWEN SDRASN
20PF
CPU_VDDCORE
JP14
SDDMP3\SDCASN3
DRAM
SDDMP2\SDCASN2
SDDMP1\SDCASN1
SDDMP0\SDCASN0
SDCSN1\SDRASN1
SDCSN0\SDRASN0
0.47UF
PBCLK FRAMEN IRDYN TRDYN STOPN DEVSELN REQN GNTN SDONEP CBEN0 CBEN1 CBEN2 CBEN3 FALEP
MISC
CONTROL
CWAITP GPIO3 GPIO2 GPIO1 GPIO0 GPRDN GPWEN3 GPWEN2 GPWEN1 GPWEN0 3V_RESETN RSTOUTN
EJTAG
ADDRESS
MEMORY
LR4102
ENG. TITLE DATE PROJECT
INT/TIMER
JOHN
FADP05 FADP04 FADP03 FADP02
12/08/98
T0_OUTN
T1_OUTN
INT5
INT4
INT3
INT2
INT1
INT0
KALDUNSKI
FADP01 FADP00
FADP31 FADP30 FADP29 FADP28 FADP27 FADP26 FADP25 FADP24 FADP23 FADP22 FADP21 FADP20 FADP19 FADP18 FADP17 FADP16 FADP15 FADP14 FADP13 FADP12 FADP11 FADP10 FADP09 FADP08 FADP07 FADP06 FADP05 FADP04 FADP03 FADP02 FADP01 FADP00
T0_OUTN
T1_OUTN
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5
ROMs, SRAMs, Address Latches
ROMSs, SRAMs address buffers shown Figure perform following functions:
Four Kbytes SRAM devices (U26, U27, U28, U29) provide BDMR4102 board with Kbytes SRAM, organized Kbytes bits memory. Mbyte Flash EPROM (U12) used boot device board. This device shipped with board. Jumper determines whether this device EPROM location boot device. When installed, boot PROM. store boot programs this EPROM, provided that neither program larger than Kbytes. Jumper selects between programs installed. Refer Section 2.2.7, "Boot Device Selection (JP9)," more information about JP9, Section 2.2.6, "Alternate Boot Program Selection (JP8)," more information about JP8. Refer Section 3.4.3, "Boot EPROMs," more information this subject.
socket (U25) houses optional Mbyte EPROM. When installed, EPROM sits over Flash EPROM (U12). alternate boot device board installing jumper JP9. store boot programs this EPROM, provided that neither program larger than Kbytes. Jumper selects between programs installed. cross references previous paragraph would like more information about jumpers boot PROM.
SN74LCX16244 buffer (U22) buffers lower order address bits FADDRP[11:0] devices except DRAM DIMM. This buffering provided reduce loading trace length these high-speed signals. LCX245 buffer (U30) buffers data from EPROMs, 7-segment display, UART. This buffering provided reduce loading trace length these high-speed signals.
Schematics
Figure
ROMs, SRAMs, Address Latches
FADDRP[28:00] BADDRP[15:00]
ROM_A19
1Mx8 ROM_A19 FADDRP18 FADDRP17 FADDRP16 FADDRP15 FADDRP14 FADDRP13 FADDRP12 BADDRP11 BADDRP10 BADDRP09 BADDRP08 BADDRP07 BADDRP06 BADDRP05 BADDRP04 BADDRP03 BADDRP02 BADDRP01 BADDRP00
Flash
RY/BY
SN74LCX16244
29F080
SRAM
RESET
GPWEN0 GPRDN
B_WEN0 B_RDN
B_RDN B_WEN0
RESETN
GPWEN3 GPRDN
GPWEN1 GPRDN
SRAM
FADDRP00 FADDRP01 FADDRP02 FADDRP03 FADDRP04 FADDRP05 FADDRP06 FADDRP07 FADDRP08 FADDRP09 FADDRP10 FADDRP11
BADDRP00 BADDRP01 BADDRP02 BADDRP03 BADDRP04 BADDRP05 BADDRP06 BADDRP07 BADDRP08 BADDRP09 BADDRP10 BADDRP11
TSOP
BDATA7 BDATA6 BDATA5 BDATA4 BDATA3 BDATA2 BDATA1 BDATA0
FADDRP16 FADDRP15 FADDRP14 FADDRP13 FADDRP12 BADDRP11 BADDRP10 BADDRP09 BADDRP08 BADDRP07 BADDRP06 BADDRP05 BADDRP04 BADDRP03 BADDRP02
FADP31 FADP30 FADP29
FADP28 FADP27 FADP26 FADP25
FADP24
FADDRP16 FADDRP15 FADDRP14 FADDRP13 FADDRP12 BADDRP11 BADDRP10 BADDRP09 BADDRP08 BADDRP07 BADDRP06 BADDRP05 BADDRP04 BADDRP03 BADDRP02
LCX245
BDATA4 BDATA5 BDATA6 BDATA7
27C080
SRAM
B_RDN
B_RDN
GPWEN2 GPRDN
GPWEN0 GPRDN
BD_SELN
DIP_SELN BDATA[7:0] FADP[31:00]
SRAM
ROMs, SRAMs, Address Latches
32Kx8
32Kx8
FADP15 FADP14 FADP13 FADP12 FADP11 FADP10 FADP09 FADP08
FLASH_SELN
1Mx8 ROM_A19 FADDRP18 FADDRP17 FADDRP16 FADDRP15 FADDRP14 FADDRP13 FADDRP12 BADDRP11 BADDRP10 BADDRP09 BADDRP08 BADDRP07 BADDRP06 BADDRP05 BADDRP04 BADDRP03 BADDRP02 BADDRP01 BADDRP00
EPROM FADDRP16 FADDRP15 FADDRP14 FADDRP13 FADDRP12 BADDRP11 BADDRP10 BADDRP09 BADDRP08 BADDRP07 BADDRP06 BADDRP05 BADDRP04 BADDRP03 BADDRP02
FADP00 FADP01 FADP02 FADP03 FADP04 FADP05 FADP06 FADP07
BDATA0 BDATA1 BDATA2 BDATA3
FADP23 FADP22 FADP21 FADP20 FADP19 FADP18 FADP17 FADP16
BDATA7 BDATA6 BDATA5 BDATA4 BDATA3 BDATA2 BDATA1 BDATA0
FADDRP16 FADDRP15 FADDRP14 FADDRP13 FADDRP12 BADDRP11 BADDRP10 BADDRP09 BADDRP08 BADDRP07 BADDRP06 BADDRP05 BADDRP04 BADDRP03 BADDRP02
32Kx8
32Kx8
FADP07 FADP06 FADP05 FADP04 FADP03 FADP02 FADP01 FADP00
PROJECT
TITLE ENG.
ROMS SRAM
SIZE
JOHN
DATE
KALDUNSKI
PAGE
12/08/98
Ethernet DRAM Circuitry
Ethernet DRAM circuitry shown Figure performs following functions:
Ethernet circuitry: Ethernet transformer (U10), conjunction with Ethernet controller, connects evaluation board Ethernet (local area network). AM79C970A Ethernet Controller (U19). controller, conjunction with transformer, connects evaluation board Ethernet LAN. Refer Section 3.7.2, "Am79C970A Ethernet Controller," more information about controller. RJ45 connector (J7) provides Ethernet hardware connection.
100-pin socket (J3) accommodates standard 100-pin JEDEC DIMM. Mbytes SDRAM DIMM supplied with board. However, socket will also accommodate DRAM. Jumper JP17 used select between SDRAM devices. memory installed socket provides main system memory board. Refer Section 3.2.2, "DIMM Connector (J3)," further information about connector, Section 3.4.1, "Synchronous DRAM Dual Inline Memory Module (SDRAM DIMM)," further information about DIMM. Refer Section 2.2.15, "EDO/SDRAM Selection (JP17)," information about jumper settings.
Schematics
Figure
Ethernet DRAM Circuitry
GPIO1 RSTOUTN ENET_GNTN ENET_REQN INTP4 ENET_LOCK ENET_PAR ENET_PERR ENET_SERR
3.3V
INTA LOCK XTAL1 XTAL2 PERR SERR TXP+
20MHZ
GPIO0
GREEN
GREEN
YELLOW
Ethernet DRAM Circuitry
GPIO[3:0]
61.9 1.21k
FADDRP[28:00]
DIMM
CKE1
RJ45
FADDRP28
JP17
FADDRP27 FADDRP11 FADDRP10 FADDRP09 FADDRP08 FADDRP07 FADDRP06 FADDRP05 FADDRP04 FADDRP03 FADDRP02 FADDRP01 FADDRP00
BA0/A11-EDO CKE0 A11-SDR RAS# CAS# OE0# RAS3#/CS3# RAS1#/CS1# RAS2#/CS2# RAS0#/CS0#
SDCLK0 SDWEN SDRASN SDCASN
PBCLK FRAMEN IRDYN DEVSELN TRDYN STOPN CBEN3 CBEN2 CBEN1 CBEN0 FADP16 FADP31 FADP30 FADP29 FADP28 FADP27 FADP26 FADP25 FADP24 FADP23 FADP22 FADP21 FADP20 FADP19 FADP18 FADP17 FADP16 FADP15 FADP14 FADP13 FADP12 FADP11 FADP10 FADP09 FADP08 FADP07 FADP06 FADP05 FADP04 FADP03 FADP02 FADP01 FADP00
FRAME IRDY DEVSEL TRDY STOP C/BE3 C/BE2 C/BE1 C/BE0 IDSEL AD31
TXD+
TDRD+ RDNC3
TXDTXP-
61.9
RXD+
49.9 49.9
RXD-
0.01UF
PULSE PE-68025
CX58
SDCSN1
AD30 AD29 SLEEP AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00 LNKST AVDD1 AVDD2 AVDD3 AVDD4 LED1 LED2 LED3 AVSS1 AVSS2 VSSB1 VSSB2 VSSB3 VSSB4 VSSB5 VSSB6 VSSB7 VSSB8 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VDDB1 VDDB2 VDDB3 VDDB4 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6
SDCSN0 SDDMP3 SDDMP2 SDDMP1 SDDMP0
CAS3#/DQMB3 CAS2#/DQMB2 CAS1#/DQMB1 CAS0#/DQMB0
3.3V
FADP15 FADP14 FADP13 FADP12 FADP11 FADP10 FADP09 FADP08 FADP07 FADP06 FADP05 FADP04 FADP03 FADP02 FADP01 FADP00
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ09 DQ08 DQ07 DQ06 DQ05 DQ04 DQ03 DQ02 DQ01 DQ00
DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16
FADP31 FADP30 FADP29 FADP28 FADP27 FADP26 FADP25 FADP24 FADP23 FADP22 FADP21 FADP20 FADP19 FADP18 FADP17 FADP16
PCnet AM79C970A
CX60
0.1UF
22UF
Ethernet Status
3.3V
PROJECT
TITLE
DRAM/ETHERNET
SIZE
FADP[31:00]
ENG.
JOHN
DATE
KALDUNSKI
PAGE
12-8-1998_11:25
12/08/98
Miscellaneous Circuitry Connectors
Figure shows following miscellaneous circuitry connectors:
Lattice ISPLSI2032 (U42) (programmable logic device). DS1307 real-time clock (U37). Refer Section 3.6.1, "Real-Time Clock (RTC)," further information. NM24C08 Kbyte EEPROM (U13). Refer Section 3.6.2, "EEPROM," further information. 7-segment display (U35) associated data buffer (U34). Refer Section 3.3.4, "7-Segment Display," further information. PC16550 UART (universal asynchronous receiver transmitter) (U24) performs serial-to-parallel parallel-to-serial data conversions data received transferred from board. additional information about UART, refer National Semiconductor datasheet, PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs. MAX3245 (U14) RS232 transceiver provides signal voltage level translation. SerialICE-1 header (J8) allows debug board using SerialICE-1 inputs. Refer Section 3.2.5, "SerialICE-1 Connector (J8)," further information. RS232 SerialICE-1 port (J9) allows debug board using SerialICE-1 inputs. Refer Section 3.2.4, "RS-232 Serial Connector SerialICE-1 (J9)," further information. RS232 serial port (J10) allows connect serial devices board. Refer Section 3.2.3, "Serial Port Connector (J10)," further information. header (J11) used program (U42). Refer Section 3.2.8, "PAL Programming Connector (J11)," further information. Jumpers (boot program selection), (boot device selection), JP15 (SerialICE-1 input data selection), JP16 (SerialICE-1 clock selection). Refer Section 2.2, "Jumper Settings," further information about these jumpers. 1.8432 oscillator (U6), provides alternate clock source SerialICE-1.
Schematics
Figure
Miscellaneous Circuitry Connectors
BADDRP[15:00] GPIO[3:0]
GPIO0
GPIO1
3V_LITHIUM
BADDRP02 BADDRP01 BADDRP00
SOUT
MAX3245 T1OUT T2OUT R1IN R2IN
T1IN T2IN R1OUT R2OUT
NM24C08
3.3V
Serial Port
Miscellaneous Circuitry Connectors
DS1307 VBAT
SQW/OUT
UART_SELN INTP3 B_WEN0 B_RDN RESETP
INTRPT
R/A_MALE
C2C1+ R4IN R5IN R4OUT
PC16550
0.33UF
OUT1 OUT2
0.047UF
R5OUT C1T3OUT R3IN
32.768KHZ
DDIS RXRDY
JMP1 JMP2
Invert BOOT
FROM
ispLSI2032v LATTICE
PBCLK FADDRP20 FADDRP19 BADDRP04 BADDRP05 B_RDN B_WEN0 RSTOUTN GNTN ENET_REQN EXP_REQN
SQW/OUT UART_SELN ROM_A19 FLASH_SELN DIP_SELN BD_SELN REQN ENET_GNTN EXP_GNTN PB_RESET
BDATA7 BDATA6 BDATA5 BDATA4 BDATA3 BDATA2 BDATA1 BDATA0
TXRDY XOUT BAUDOUT RCLK
Serial
R/A_MALE
T3IN R3OUT
INVALID FORCEON FORCEOFF
0.33UF
1.5K
0.33UF
14.7456MHZ
0.047UF
47PF 20PF JP15
ICERXP
INTP5
SI_RESET EJTAG_RESET
WRITE_DISPN
READ_DISPN
JP16
ICECLKP
3.3V
ISPEN
74LCX14
74LCX14
ISP_EN ISP_MODE ISP_SCLK
CX59 0.01UF
74LCX14
CONN_RXP
74LCX14
1.8432MHZ
74FCT543
SI_RESET
3.3V
ICETXP
ICETXP
74LCX14
OEBA
LEAB
BDATA6 BDATA5 BDATA4 BDATA3 BDATA2 BDATA1 BDATA0 BDATA7
LEBA CEBA
OEAB CEAB
BDATA[7:0]
PROJECT
TITLE ENG.
SERIAL JOHN
PORT/SERIAL KALDUNSKI
PAGE
ICE/DISPLAY
SIZE
DATE
12/08/98
Expansion Connector Boot Device Selection Circuitry
circuitry shown Figure performs following functions:
150-pin expansion connector (J2) allows expand design debugging capabilities include external logic. Refer Section 3.2.1, "Expansion Connector (J2)," further information. reset, 74LCX541 (U32) provides boot device chip select number boot device width LR4102. buffer enabled with RSTOUTN.
5-10
Schematics
Figure
Expansion Connector Boot Device Selection Circuitry
FADDRP[28:00] FADP[31:00]
FADP00 FADP01 FADP02 FADP03 FADP04 FADP05 FADP06 FADP07 FADP08 FADP09 FADP10 FADP11 FADP12 FADP13 FADP14 FADP15 SDWEN SDDMP1 SDRASN FADDRP00 FADDRP02 FADDRP04 FADDRP06 FADDRP08 FADDRP10 FADDRP27 SDCLK0 FADP16 FADP17 FADP18 FADP19 FADP20 FADP21 FADP22 FADP23 FADP24 FADP25 FADP26 FADP27 FADP28 FADP29 FADP30 FADP31
150_DIN
FADDRP12 FADDRP13 FADDRP14 FADDRP15 FADDRP16 FADDRP17 FADDRP18 FADDRP19 FADDRP20 FADDRP21 FADDRP22 FADDRP23 FADDRP24 FADDRP25 FADDRP26 SDCASN SDDMP0 SDCSN0 FADDRP01 FADDRP03 FADDRP05 FADDRP07 FADDRP09 FADDRP11 FADDRP28 SDCSN1 SDDMP2 SDDMP3 FRAMEN IRDYN TRDYN STOPN DEVSELN PBCLK CBEN0 CBEN1 CBEN2 CBEN3 SDONEP FALEP EXP_GNTN EXP_REQN
74LCX541
150_DIN 3.3V
BOOTCFG0 BOOTCFG1 BOOTCFG2
CBEN0 CBEN1 CBEN2
Expansion Connector Boot Device Selection Circuitry 5-11
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 T0_OUTN T1_OUTN
RSTOUTN
3.3V
BOOTCFG0 BOOTCFG1 BOOTCFG2
4.7K 4.7K
CWAITP RSTOUTN RESETN
GPWEN0 GPWEN1 GPWEN2 GPWEN3 GPRDN GPIO0 GPIO1 GPIO2 GPIO3
150_DIN
GPIO0 GPIO1 GPIO2 GPIO3 GPWEN0 GPWEN1 GPWEN2 GPWEN3 GPRDN
FRAMEN IRDYN TRDYN STOPN DEVSELN ENET_LOCK ENET_PAR ENET_PERR ENET_SERR ENET_REQN EXP_REQN
SQW/OUT
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5
4.7K
BOOTCFG0 BOOTCFG1 BOOTCFG2
BOOTCFG[2:0] INTP[5:0],T[1:0]_OUTN
GPIO3
PROJECT
JP18
TITLE ENG.
EXPANSION CONNECTOR
SIZE
JOHN
DATE
KALDUNSKI
PAGE
12/08/98
Power Reset Circuitry
power reset circuitry shown Figure performs following functions:
power connector (J1) supplies board with power means switching adapter. Refer Section 3.2.9, "Power Supply Connector (J1)," further information. Power (D5) comes when power applied board, stays while power being applied. MAX708 device (U33) generates reset signal board. voltage regulator (U16) provides core voltage. voltage regulator (U36) provides power supply board. Heatsink provides heatsink regulator U36, provides heatsink regulator U16. Test points TP1, TP2, TP3, TP4, TP5, provide grounding oscilloscope during testing. decoupling capacitors.
5-12
Schematics
Figure
Power Reset Circuitry
HEATSINK
LT1084CT-adj
CPU_VDDCORE
JP12
105_1%
Power Reset Circuitry 5-13
JP13
105_1% 10UF
82.5_1%
0.1UF
22UF 22UF
HEATSINK 3.3V
CPU_VDDIO
MAX708
LT1084CT-3.3
JP10 JP11
RESET
PB_RESET
RESETN
3V_RESETN
0.1UF
22UF
22UF
RESET
RESETP
22UF
22UF
22UF
74CBTD3306
0.1UF
22UF 22UF
0.1UF
POWER
3.3V Generation circuit
74CBTD3306
3.3V
CX62
0.1UF
CX61
0.1UF
CX40
0.1UF
CX41
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
CX12
0.1UF
CX11
0.1UF
CX10
0.1UF
0.1UF
CX37
0.1UF
CX38
0.1UF
CX39
0.1UF
CX49
0.1UF
CX48
0.1UF
CX47
0.1UF
CX46
0.1UF
CX21
0.1UF
CX22
0.1UF
CX23
0.1UF
CX24
0.1UF
CX25
0.1UF
CX26
0.1UF
CX27
0.1UF
CX28
0.1UF
CX43
0.1UF
CX42
0.1UF
CX45
0.1UF
CX44
0.1UF
CPU_VDDIO CPU_VDDCORE
CX18
CX17
0.1UF
CX16
0.1UF
CX15
0.1UF
CX14
0.1UF
CX13
0.1UF
CX36
0.1UF
CX35 CX34 CX33
0.1UF
0.1UF 0.1UF
CX32
0.1UF
CX31
0.1UF
CX30
0.1UF
CX29
0.1UF
CX19
0.1UF
CX20
PROJECT 0.1UF
0.1UF
TITLE ENG.
POWER/RESET
SIZE
JOHN
KALDUNSKI
PAGE
12-8-1998_12:09
DATE
12/08/98
EJTAG Connectors
EJTAG connectors shown Figure performs following functions:
EJTAG connectors debug indicator: EJTAG connector (J4) provides basic EJTAG debugging capabilities, including break control. Refer Section 3.2.7.2, "EJTAG Connector (J4)," additional information. EJTAG connector (J5) provides same EJTAG debugging capabilities addition, supports trace. Refer Section 3.2.7.3, "EJTAG Connector (J5)," further information. EJTAG connector (J6) used only factory testing. yellow (D6) comes when LR4102 debug mode.
Refer Section 3.2.7.1, "Overview EJTAG Functions," additional information about EJTAG functions. detailed EJTAG information, refer EJTAG specification published Philips Semiconductors MIPS licensees.
5-14
Schematics
Figure
EJTAG Connectors
R_BUF_TDO
TRST*
3.3V
TDI/DINT*
3.3V
3.3V
ACTIVE
4.7K
DEBUG
EJTAG Connectors 5-15
EJTAG_RESET
PITRST PITDI_DINT PITMS PITCK PIRST
TDO/TPC
NC7SZ08
TDO/TPC PCST1_0 PCST1_1 PCST1_2 DCLK
R_TDO/TPC R_PCST1_0 R_PCST1_1 R_PCST1_2 R_DCLK
TRST* TDI/DINT* R_TDO/TPC EJTAG_RESET R_PCST1_0 R_PCST1_1 R_PCST1_2 R_DCLK R_TPC2 R_PCST2_0 R_PCST2_1 R_PCST2_2 R_TPC3 R_PCST3_0 R_PCST3_1 R_PCST3_2 R_TPC4 R_PCST4_0 R_PCST4_1 R_PCST4_2 R_TPC5 R_TPC6 R_TPC7 R_TPC8
R_PITRST R_PITDI_DINT PITDO_TPC R_PITMS R_PITCK R_PIRST PIBREAK PTTRIGIN PTTRIGOUT PTDCLK
TPC2 PCST2_0 PCST2_1 PCST2_2 TPC3 PCST3_0 PCST3_1 PCST3_2
R_TPC2 R_PCST2_0 R_PCST2_1 R_PCST2_2 R_TPC3 R_PCST3_0 R_PCST3_1 R_PCST3_2
PITRST PTDCLK
TPC4 PCST4_0 PCST4_1 PCST4_2 TPC5 TPC6 TPC7 TPC8
R_TPC4 R_PCST4_0 R_PCST4_1 R_PCST4_2 R_TPC5 R_TPC6 R_TPC7 R_TPC8
4.7K
3.3V
PITDO_TPC PIBREAK PTTRIGIN PTTRIGOUT
3.3V
TDI/DINT* EJTAG_RESET
YELLOW
PITDI_DINT PITMS PITCK PIRST
DEBUGMP
74LCX14
TRST*
JMP1 JMP2
PROJECT
TITLE ENG.
EJTAG
SIZE
JOHN
KALDUNSKI
PAGE
12-8-1998_13:13
DATE
12/08/98
5-16
Schematics
Chapter Bill Materials
Table lists bill materials BDMR4102 Evaluation Board. reference numbers correspond those used schematics. board contains total components. Note that, since different manufacturers categorize their products different ways, some categories shown Table relevant products.
TinyRISC® BDMR4102 Evaluation Board User's Guide
packaging information:
Bill Materials
numbers shown packaging information frequently refer number pins package. example, 14PDIP indicates 14-pin dual in-line package, 44PLCC indicates 44-pin plastic leaded chip carrier, forth. other cases, number refers standard packaging type, such capacitor package 1206. case onboard devices, numbers (C1, forth) represent board locations. Items designated ACC, removable accessory modules, such SDRAM DIMM, that supplied with board.
Table
BDMR4102 Bill Materials
Manufacturer's Part Number MT2LSDT432UG-10 PSA-30U050 BR1225-1HC
Qty.
Reference Designator(s) ACC1 ACC2 C1316, C18-21
Device Name Mbytes SDRAM DIMM Power Supply Lithium Battery Capacitors Capacitor Tantalum Capacitors 1206 Capacitors 0805 Capacitors 0805 Capacitor Tantalum Capacitor
Package 100-pin DIMM Battery 0805 1206 1206 0805 0805
Value/Type 5V@4A 0.47 0.33 0.047
Manufacturer Micron Phihong Panasonic
(Sheet
Table
BDMR4102 Bill Materials (Cont.)
Manufacturer's Part Number HSMG-C650 HSMY-C650 HSMR-C650 AAVID Switchcraft Molex 577002B00000 RAPC722 650907-5 71251-5101
Qty.
Reference Designator(s) CX1-49, CX60-62, CX58, CX59 HS1,
Device Name Capacitors Capacitors Small LEDs Small LEDs Small LEDs Heatsinks Power Plug 150-Pin 41612 Connector 100-Pin DIMM Socket 16-Pin Header 52-Pin High-Speed Header 20-Pin High-Speed Header RJ45 Connector 10-Pin Header
Package 0805 0805 1206 1206 1206 TO-220-HS Typec 100-Pin DIMM 16-Pin Header, 52-Pin Header, 0.05 0.05 20-Pin Header, 0.05 0.05 10-Pin Header,
Value/Type 0.01 Green Yellow Pins
Manufacturer Hewlett Packard
(Sheet
Table
BDMR4102 Bill Materials (Cont.)
Manufacturer's Part Number
Bill Materials
Qty.
Reference Designator(s) JP1-13, JP18 JP14-17 R4-7, R8-10, R20-25 R14,
Device Name 9-Pin Subconnector Header 2-Pin Headers Jumpers 3-Pin Headers Jumpers Resistor Resistors Resistors Resistors Resistors Resistor Resistor Resistors Resistor Resistor Resistor
Package MIL-C-24308 8-Pin .025 Square 2-Pin .025 Square 3-Pin .025 Square 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805
Value/Type Male
Manufacturer
82.5
(Sheet
Table
BDMR4102 Bill Materials (Cont.)
Manufacturer's Part Number TP11CGPC0 2QSP16-TJ2-XXX 2QSP16-TJ1-XXX PE-68025 74LCX14M AM29F080-90EC NS24C08M8 MAX3245CAI
Qty.
Reference Designator(s) TP1-6 U2-4, U18, U20, U7-9,
Device Name SPST Switch Test Points LR4102 Microprocessor 16-Pin 15-Resistor Arrays Oscillator Oscillator 16-Pin 8-Resistor Arrays Ethernet Transformer 10BASE-T Module 74LCX14 Mbyte Flash Kbyte EEPROM 3245 RS232 transceiver Small Oscillator
Package 2-Pin Switch .025 Square PBGA 16-Pin QSOP 14-Pin Socket 14-Pin Socket 16-Pin QSOP 16-Pin Small 14-Pin SOIC 40-Pin TSOP 8-Pin SOIC 28-Pin SSOP 4-Pin
Value/Type 1.8432
Manufacturer Alcoswitch Logic Bourns Bourns Pulse National Semiconductor Advanced Micro Devices Fairchild Semiconductor Maxim
(Sheet
Table
BDMR4102 Bill Materials (Cont.)
Manufacturer's Part Number LT1084CT 2QSP16-TJ1-XXX AM79C970AVC 74LCX16244MTD PC16550DV IDT71V254SA12Y 74LCX245WM NC7SZ08M5 74LCX541WM MAX708CSA QS74FCT543ATQ HDSP-F101
Bill Materials
Qty.
Reference Designator(s) U26-29 U31,
Device Name Linear Adjustable Voltage Regulator Small 16-Pin 8-Resistor Array PCNet Device (Ethernet Controller) 74LCX16244 (Address Buffer) UART 32-Pin Socket SRAM 74LCX245 Tiny Gate 74LCX541 74FCT543 7-Segment Display
Package TO-220 16-Pin QSOP 144-Pin TQFP 48-Pin TSSOP 44-Pin PLCC 32-Pin 28SOJ300MIL 20-Pin SOIC SOT23-5 20-Pin SOIC 8-Pin SOIC 24-Pin QSOP 10-Pin
Value/Type
Manufacturer Linear Bourns Advanced Micro Devices National Semiconductor National Semiconductor National Semiconductor Fairchild National Semiconductor Maxim Quality Semiconductor Hewlett Packard
(Sheet
Table
BDMR4102 Bill Materials (Cont.)
Manufacturer's Part Number LT1084CT-3.3 DS1307Z SN74CBTD3306D ISPLSI2032V-100LT44
Qty.
Reference Designator(s)
Device Name Linear Regulator Real-Time Clock Dual Switch CPLD (PAL) Crystal Crystal Crystal
Package TO-220 8-Pin SOIC 8-Pin SOIC 44-Pin TQFP Cylinder
Value/Type 14.7456 32.768
Manufacturer Linear Dallas Semiconductor Texas Instruments Lattice Semiconductor
(Sheet
Bill Materials
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User's Guide Order Number C14064 Document DB15-000096-01, Se

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