SBAS203A MARCH 2002 Precision Analog-to-Digital Converter (ADC) w
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MSC1210
SBAS203A MARCH 2002
Precision Analog-to-Digital Converter (ADC) with 8051 Microcontroller Flash Memory
FEATURES
ANALOG FEATURES 24-BITS MISSING CODES 22-BITS EFFECTIVE RESOLUTION 10Hz Noise: 75nV FROM PRECISION ON-CHIP VOLTAGE REFERENCE: Accuracy: 0.2% Drift: 5ppm/°C DIFFERENTIAL/SINGLE-ENDED CHANNELS ON-CHIP OFFSET/GAIN CALIBRATION OFFSET DRIFT: 0.02PPM/°C GAIN DRIFT: 0.5PPM/°C BURN-OUT SENSOR DETECTION SINGLE-CYCLE CONVERSION SELECTABLE BUFFER INPUT DIGITAL FEATURES Microcontroller Core 8051 COMPATIBLE HIGH SPEED CORE: Clocks Instruction Cycle 33MHz SINGLE INSTRUCTION 121ns DUAL DATA POINTER Memory 32kB FLASH DATA MEMORY FLASH MEMORY PARTITIONING ENDURANCE ERASE/WRITE CYCLES, YEAR DATA RETENTION IN-SYSTEM SERIALLY PROGRAMMABLE EXTERNAL PROGRAM/DATA MEMORY (64kB) 1,280 BYTES DATA SRAM FLASH MEMORY SECURITY BOOT PROGRAMMABLE WAIT STATE CONTROL
registered trademark Motorola.
Peripheral Features PINS ADDITIONAL 32-BIT ACCUMULATOR THREE 16-BIT TIMER/COUNTERS SYSTEM TIMERS PROGRAMMABLE WATCHDOG TIMER FULL DUPLEX DUAL UART MASTER/SLAVE SPIWITH 16-BIT POWER MANAGEMENT CONTROL IDLE MODE CURRENT STOP MODE CURRENT PROGRAMMABLE BROWNOUT RESET PROGRAMMABLE VOLTAGE DETECT INTERRUPT SOURCES HARDWARE BREAKPOINTS GENERAL FEATURES PACKAGE: TQFP-64 POWER: INDUSTRIAL TEMPERATURE RANGE: -40°C +85°C POWER SUPPLY: 2.7V 5.25V
APPLICATIONS
INDUSTRIAL PROCESS CONTROL INSTRUMENTATION LIQUID/GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTS WEIGH SCALES PRESSURE TRANSDUCERS INTELLIGENT SENSORS PORTABLE APPLICATIONS SYSTEMS
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2002, Texas Instruments Incorporated
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PACKAGE/ORDERING INFORMATION
FLASH MEMORY PACKAGE-LEAD TQFP-64 PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE -40°C +85°C PACKAGE MARKING MSC1210Y2 ORDERING NUMBER MSC1210Y2PAGT MSC1210Y2PAGR MSC1210Y3PAGT MSC1210Y3PAGR MSC1210Y4PAGT MSC1210Y4PAGR MSC1210Y5PAGT MSC1210Y5PAGR TRANSPORT MEDIA, QUANTITY Tape Reel, Tape Reel, 2000 Tape Reel, Tape Reel, 2000 Tape Reel, Tape Reel, 2000 Tape Reel, Tape Reel, 2000
PRODUCT MSC1210Y2 MSC1210Y2 MSC1210Y3 MSC1210Y3 MSC1210Y4 MSC1210Y4 MSC1210Y5 MSC1210Y5
TQFP-64
-40°C +85°C
MSC1210Y3
TQFP-64
-40°C +85°C
MSC1210Y4
TQFP-64
-40°C +85°C
MSC1210Y5
NOTE: most current specifications package information, refer site www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Analog Inputs Input Current 100mA, Momentary Input Current 10mA, Continuous Input Voltage AGND 0.5V AVDD 0.5V Power Supply DVDD DGND -0.3V AVDD AGND -0.3V AGND DGND -0.3V +0.3V VREF AGND -0.3V AVDD 0.3V Digital Input Voltage DGND -0.3V DVDD 0.3V Digital Output Voltage DGND -0.3V DVDD 0.3V Maximum Junction Temperature +150°C Operating Temperature Range -40°C +85°C Storage Temperature Range -65°C +150°C Lead Temperature (soldering, 10s) +300°C Package Power Dissipation 900mW Output Current Pins 200mA Output Short Circuit Thermal Resistance, Junction-to-Ambient (JA) 66.6°C/W Thermal Resistance, Junction-to-Case (JC) 4.3°C/W Digital Outputs Output Current 100mA, Continuous Source/Sink Current 100mA Power Maximum 300mA NOTE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute-maximumrated conditions extended periods affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
MSC1210YX FAMILY FEATURES
FEATURES
MSC1210Y2(2) 1024 Program, Data
MSC1210Y3(2) 1024 Program, Data
MSC1210Y4(2) 1024 Program, Data
MSC1210Y5(2) 1024 Program, Data
Flash Program Memory (Bytes) Flash Data Memory (Bytes) Internal Scratchpad (Bytes) Internal MOVX SRAM (Bytes) Externally Accessible Memory (Bytes)
NOTES: peripheral features same devices; flash memory size only difference. last digit part number represents onboard flash size )kBytes.
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ELECTRICAL CHARACTERISTICS: AVDD
specifications from TMIN TMAX, DVDD +2.7V 5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified. MSC1210Yx PARAMETER ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources OFFSET Offset Range Offset Monotonicity Offset Gain Error Offset Gain Error Drift SYSTEM PERFORMANCE Resolution ENOB Output Noise Missing Codes Integral Nonlinearity Offset Error Offset Drift(1) Gain Error Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection CONDITION Buffer Buffer (In+) (In-) Figure Buffer Buffer -3dB -3dB -3dB User-Selectable Gain Ranges Modulator Off. +25°C Input Open Cicuit AGND AGND 5/PGA 0.469 fDATA 0.318 fDATA 0.262 fDATA ±VREF/(2 PGA) ±1.5 Typical Characteristics Sinc3 Filter Point After Calibration Before Calibration After Calibration Before Calibration ±0.0015 0.02 0.002 AVDD Bits Range ppm/°C Bits Bits Bits %FSR FS/°C ppm/°C ppm/°C µV/°C 5.25 AVDD AVDD ±VREF/PGA UNITS
Normal Mode Rejection Power-Supply Rejection VOLTAGE REFERENCE INPUT Reference Input Range VREF Common-Mode Rejection Common-Mode Rejection Input Current(3) ON-CHIP VOLTAGE REFERENCE Output Voltage Power-Supply Rejection Ratio Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Drift Output Impedance Startup Time from Power Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coeff. ANALOG POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current (IADC IVREF) Current (IADC)
60Hz, fDATA 10Hz 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz fSIG 50Hz, fDATA 50Hz fSIG 60Hz, fDATA 60Hz -20log(VOUT/VDD)(2) IN+, VREF (REF IN+) (REF IN-) 60Hz, fDATA 60Hz REFCM VREF 2.5V VREFH +25°C VREFH
1.25 Indefinite
2.495
2.505
Sink Source Sourcing 100uA CREF 0.1µF +25°C
AVDD Analog OFF, PDAD Buffer 128, Buffer Buffer 128, Buffer
4.75
VREF Current (IVREF)
NOTES: Calibration minimize these errors. DVOUT change digital result. 12pF switched capacitor fSAMP clock frequency (see Figure
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ELECTRICAL CHARACTERISTICS: AVDD
specifications from TMIN TMAX, AVDD +3V, DVDD +2.7V 5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +1.25V, unless otherwise specified. MSC1210Yx PARAMETER ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources OFFSET Offset Range Offset Monotonicity Offset Gain Error Offset Gain Error Drift SYSTEM PERFORMANCE Resolution ENOB Output Noise Missing Codes Integral Non-Linearity Offset Error Offset Drift(1) Gain Error Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection CONDITION Buffer Buffer (In+) (In-) Figure Buffer Buffer -3dB -3dB -3dB User-Selectable Gain Ranges Modulator Off, +25°C Sensor Input Open Circuit AGND AGND 5/PGA 0.469 fDATA 0.318 fDATA 0.262 fDATA ±VREF/(2 PGA) ±1.5 Typical Characteristics Sinc3 Filter Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration ±0.0015 0.02 0.010 AVDD Bits Range ppm/°C Bits Bits Bits %FSR FS/°C ppm/°C ppm/°C µV/°C AVDD AVDD ±VREF/PGA UNITS
Normal Mode Rejection Power-Supply Rejection VOLTAGE REFERENCE INPUT Reference Input Range VREF Common-Mode Rejection Common-Mode Rejection Input Current(3) ON-CHIP VOLTAGE REFERENCE Output Voltage Power-Supply Rejection Ratio Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Drift Output Impedance Startup Time from Power Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coeff. POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current (IADC IVREF) Current (IADC)
fSIG fSIG
60Hz, fDATA 10Hz 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz -20log(DVOUT/DVDD)(2)
IN+, VREF (REF IN+) (REF IN-) 60Hz, fDATA VREF 1.25V VREFH +25°C
1.25 1.25 Indefinite
1.245
1.255
Sink Source Sourcing 100uA CREF 0.1µF +25°C
AVDD Analog OFF, PDAD Buffer 128, Buffer Buffer 128, Buffer
VREF Current (IVREF)
NOTES: Calibration minimize these errors. DVOUT change digital result. 12pF switched capacitor fSAMP clock frequency (see Figure
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DIGITAL CHARACTERISTICS: DVDD 2.7V 5.25V
specifications from TMIN TMAX, fOSC 1MHz, unless otherwise specified. MSC1210Yx PARAMETER POWER-SUPPLY REQUIREMENTS DVDD Normal Mode, fOSC 1MHz Normal Mode, fOSC 8MHz Stop Mode DVDD Normal Mode, fOSC 1MHz Normal Mode, fOSC 8MHz Stop Mode DIGITAL INPUT/OUTPUT (CMOS) Logic Level: (except pin) (except pin) Ports 0-3, Input Leakage Current, Input Mode Pins Input Leakage Current VOL, ALE, PSEN, Ports 0-3, Output Modes VOL, ALE, PSEN, Ports 0-3, Output Modes VOH, ALE, PSEN, Ports 0-3, Strong Drive Output VOH, ALE, PSEN, Ports 0-3, Strong Drive Output Ports Pull-Up Resistors Pins ALE, PSEN, Pull-Up Resistors RST, Pull Down Resistor 4.75 DVDD DGND DGND DVDD DVDD DVDD 5.25 CONDITION UNITS
DVDD 30mA 30mA Flash Programming Mode Only
DVDD DVDD DVDD
FLASH MEMORY CHARACTERISTICS: DVDD 2.7V 5.25V
MSC1210Yx PARAMETER Flash Memory Endurance Flash Memory Data Retention CONDITION 100,000 1,000,000 UNITS cycles Years
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ELECTRICAL CHARACTERISTICS(1)(2): DVDD 2.7V 5.25V
2.7V 3.6V SYMBOL System Clock 1/tCLK FIGURE Program Memory tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH External Clock tHIGH tLOW PARAMETER External Crystal Frequency (fOSC) External Clock Frequency (fOSC) External Ceramic Resonator Frequency (fOSC) Pulse Width Address Valid Address Hold After Valid Instruction PSEN PSEN Pulse Width PSEN Valid Instruction Input Instruction Hold After PSEN Input Instruction Float After PSEN Address Valid Instruction PSEN Address Float tCLK 3tCLK 0.5tCLK 2tCLK 2tCLK tCLK 3tCLK 1.5tCLK 0.5tCLK 0.5tCLK 2.5tCLK 0.5tCLK 2tCLK 2tCLK 4.75V 5.25V 1.5tCLK 0.5tCLK 0.5tCLK 2.5tCLK UNITS
Pulse Width (tMCS Pulse Width (tMCS Pulse Width (tMCS Pulse Width (tMCS Valid Data (tMCS Valid Data (tMCS Data Hold After Read Data Float After Read (tMCS Data Float After Read (tMCS Valid Data (tMCS Valid Data (tMCS Address Valid Data (tMCS Address Valid Data (tMCS (tMCS (tMCS Address (tMCS Address (tMCS Data Valid Transition Data Hold After Address Float HIGH HIGH (tMCS HIGH HIGH (tMCS HIGH Time(3) Time(3) Rise Time(3) Fall Time(3)
2tCLK tMCS 2tCLK tMCS 2tCLK tMCS tCLK 2tCLK 2.5tCLK tCLK tMCS 3tCLK 1.5tCLK tMCS 0.5tCLK tCLK tCLK 2tCLK tCLK -0.5tCLK tCLK tCLK 0.5tCLK tCLK
2tCLK tMCS 2tCLK tMCS 2tCLK tMCS tCLK 2tCLK 2.5tCLK tCLK tMCS 3tCLK 1.5tCLK tMCS 0.5tCLK tCLK tCLK 2tCLK tCLK -0.5tCLK tCLK tCLK 0.5tCLK tCLK
NOTES: Parameters valid over operating temperature range, unless otherwise specified. Load capacitance Port ALE, PSEN 100pF, load capacitance other outputs 80pF. These values characterized 100% production tested. tCLK 1/fOSC oscillator clock period. tMCS time period related Stretch MOVX selection. following table shows value tMCS each stretch selection.
MOVX DURATION Machine Cycles Machine Cycles (default) Machine Cycles Machine Cycles Machine Cycles Machine Cycles Machine Cycles Machine Cycles
tMCS 4tCLK 8tCLK 12tCLK 16tCLK 20tCLK 24tCLK 28tCLK
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SBAS203A
EXPLANATION SYMBOLS
Each Timing Symbol five characters. first character always time). other characters, depending their positions, indicate name signal logical status that signal. designators are: A-Address C-Clock D-Input Data H-Logic Level HIGH I-Instruction (program memory contents) L-Logic Level LOW, P-PSEN Q-Output Data R-RD Signal t-Time V-Valid W-WR Signal X-No Longer Valid Logic Level Z-Float Examples: tAVLL Time address valid LOW. tLLPL Time PSEN LOW.
tLHLL tAVLL tLLPL tLLIV PSEN tLLAX PORT A0-A7 tPLAZ tPLIV tPXIZ tPXIX INSTR A0-A7 tPLPH
tAVIV PORT A8-A15 A8-A15
FIGURE External Program Memory Read Cycle
tWHLH PSEN
tLLDV tLLWL tRLRH
tAVLL tLLAX tRLAZ PORT A0-A7 from tAVWL tAVDV PORT P2.0-P2.7 A8-A15 from A8-A15 from tRLDV tRHDX DATA A0-A7 from INSTR tRHDZ
FIGURE External Data Memory Read Cycle
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EXPLANATION SYMBOLS (Cont.)
tWHLH PSEN tLLWL tWLWH
tAVLL tLLAX tQVWX PORT A0-A7 from tAVWL DATA A0-A7 from INSTR tWHQX
PORT
P2.0-P2.7 A8-A15 from
A8-A15 from
FIGURE External Data Memory Write Cycle
tHIGH VIH1 0.8V VIH1 0.8V tLOW VIH1 0.8V tCLK
VIH1 0.8V
FIGURE External Clock Drive
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CONFIGURATION
View
P1.7/INT5/SCLK P1.5/INT3/MOSI P1.6/INT4/MISO P1.4/INT2/SS
TQFP
P1.1/T2EX
P1.2/RxD1
P1.3/TxD1
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
XOUT P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.3/INT1/TONE/PWM P3.4/T0 P3.5/T1 P3.6/WR
P0.6/AD6 P0.7/AD7 PSEN/OSCCLK/MODCLK P2.7/A15 DVDD DGND
MSC1210
P0.5/AD5
P1.0/T2
DGND
DVDD
P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A09 P2.0/A08
P3.7/RD DVDD DGND DVDD DVDD
AGND
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6/EXTD
AIN7/EXTA
AINCOM
AGND
AVDD
DESCRIPTIONS
3-10 NAME XOUT P3.0-P3.7 DESCRIPTION crystal oscillator XOUT supports parallel resonant crystals ceramic resonators. XOUT serves output crystal amplifier. crystal oscillator supports parallel resonant crystals ceramic resonators. also input there external clock source instead crystal. Port bidirectional port. alternate functions Port3 listed below. Port 3-Alternate Functions: PORT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 DVDD DGND AGND AVDD AIN0 ALTERNATE RxD0 TxD0 INT0 INT1/TONE/PWM MODE Serial Port Input Serial Port Output External Interrupt External Interrupt 1/TONE/PWM Output Timer External Input Timer External Input External Data Memory Write Strobe External Data Memory Read Strobe
Digital Power Supply Digital Ground HIGH reset input instruction clock cycles will reset device. Connection Analog Ground Analog Power Supply Analog Input Channel
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DESCRIPTIONS (Cont.)
34-40, NAME AIN1 AIN2 AIN3 AIN4 AIN5 AIN6, EXTD AIN7, EXTA AINCOM P2.0-P2.7 DESCRIPTION Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Digital Voltage Detect Input Analog Input Channel Analog Voltage Detect Input Analog Common Single-Ended Inputs Voltage Reference Negative Input Voltage Reference Positive Input Voltage Reference Output Port bidirectional port. alternate functions Port listed below. Port 2-Alternate Functions: PORT P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN OSCCLK MODCLK ALTERNATE MODE Address Address Address Address Address Address Address Address
Program Store Enable: Connected optional external memory chip enable. PSEN will provide active pulse. programming mode, PSEN used input along with define serial parallel programming mode. PSEN held HIGH parallel programming tied serial programming. This also selected (when using external program memory) output Oscillator clock, Modulator clock, HIGH, LOW. PSEN PROGRAM MODE SELECTION Normal Operation Parallel Programming Serial Programming Reserved
Address Latch Enable: Used latching byte address during access external memory. emitted constant rate oscillator frequency, used external timing clocking. pulse skipped during each access external data memory. programming mode, used input along with PSEN define serial parallel programming mode. held HIGH serial programming tied parallel programming. External Access Enable: must externally held enable device fetch code from external program memory locations starting with 0000H. Port bidirectional port. alternate functions Port listed below. Port 0-Alternate Functions: PORT P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALTERNATE MODE Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data
49-54
P0.0-P0.7
59-64
P1.0-P1.7
Port bidirectional port. alternate functions Port listed below. Port 1-Alternate Functions: PORT P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 ALTERNATE T2EX RxD1 TxD1 INT2/SS INT3/MOSI INT4/MISO INT5/SCK MODE Input External Input Serial Port Input Serial Port Output External Interrupt/Slave Select External Interrupt/Master Out-Slave External Interrupt/Master In-Slave External Interrupt/Serial Clock
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TYPICAL CHARACTERISTICS
AVDD +5V, DVDD +5V, fOSC 8MHz, fDATA 10Hz, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA1 PGA2 PGA4 PGA8
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA2 PGA4 PGA8
ENOB (rms) ENOB (rms)
PGA16 PGA32 PGA64 PGA128
PGA1
PGA32 PGA16
PGA64
PGA128
Sinc3 Filter, Buffer
Sinc3 Filter, Buffer
1000 Decimation Ratio fMOD
1500 fDATA
2000
1000 Decimation Ratio fMOD
1500 fDATA
2000
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA1 PGA2 PGA4 PGA8
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA2 PGA4 PGA8
ENOB (rms) ENOB (rms)
Sinc3 Filter, VREF 1.25V, Buffer 1000 Decimation Ratio fMOD fDATA 1500 2000
PGA1
PGA16 PGA32 PGA64 PGA128
PGA16
PGA32
PGA64
PGA128
Sinc3 Filter, VREF 1.25V, Buffer
1000 Decimation Ratio fMOD
1500 fDATA
2000
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA2 PGA4 PGA8
FAST SETTLING FILTER EFFECTIVE NUMBER BITS DECIMATION RATIO
ENOB (rms)
PGA1
ENOB (rms)
1000 Decimation Ratio 1500 fMOD fDATA 2000 Sinc2 Filter
PGA32 PGA16 PGA64 PGA128
1000 Decimation Ratio 1500 fMOD fDATA 2000 Fast Settling Filter
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TYPICAL CHARACTERISTICS (Cont.)
AVDD +5V, DVDD +5V, fOSC 8MHz, fDATA 10Hz, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
NOISE INPUT SIGNAL
Noise (rms,
CMRR FREQUENCY 100k Frequency Signal (Hz)
-2.5
-1.5
-0.5
PSRR FREQUENCY 100k Frequency Power Supply (Hz)
CMRR (dB)
OFFSET TEMPERATURE PGA1 PGA16
Offset (ppm
PSRR (dB)
PGA64 PGA128 -150
-100
-200 Temperature (°C)
GAIN TEMPERATURE 1.00010 1.00006
Gain (Normalized)
INTEGRAL NON-LINEARITY INPUT SIGNAL
(ppm
-40°C
1.00002 0.99998 0.99994 0.99990 0.99986 Temperature (°C)
-2.5 -1.5 -0.5 +25°C +85°C
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TYPICAL CHARACTERISTICS (Cont.)
AVDD +5V, DVDD +5V, fOSC 8MHz, fDATA 10Hz, Buffer 0VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
MAXIMUM ANALOG CURRENT TEMPERATURE 1.25 1.20 1.15
CURRENT AVDD Buffer Buffer
Current (mA)
1.10 1.05 1.00 0.95 0.90 0.85 0.80 Temperature (°C)
IADC (µA)
AVDD Buffer Buffer
Setting
HISTOGRAM OUTPUT DATA 4500 4000 2.55
VREFOUT LOAD CURRENT
Number Occurrences
3500
2500 2000 1500 1000 -1.5 -0.5
VREFOUT
3000
2.50
2.45 -0.5
VREFOUT Current Load (mA)
OFFSET DAC: OFFSET TEMPERATURE 1.00020 1.00016 1.00012
Normalized Gain
OFFSET GAIN TEMPERATURE
Offset (ppm FSR)
-100 Temperature (°C)
1.00008 1.00004 1.00000 0.99996 0.99992 0.99988 0.99984 0.99980 0.99976 Temperature (°C)
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TYPICAL CHARACTERISTICS (Cont.)
AVDD +5V, DVDD +5V, fOSC 8MHz, fDATA 10Hz, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
DIGITAL CURRENT FREQUENCY
DIGITAL STOP CURRENT FREQUENCY
Supply Current (mA)
Digital Current (µA)
Clock Frequency (MHz)
Clock Frequency (MHz)
MAXIMUM ERROR
DIGITAL CURRENT TEMPERATURE 21.5
21.0
Full-Scale
Setting
Current (mA)
20.5
20.0
19.5
19.0 Temperature (°C)
NORMALIZED GAIN
CMOS DIGITAL OUTPUT
Normalized Gain
Output Voltage
Output
Setting
Output Current (mA)
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DESCRIPTION
MSC1210Yx completely integrated family mixedsignal devices incorporating high-resolution delta-sigma ADC, 8-channel multiplexer, burn-out current sources, selectable buffered input, offset (Digital-to-Analog Converter), Programmable Gain Amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, Data SRAM, shown Figure On-chip peripherals include additional 32-bit accumulator, compatible serial port with FIFO, dual UARTs, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, 16-bit PWM, breakpoints, brownout reset, three timer/counters. device accepts low-level differential single-ended signals directly from transducer. provides bits resolution bits no-missing-code performance using sinc3 filter with programmable sample rate. also selectable filter that allows high-resolution single-cycle conversion. microcontroller core 8051 instruction compatible. microcontroller core optimized 8051 core which executes three times faster than standard 8051 core, given same clock source. That makes possible device lower external clock frequency achieve same performance lower power than standard 8051 core.
MSC1210Yx allows user uniquely configure Flash SRAM memory maps meet needs their application. Flash programmable down 2.7V using both serial parallel programming methods. Flash endurance 100k Erase/Write cycles. addition, 1,280 bytes incorporated on-chip. part separate analog digital supplies, which independently powered from 2.7V +5.5V. operation, power dissipation part typically less than 4mW. MSC1210Yx packaged TQFP-64 package. MSC1210Yx designed high-resolution measurement applications smart transmitters, industrial process control, weigh scales, chromatography, portable instrumentation.
ENHANCED 8051 CORE
instructions MSC1210 family perform exactly same functions they would standard 8051. effect bits, flags, registers same. However, timing different. MSC1210 family utilizes efficient 8051 core which results improved instruction execution speed between times faster than original core same external clock speed clock cycles instruction versus clock cycles instruction, shown Figure This translates into effective throughput
AVDD
AGND
DVDD
DGND
+AVDD VREF Timers/ Counters AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM FLASH 1.2K SRAM PORT2 8051 PORT3 Clock Generator AGND XOUT FIFO ADDR UART1 Modulator Digital Filter PORT0 8-Bit Offset Alternate Functions ADDR DATA SPI/EXT UART2 PSEN
PORT1
FIGURE Block Diagram.
instr_cycle
cpu_cycle
FIGURE Instruction Cycle Timing.
MSC1210
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improvement more than times, using same code same external clock speed. Therefore, device frequency 33MHz MSC1210Yx actually performs equivalent execution speed 82.5MHz compared standard 8051 core. This allows user device slower external clock speeds which reduces system noise power consumption, provides greater throughput. This performance difference seen Figure timing software loops will faster with MSC1210. However, timer/counter operation MSC1210 maintained clocks increment optionally clocks increment. MSC1210 also provides dual data pointers (DPTRs) speed block Data Memory moves. Additionally, stretch number memory cycles access external Data Memory from between nine instruction cycles order accommodate different speeds memory devices, shown Table MSC1210 provides external memory interface with 16-bit address P2). 16-bit address makes necessary
CKCON (8EH) MD2:MD0 INSTRUCTION CYCLES (for MOVX) (default) STROBE WIDTH (SYS CLKs) STROBE WIDTH (µs) 12MHz 0.167 0.333 0.667 1.000 1.333 1.667 2.000 2.333
multiplex address byte through port. enhance high-speed memory access, hardware configuration control provided configure ports external memory/peripheral interface general-purpose I/O. Furthermore, improvements were made peripheral features that offload processing from core, user, further improve efficiency. instance, interface uses FIFO, which allows interface transmit receive data with minimum overhead needed from core. Also, 32-bit accumulator added significantly reduce processing overhead multiple byte data from other sources. This allows 24-bit addition shifting accomplished instruction cycles, compared hundreds instruction cycles through software implementation.
Family Device Compatibility
hardware functionality configuration across MSC1210 family fully compatible. user only difference between family members memory configuration. This makes migration between family members simple. Code written MSC1210Y2 executed directly MSC1210Y3, MSC1210Y4, MSC1210Y5. This gives user ability subtract software functions freely migrate between family members. Thus, MSC1210 become standard device used across several application platforms.
Family Development Tools
MSC1210 fully compatible with standard 8051 instruction set. This means that user develop software MSC1210 with their existing 8051 development tools. Additionally, complete, integrated development environment provided with each demo board, third party developers also provide support.
TABLE Memory Cycle Stretching. Stretching MOVX timing defined MD2, MD1, bits CKCON register (address 8EH).
Single-Byte, Single-Cycle Instruction PSEN
MSC1210 Timing
AD0-AD7 PORT Cycles Cycles
Standard 8051 Timing
PSEN AD0-AD7 PORT Single-Byte, Single-Cycle Instruction
FIGURE Comparison MSC1210 Timing Standard 8051 Timing.
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OVERVIEW
INPUT MULTIPLEXER
input multiplexer provides combination differential inputs selected input channel, shown Figure AIN0 selected positive differential input channel, other channel selected negative differential input channel. With this method, possible have eight fully differential input channels. also possible switch polarity differential input pair negate offset voltages.
INPUT BUFFER
analog input impedance always high, regardless setting (when buffer enabled). With buffer enabled, input voltage range reduced analog power-supply current higher. limitation input voltage range acceptable, then buffer always beneficial. input impedance MSC1210 without buffer 5M/PGA. buffer controlled state control register (ADCON0 DCH).
ANALOG INPUT
When buffer selected, input impedance analog input changes with clock frequency (ACLK F6H) gain (PGA). relationship pedance ACLK Frequency
Burnout Current Source
AIN0
AIN1
AVDD
AIN2
Figure shows basic input structure MSC1210.
AIN3
typical)
AIN4
High Impedance CINT 12pF Typical
AIN5
Switching Frequency fSAMP
Burnout Current Source
AIN6 AGND AIN7
FIGURE Analog Input Structure.
Programmable Gain Amplifier (PGA) gains 128. Using actually improve effective resolution ADC. instance, with full-scale range, resolve 1µV. With 40mV full-scale range, resolve 75nV. With full-scale range, would require 26-bit resolve 76nV.
AINCOM
FIGURE Input Multiplexer Configuration. addition, current sources supplied that will source sink current detect open short circuits pins.
OFFSET
analog input offset half full-scale input range using ODAC register (SFR E6H). ODAC (Offset DAC) register 8-bit value; sign seven LSBs provide magnitude offset. Since ODAC introduces analog (instead digital) offset PGA, using ODAC does reduce performance ADC.
TEMPERATURE SENSOR
On-chip diodes provide temperature sensing capability. When configuration register input diodes connected input Analog-to-Digital Converter (ADC). other channels open.
BURNOUT CURRENT SOURCES
When Burnout Detect (BOD) control configuration register (ADCON0 DCH), current sources enabled. current source positive input channel sources approximately current. current source negative input channel sinks approximately 2µA. This allows detection open circuit (full-scale reading) short circuit (small differential reading) selected input differential pair.
MODULATOR
modulator single-loop second-order system. modulator runs clock speed (fMOD) that derived from using value Analog Clock register (ACLK). data output rate (ACLK 1)/64/(Decimation Ratio).
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CALIBRATION
offset gain errors MSC1210, complete system, reduced with calibration. Calibration controlled through ADCON1 register (SFR DDH), bits CAL2:CAL0. Each calibration process takes seven tDATA periods (data conversion time) complete. Therefore, takes tDATA periods complete both offset gain calibration. system calibration, appropriate signal must applied inputs. system offset command requires "zero" differential input signal. then computes offset that will nullify offset system. system gain command requires positive "full-scale" differential input signal. then computes value nullify gain errors system. Each these calibrations will take seven tDATA periods complete. Calibration should performed after power change temperature, decimation ratio, buffer, change PGA. Calibration will remove effects Offset DAC, therefore, changes Offset register must done after calibration. completion calibration, Interrupt goes HIGH which indicates calibration finished valid data available.
Fast Settling filter, next conversions first which should discarded. will then Sinc2 followed Sinc3 filter improve noise performance. This combines low-noise advantage Sinc3 filter with quick response Fast Settling Time filter. frequency response each filter shown Figure
SINC3 FILTER RESPONSE (-3dB 0.262 fDATA)
Gain (dB)
-100 -120 Frequency (Hz) SINC2 FILTER RESPONSE (-3dB 0.318 fDATA)
DIGITAL FILTER
Digital Filter either Fast Settling, Sinc2, Sinc3 filter, shown Figure addition, Auto mode changes Sinc filter after input channel changed. When switching channel, will
Gain (dB)
Adjustable Digital Filter Sinc3
-100 -120 Frequency (Hz)
Modulator
Sinc2
Data
FAST SETTLING FILTER RESPONSE (-3dB 0.469 fDATA)
Fast Settling
SETTLING TIME (Conversion Cycles) 3(1) 2(1) 1(1)
Gain (dB)
FILTER SETTLING TIME FILTER Sinc3 Sinc2 Fast
-100 -120 Frequency (Hz)
NOTE: With Synchronized Channel Changes. AUTO MODE FILTER SELECTION CONVERSION CYCLE Discard Fast Sinc2 Sinc3 NOTE: Data Output Rate 1/tDATA
FIGURE Filter Step Responses.
FIGURE Filter Frequency Responses.
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VOLTAGE REFERENCE
voltage reference used MSC1210 either internal external. power-up configuration voltage reference 2.5V internal. selection voltage reference made through ADCON0 register (SFR DCH). internal voltage reference selectable either 1.25V (AVDD 2.7V 5.25V) 2.5V (AVDD 4.5V 5.25V). internal VREF used, should turned reduce noise power consumption. VREFOUT should have 0.1µF capacitor AGND. external voltage reference differential represented voltage difference between pins: IN-. absolute voltage either (REF IN-) range from AGND AVDD, however, differential voltage must exceed 2.6V. differential voltage reference provides easy means performing ratiometric measurement.
FLASH MEMORY
MSC1210 uses memory addressing scheme that separates Program Memory (FLASH/ROM) from Data Memory (FLASH/RAM). Each area 64kB beginning address 0000H ending FFFFH, shown Figure program data segments overlap since they accessed different ways. Program Memory fetched microcontroller automatically. There instruction (MOVC) that used explicitly read program area. This commonly used read lookup tables. Data Memory area accessed explicitly using MOVX instruction. This instruction provides multiple ways specifying target address. used access 64kB Data Memory. address data range devices with on-chip Program Data Memory overlap 64kB memory space. When on-chip memory enabled, accessing memory on-chip range will cause device access internal memory. Memory accesses beyond internal range will addressed externally Ports
POWER-UP-SUPPLY VOLTAGE RAMP RATE
built-in (on-chip) power-on reset circuitry designed accommodate analog digital supply ramp rates slow 1V/10ms. ensure proper operation, power supply should ramp monotonically specified rate.
Program Memory
Select HCR0
Internal Boot FFFFH F800H
Data Memory
FFFFH
External Program Memory
Select MCON
External External Memory
Mapped Either Memory Space 8800H 8400H, (Y5) 8000H, (Y5)
External Data Memory
External 8800H 8400H, (Y5) 4400H, (Y4)
MEMORY
MSC1210 contains on-chip SFR, Flash Memory, Scratchpad Memory, Boot ROM, SRAM. registers primarily used control status. standard 8051 features additional peripheral features MSC1210 controlled through SFR. Reading from undefined will return zero writing undefined registers recommended will have indeterminate effects. Flash Memory used both Program Memory Data Memory. user ability select partition size Program Data Memories. partition size through hardware configuration bits, which programmed through either parallel serial programming methods. Both Program Data Flash Memories erasable writable (programmable) user application mode. However, only program execution occur from Program Memory. added precaution, lock feature activated through hardware configuration bits, which disables erase writes Program Flash Memory entire Program Flash Memory user application mode. MSC1210 includes SRAM on-chip. SRAM starts address accessed through MOVX instruction. This SRAM also located start 8400H accessed both Program Data Memory.
Select MCON
4000H, (Y4)
2000H, (Y3)
1000H, (Y2) 0000H,
2400H, (Y3)
1400H, (Y2) 0400H,
External
FIGURE Memory Map. MSC1210 Hardware Configuration registers (HCR0 HCR1) that programmable only during Flash Memory Programming mode. MSC1210 allows user partition Flash Memory between Program Memory Data Memory. instance, MSC1210Y5 contains 32kB Flash Memory on-chip. Through configuration registers, user define partition between Program Memory (PM) Data Memory (DM), shown Table MSC1210 family offers four memory configurations, shown.
HCR0 DFSEL (default) MSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5 12kB 14kB 15kB 16kB 16kB 32kB 16kB 16kB 24kB 28kB 30kB 31kB 32kB
NOTE: When program memory configuration selected program execution external. reserved.
TABLE MSC1210Y Flash Partitioning.
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HCR0 DFSEL (reserved) (default)
MSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5
REGISTER
Register illustrated Figure entirely separate from Program Data Memory areas mentioned before. separate class instructions used access registers. There potential register locations. practice, MSC1210 bytes Scratchpad SFRs. This possible, since upper Scratchpad locations only accessed indirectly. That contents Working Register (described below) will designate location. Thus, direct reference upper locations must access. Direct reached locations 127).
0000 040013FF 0000 0400 13FF 0000 040013FF
0000 040023FF 0000 0400 23FF 0000 040023FF
0000 040043FF
0000 040083FF
0000 0400 0000- 040043FF 3FFF 43FF 0000- 0400- 0000- 04001FFF 23FF 5FFF 23FF 0000- 0400- 0000- 04002FFF 13FF 6FFF 13FF 0000- 0400- 0000- 040037FF 0BFF 77FF 0BFF 0000- 0400- 0000- 04003BFF 07FF 7BFF 07FF 0000- 0000 3FFF 0000- 0000 7FFF
0000 0400- 0000- 040013FF 0FFF 13FF 0000- 0400- 0000- 040007FF 0BFF 17FF 0BFF 0000- 0400- 0000- 04000BFF 07FF 1BFF 07FF 0000- 0000 0FFF 0000- 0000 1FFF
Indirect Direct 0000H Scratchpad
Direct Special Function Registers Registers
NOTE: Program memory accesses above highest listed address will access external program memory.
TABLE III. Flash Memory Partitioning. important note that Flash Memory readable writable (depending MXWS SFR) user through MOVX instruction when configured either Program Data Memory. This means that user partition device maximum Flash Program Memory size Flash Data Memory) Flash Program Memory Flash Data Memory. This lead undesirable behavior points area Flash Program Memory that being used data storage. Therefore, recommended Flash partitioning when Flash Memory used data storage. Flash partitioning prohibits execution code from Data Flash Memory. Additionally, Program Memory erase/ write disabled through hardware configuration bits (HCR0), while still providing access (read/write/erase) Data Flash Memory. effect memory mapping Program Data Memory straightforward. Program Memory decreased size from internal Program Memory. Therefore, MSC1210Y5 partitioned with 31kB Flash Program Memory Flash Data Memory, external Program Memory execution will begin 7C00H (versus 8000H 32kB). Flash Data Memory added SRAM memory. Therefore, access Data Memory (through MOVX) will access SRAM addresses 0000H-03FFH access Flash Memory addresses 0400H-07FFH.
FIGURE Register Map. SFRs accessed directly between (128 255). locations between reached through indirect reference those locations. Scratchpad available general-purpose data storage. commonly used place off-chip when total data contents small. When off-chip needed, Scratchpad area will still provide fastest generalpurpose access. Within bytes RAM, there several special-purpose areas.
Addressable Locations
addition direct register access, some individual bits also accessible. These individually addressable bits both area. Scratchpad area, registers addressable. This provides individual bits available software. access distinguished from full-register access type instruction. area, register location ending addressable. Figure shows details onchip addressing including locations individual bits.
Data Memory
MSC1210 address 64kB Data Memory. Scratchpad Memory provides bytes addition 64kB Data Memory. MOVX instruction used access Data SRAM Memory. This includes 1,024 bytes on-chip Data SRAM Memory. data values appear Port (during data timing) internal memory access. MSC1210 also on-chip Flash Data Memory which readable writable (depending Memory Write Select register) during normal operation (full range). This memory mapped into external Data Memory space directly above SRAM.
Working Registers
part lower bytes RAM, there four banks Working Registers (each). Working Registers generalpurpose locations that addressed special way. They designated through Since there four banks, currently selected bank will used instruction using R0-R7. This allows software change context simply switching banks. This controlled Program Status Word register (PSW; 0D0H) area described below. Working Registers also allow their contents used indirect address-
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upper bytes RAM. Thus, instruction designate value stored (for example) address upper RAM. bytes immediately above these registers addressable. bits this area directly accessed using addressable instructions.
Indirect Direct Bank Bank Bank Bank 0000H
Stack
Another Scratchpad area programmer's stack. This area selected using Stack Pointer (SP;81H) SFR. Whenever call interrupt invoked, return address placed Stack. also available programmer variables, etc., since Stack moved there fixed location within designated Stack. Stack Pointer will default reset. user then move needed. convenient location would upper area 7FH) since this only available indirectly. will point last used value. Therefore, next value placed Stack Each PUSH CALL will increment appropriate value. Each will decrement well.
Program Memory
After reset, begins execution from Program Memory location 0000H. selection where Program Memory execution begins made tying internal access, DGND external access. When tied VDD, fetches outside internal Program Memory address occur from external memory. tied DGND, then fetches address external memory. standard internal Program Memory size MSC1210 family members shown Table Refer Accessing External Memory section details using external Program Memory. enabled Boot will appear from address F800H FFFFH.
STANDARD INTERNAL PROGRAM MEMORY SIZE (BYTES)
MODEL NUMBER MSC1210Y5 MSC1210Y4 MSC1210Y3 MSC1210Y2
TABLE MSC1210 Maximum Internal Program Memory Sizes.
ACCESSING EXTERNAL MEMORY
external memory used, configured address data lines. external memory used, configured general-purpose lines through Hardware Configuration Register. enable access external memory bits HCR1 register must When these bits enabled memory accesses both internal external memory will appear ports During data portion cycle internal memory, Port will zero security purposes. Accesses external memory types: accesses external Program Memory accesses external Data Memory. Accesses external Program Memory signal PSEN (program store enable) read strobe. Accesses external Data Memory (alternate functions P3.7 P3.6) strobe memory.
FIGURE Scratchpad Register Addressing. External Program Memory external Data Memory combined desired applying PSEN signals inputs gate using output gate read strobe external Program/Data Memory. Program fetches from external Program Memory always 16-bit address. Accesses external Data Memory either 16-bit address (MOVX DPTR) 8-bit address (MOVX Ri). Port selected external memory (HCR1, used general-purpose I/O. This HCR1)also forces bits P3.6 P3.7 used instead I/O. Port P3.6, P3.7 should written `1'. 8-bit address being used (MOVX RI), contents MPAGE (92H) remain Port pins throughout external memory cycle. This will facilitate paging.
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case, byte address time-multiplexed with data byte Port ADDR/DATA signals CMOS drivers Port Port2, output buffers. Thus, this application Port pins opendrain outputs, require external pull-ups highspeed access. Signal (Address Latch Enable) should used capture address byte into external latch. address byte valid negative transition ALE. Then, write cycle, data byte written appears Port just before activated, remains there until after deactivated. read cycle, incoming byte accepted Port just before read strobe deactivated. function Port Port selected Hardware Configuration Register This only changed during Flash Program mode. There conflict these registers; they will either used general-purpose external memory access. default state Port Port used general-purpose I/O. external memory access attempted when they configured generalpurpose I/O, values Port Port will affected. External Program Memory accessed under conditions: Whenever signal active; Whenever Program Counter (PC) contains number that outside internal Program Memory address range. Port selected external memory, bits Port well P3.6 P3.7, dedicated output function used general-purpose I/O. During external program fetches, Port outputs high byte
Flash Programming Mode
There programming modes: parallel serial. programming mode selected state PSEN signals during power-on reset. Serial programming mode selected with PSEN Parallel programming mode selected with PSEN they both HIGH, MSC1210 will operate normal user mode. Both signals reserved mode defined. Programming mode exited with power-on reset signal normal mode selected. MSC1210 shipped with Flash Memory erased (all 1's). Parallel programming methods typically involve third-party programmer. Serial programming methods typically involve in-system programming. User Application mode allows Flash Program Data Memory programming. actual code Flash programming execute from Flash. That code must execute from Boot internal (Von Neuman) RAM.
MSC1210 PSEL/AddrHi[6:0] P2[7:0] PSEN P1[7:0] Data[3:0] P0[7:0] P3[7:5] P3[4] P3[3] P3[2] Cmd[2:0] Pass AddrLo[7:0]
HOST Flash Programmer
Programming Flash Memory
There four sections Flash Memory programming. configuration bytes. Reset sector (4kB) (not confused with Boot ROM). Program Memory. Data Memory.
Boot
There Boot that controls operation during serial parallel programming. Additionally, Boot routines accessed during user mode enabled. When enabled, Boot routines will located memory addresses F800H-FFFFH during user mode. program mode Boot located first Program Memory.
FIGURE Parallel Programming Configuration.
Hardware Configuration Memory
configuration bytes only written during program mode. bytes accessed through registers CADDR (SFR 93H) CDATA (SFR 94H). configuration bytes control Flash partitioning system control. security set, these bits changed except with Mass Erase command that erases Flash Memory including configuration bytes.
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Hardware Configuration Register (HCR0)-Accessed Using Registers CADDR CDATA.
FADDR EPMA EWDR DFSEL2 DFSEL1 DFSEL0
access this register during normal operation, refer register descriptions CADDR CDATA. EPMA Enable Programming Memory Access (Security Bit). After reset programming modes, Flash Memory read written. Fully Accessible (default) Program Memory Lock. (PML Priority Over RSL) Enable Flash Programming Modes program mode, written UAM. Enable read only program mode, can't written (default). Reset Sector Lock. Enable Reset Sector Writing Enable Read Only Mode Reset Sector (4kB) (default) Enable Boot Rom. Boot code located ROM, confused with Boot Sector located Flash Memory. Disable Internal Boot Enable Internal Boot (default) EWDR Enable Watchdog Reset. Disable Watchdog Reset Enable Watchdog Reset (default) DFSEL Data Flash Memory Size. (see Table bits 000: Reserved 001: 32kB, 16kB, 8kB, Data Flash Memory 010: 16kB, 8kB, Data Flash Memory 011: Data Flash Memory 100: Data Flash Memory 101: Data Flash Memory 110: Data Flash Memory 111: Data Flash Memory (default) reset sector used provide another method Flash Memory programming. This will allow Program Memory updates without changing jumpers in-circuit code updates program development. code this boot sector would then provide monitor programming routines with ability jump into main Flash code when programming finished.
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Hardware Configuration Register (HCR1)
FADDR DBLSEL1 DBLSEL0 ABLSEL1 ABLSEL0 EGP0 EGP23
access this register during normal operation, refer register descriptions CADDR CDATA. DBLSEL Digital Brownout Level Select bits 4.5V 4.2V 2.7V 2.5V (default) ABLSEL Analog Brownout Level Select bits 4.5V 4.2V 2.7V 2.5V (default) EGP0 EGP23 Disable Analog Power-Supply Brownout Detection Enable Analog Brownout Detection Disable Analog Brownout Detection (default) Disable Digital Power-Supply Brownout Detection Enable Digital Brownout Detection Disable Digital Brownout Detection (default) Enable General-Purpose Port Port Used External Memory, P3.6 P3.7 Used Port Used General-Purpose (default) Enable General-Purpose Ports Port Used External Memory, P3.6 P3.7 Used Port Port3 Used General-Purpose (default)
Configuration Memory Programming
Certain functions such Brownout Reset Watchdog Timer controlled hardware configuration bits. These bits nonvolatile only changed through serial parallel programming. Other peripheral control status functions, such configuration timer setup, Flash control controlled through SFRs.
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Definition (Boldface unique MSC1210xx)
ADDRESS REGISTER DPL0 DPH0 DPL1 DPH1 PCON TCON TMOD CKCON EXIF MPAGE CADDR CDATA MCON P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 RESET VALUES
SMOD0 -Timer GATE
-Timer GATE
IDLE
STOP
P1.7 INT5/SCK
P1.6 P1.5 INT4/MISO INT3/MOSI
P1.4 INT2/SS
P1.3 TXD1
P1.2 RXD1
P1.1 T2EX
MXWS P1.0
BPSEL
RAMMAP
SCON0 SBUF0 SPICON SPIDATA SPIRCON SPITCON SPISTART SPIEND PWMCON PWMLOW PWMHI AISTAT BPCON P0DDRL P0DDRH P1DDRL P1DDRH P2DDRL P2DDRH P3DDRL P3DDRH
SM0_0 SCLK2 RXCNT7 RXFLUSH TXCNT7 TXFLUSH P2.7 PWM7 PWM15 ESEC
SM1_0 SCLK1 RXCNT6 TXCNT6
SM2_0 SCLK0 RXCNT5 TXCNT5 CLK_EN
REN_0 FIFO RXCNT4 TXCNT4 DRV_DLY
TB8_0 ORDER RXCNT3 TXCNT3 DRV_EN
RB8_0 MSTR RXCNT2 RXIRQ2 TXCNT2 TXIRQ2
TI_0 CPHA RXCNT1 RXIRQ1 TXCNT1 TXIRQ1
RI_0 CPOL RXCNT0 RXIRQ0 TXCNT0 TXIRQ0
P2.6 PWM6 PWM14 ESUM
P2.5 PPOL PWM5 PWM13 EADC
P2.4 PWMSEL PWM4 PWM12 EMSEC MSEC
P2.3 SPDSEL PWM3 PWM11 PIP.3 ESPIT SPIT
P2.2 TPCNTL2 PWM2 PWM10 PIP.2 ESPIR SPIR
P2.1 TPCNTL1 PWM1 PWM9 PIP.1 EALV ALVD PMSEL
P2.0 TPCNTL0 PWM0 PWM8 PIP.0 EDLVB DLVD
P03H P07H P13H P17H P3.7 P23H P27H P33H P37H
P03L P07L P13L P17L P3.6 P23L P27L P33L P37L
P02H P06H P12H P16H P3.5 P22H P26H P32H P36H
P02L P06L P12L P16L P3.4 P22L P26L P32L P36L
P01H P05H P11H P15H P3.3 P21H P25H P31H P35H
P01L P05L P11L P15L P3.2 P21L P25L P31L P35L
P00H P04H P10H P14H P3.1 P20H P24H P30H P34H
P00L P04L P10L P14L P3.0 P20L P24L P30L P34L
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Definition (Cont.)
ADDRESS REGISTER SCON1 SBUF1 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 RESET VALUES
T2CON RCAP2L RCAP2H EXF2 RCLK TCLK EXEN2
EWUWDT
EWUEX1 C/T2
EWUEX0 CP/RL2
ADMUX EICON ADRESL ADRESM ADRESH ADCON0 ADCON1 ADCON2 ADCON3 SSCON SUMR0 SUMR1 SUMR2 SUMR3 ODAC LVDCON HWPC0 HWPC1 Reserved Reserved Reserved FMCON FTCON PDCON PASEL
INP3 SMOD1
INP2
INP1
INP0
INN3 WDTI
INN2
INN1
INN0
ACC.7 SSCON1
ACC.6 SSCON0
EVREF ACC.5 SCNT2
VREFH ACC.4 SCNT1
EBUF ACC.3 SCNT0
PGA2 CAL2 DR10 ACC.2 SHF2
PGA1 CAL1 ACC.1 SHF1
PGA0 CAL0 ACC.0 SHF0
ALVDIS
ALVD2
ALVD1
ALVD0 EWDI
DLVDIS
DLVD2
DLVD1 DLVD0 MEMORY SIZE
FER3
PGERA FER2
FER1 PSEN2
FRCM FER0 PDPWM PSEN1
FWR3 PDAD PSEN0
BUSY FWR2 PDSDT
FWR1 PDST ALE1
FWR0 PDSPI ALE0
x000 0000B 0000 00xxB
ACLK SRST SECINT MSINT USEC MSECL MSECH HMSEC WDTCON
SECINT6 MSINT6
SECINT5 MSINT5
FREQ4 PWDI SECINT4 MSINT4 FREQ4
FREQ3 SECINT3 MSINT3 FREQ3
FREQ2 SECINT2 MSINT2 FREQ2
FREQ1 SECINT1 MSINT1 FREQ1
FREQ0 RSTREQ SECINT0 MSINT0 FREQ0
EWDT
DWDT
RWDT
WDCNT4
WDCNT3
WDCNT2
WDCNT1
WDCNT0
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Port (P0)
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Reset Value
P0.7-0 bits
Port This port functions multiplexed address/data during external memory access, generalpurpose port when external memory access needed. During external memory cycles, this port will contain address when HIGH, Data when LOW. When used general-purpose I/O, this port drive selected P0DDRL P0DDRH (ACH, ADH). Whether Port used general-purpose external memory access determined Flash Configuration Register (HCR1.1) (see CADDR 93H).
Stack Pointer (SP)
SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 Reset Value
SP.7-0 bits
Stack Pointer. stack pointer identifies location where stack will begin. stack pointer incremented before every PUSH CALL operation decremented after each RET/RETI. This register defaults after reset.
Data Pointer (DPL0)
DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0 Reset Value
DPL.7-0 bits
Data Pointer This register byte standard 8051 16-bit data pointer. DPL0 DPH0 used point non-scratchpad data RAM. current data pointer selected (SFR 86H).
Data Pointer High (DPH0)
DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0 Reset Value
DPH.7-0 bits
Data Pointer High This register high byte standard 8051 16-bit data pointer. DPL0 DPH0 used point non-scratchpad data RAM. current data pointer selected (SFR 86H).
Data Pointer (DPL1)
DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 Reset Value
DPL1.7-0 bits
Data Pointer This register byte auxiliary 16-bit data pointer. When (DPS.0) (SFR 86H) set, DPL1 DPH1 used place DPL0 DPH0 during DPTR operations.
Data Pointer High (DPH1)
DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 Reset Value
DPH1.7-0 Data Pointer High. This register high byte auxiliary 16-bit data pointer. When (DPS.0) bits (SFR 86H) set, DPL1 DPH1 used place DPL0 DPH0 during DPTR operations.
Data Pointer Select (DPS)
Reset Value
Data Pointer Select. This selects active data pointer. Instructions that DPTR will DPL0 DPH0. Instructions that DPTR will DPL1 DPH1.
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Power Control (PCON)
SMOD0 STOP IDLE Reset Value
SMOD0 STOP IDLE
Serial Port Baud Rate Doubler Enable. serial baud rate doubling function Serial Port Serial Port baud rate will standard baud rate. Serial Port baud rate will double that defined baud rate generation equation. General-Purpose User Flag This general-purpose flag software control. General-Purpose User Flag This general-purpose flag software control. Stop Mode Select. Setting this will stop program execution, halt oscillator internal timers, place low-power mode. This will always read Exit with RESET. Idle Mode Select. Setting this will stop program execution leave external interrupt auxiliary interrupts, active. This will always read Exit with (C6H) interrupts.
Timer/Counter Control (TCON)
Reset Value
Timer Overflow Flag. This indicates when Timer overflows maximum count defined current mode. This cleared software automatically cleared when vectors Timer interrupt service routine. Timer overflow been detected. Timer overflowed maximum count. Timer Control. This enables/disables operation Timer Halting this timer will preserve current count TH1, TL1. Timer halted. Timer enabled. Timer Overflow Flag. This indicates when Timer overflows maximum count defined current mode. This cleared software automatically cleared when vectors Timer interrupt service routine. Timer overflow been detected. Timer overflowed maximum count. Timer Control. This enables/disables operation Timer Halting this timer will preserve current count TH0, TL0. Timer halted. Timer enabled. Interrupt Edge Detect. This when edge/level type defined detected. this will remain until cleared software start External Interrupt service routine. this will inversely reflect state INT1 pin. Interrupt Type Select. This selects whether INT1 will detect edge level triggered interrupts. INT1 level triggered. INT1 edge triggered. Interrupt Edge Detect. This when edge/level type defined detected. this will remain until cleared software start External Interrupt service routine. this will inversely reflect state INT0 pin. Interrupt Type Select. This selects whether INT0 will detect edge level triggered interrupts. INT0 level triggered. INT0 edge triggered.
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Timer Mode Control (TMOD)
TIMER TIMER Reset Value
GATE
GATE
GATE bits
Timer Gate Control. This enables/disables ability Timer increment. Timer will clock when regardless state INT1. Timer will clock only when INT1 Timer Counter/Timer Select. Timer incremented internal clocks. Timer incremented pulses when (TCON.6, 88H) Timer Mode Select. These bits select operating mode Timer
MODE Mode Mode Mode Mode 8-bit counter with 5-bit prescale. bits. 8-bit counter with auto reload. Timer halted, holds count.
GATE bits
Timer Gate Control. This enables/disables ability Timer increment. Timer will clock when regardless state INT0 (software control). Timer will clock only when INT0 (hardware control). Timer Counter/Timer Select. Timer incremented internal clocks. Timer incremented pulses when (TCON.4, 88H) Timer Mode Select. These bits select operating mode Timer
MODE Mode Mode Mode Mode 8-bit counter with 5-bit prescale. bits. 8-bit counter with auto reload. Timer halted, holds count.
Timer (TL0)
TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 Reset Value
TL0.7-0 bits
Timer LSB. This register contains least significant byte Timer
Timer (TL1)
TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 Reset Value
TL1.7-0 bits
Timer LSB. This register contains least significant byte Timer
Timer (TH0)
TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 Reset Value
TH0.7-0 bits
Timer MSB. This register contains most significant byte Timer
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Timer (TH1)
TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 Reset Value
TH1.7-0 bits
Timer MSB. This register contains most significant byte Timer
Clock Control (CKCON)
Reset Value
Timer Clock Select. This controls division system clock that drives Timer This effect when timer baud rate generator clock output modes. Clearing this maintains 80C32 compatibility. This effect instruction cycle timing. Timer uses divide crystal frequency. Timer uses divide crystal frequency. Timer Clock Select. This controls division system clock that drives Timer Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide crystal frequency. Timer uses divide crystal frequency. Timer Clock Select. This controls division system clock that drives Timer Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide crystal frequency. Timer uses divide crystal frequency. Stretch MOVX Select 2-0. These bits select time which external MOVX cycles stretched. This allows slower memory peripherals accessed without using ports manual software intervention. strobe will stretched specified interval, which will transparent software except increased time execute MOVX instruction. internal MOVX instructions devices containing MOVX SRAM performed instruction cycle rate.
STROBE WIDTH (SYS CLKs) STROBE WIDTH (µs) 12MHz 0.167 0.333 0.667 1.000 1.333 1.667 2.000 2.333
MD2, MD1, bits
STRETCH VALUE
MOVX DURATION Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Cycles Cycles (default) Cycles Cycles Cycles Cycles Cycles Cycles
Memory Write Select (MWS)
MXWS Reset Value
MXWS
MOVX Write Select. This allows writing internal Flash program memory. writes allowed internal Flash program memory. Writing allowed internal Flash program memory, unless (HCR0)
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Port (P1)
P1.7 INT5/SCK P1.6 INT4/MISO P1.5 INT3/MOSI P1.4 INT2/SS P1.3 TXD1 P1.2 RXD1 P1.1 T2EX P1.0 Reset Value
P1.7-0 bits
General-Purpose Port This register functions general-purpose port. addition, pins have alternative function listed below. Each functions controlled several other SFRs. associated Port latch must contain logic before used alternate function capacity. alternate function, appropriate mode P1DDRL (SFR AEH), P1DDRH (SFR AFH). External Interrupt falling edge this will cause external interrupt enabled. Clock. master clock data transfers. External Interrupt rising edge this will cause external interrupt enabled. Master Slave Out. data transfers, this receives data master transmits data from slave. External Interrupt falling edge this will cause external interrupt enabled. Master Slave data transfers, this transmits master data receives slave data. External Interrupt falling edge this will cause external interrupt enabled. Slave Select. During operation, this provides select signal slave device. Serial Port Transmit. This transmits serial Port data serial port modes emits synchronizing clock serial port mode Serial Port Receive. This receives serial Port data serial port modes bidirectional data transfer serial port mode Timer Capture/Reload Trigger. transition this will cause value registers transferred into capture registers enabled EXEN2 (T2CON.3, C8H). When auto-reload mode, transition this will reload Timer registers with value RCAP2L RCAP2H enabled EXEN2 (T2CON.3, C8H). Time External Input. transition this will cause Timer increment decrement depending timer configuration.
INT5/SCK INT4/MISO INT3/MOSI INT2/SS TXD1 RXD1 T2EX
External Interrupt Flag (EXIF)
Reset Value
External Interrupt Flag. This will when falling edge detected INT5. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when rising edge detected INT4. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when falling edge detected INT3. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when rising edge detected INT2. This must cleared manually software. Setting this software will cause interrupt enabled.
Memory Page (MPAGE)
Reset Value
MPAGE bits
8051 uses Port upper bits external data memory access MOVX MOVX instructions. MSC1210 uses register MPAGE instead Port access external data memory using MOVX MOVX instructions, user should preload upper byte address into MPAGE (versus preloading into standard 8051).
Configuration Address Register (CADDR)
Reset Value
CADDR bits
Configuration Address Register. This register supplies address reading bytes bytes Flash Configuration Memory. WARNING: this register written while executing from Flash Memory, CDATA register will incorrect.
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Configuration Data Register (CDATA)
Reset Value
CDATA bits
Configuration Data Register. This register will contain data bytes Flash Configuration Memory that located last written address CADDR register. This read-only register.
Memory Control (MCON)
BPSEL Reserved Reserved RAMMAP Reset Value
BPSEL RAMMAP
Breakpoint Address Selection Write: Select Breakpoint registers: Read: Provides Breakpoint register that created last interrupt: Memory data RAM. Address 0000H-03FFH (default) (Data Memory) Program Mode, Address 7C00H-7FFFH User Mode, Address 8400H-87FFH (Data Program Memory)
RAMMAP USER 0000H-3FFFH 8400H-87FFH PROG 0000H-3FFFH 7C00H-7FFFH
Serial Port Control (SCON0)
SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 Reset Value
SM0-2 bits
Serial Port Mode. These bits control mode serial Port Modes have start stop addition data bits.
MODE FUNCTION Synchronous Synchronous Asynchronous Asynchronous Asynchronous with Multiprocessor Communication Asynchronous Asynchronous with Multiprocessor Communication LENGTH bits bits bits bits bits bits bits PERIOD pCLK(1) pCLK(1) Timer Baud Rate Equation pCLK(1) pCLK(1) pCLK(1) pCLK(1) (SMOD (SMOD (SMOD (SMOD
Timer Baud Rate Equation Timer Baud Rate Equation
NOTE: pCLK will equal tCLK, except that pCLK will stop IDLE.
REN_0 TB8_0 RB8_0 TI_0 RI_0
Receive Enable. This enables/disables serial Port received shift register. Serial Port reception disabled. Serial Port received enabled (modes Initiate synchronous reception (mode Transmission State. This defines state transmission serial Port modes Received State. This identifies state reception received data serial Port modes serial port mode when SM2_0 RB8_0 state stop bit. RB8_0 used mode Transmitter Interrupt Flag. This indicates that data serial Port buffer been completely shifted out. serial port mode TI_0 data bit. other modes, this last data bit. This must manually cleared software. Receiver Interrupt Flag. This indicates that byte data been received serial Port buffer. serial port mode RI_0 bit. serial port mode RI_0 after last sample incoming stop subject state SM2_0. modes RI_0 after last sample RB8_0. This must manually cleared software.
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Serial Data Buffer (SBUF0)
Reset Value
SBUF0 bits
Serial Data Buffer Data Serial Port read from written this location. serial transmit receive buffers separate registers, both addressed this location.
Control (SPICON). Change resets interface, counters, pointers.
SCLK2 SCLK1 SCLK0 FIFO ORDER MSTR CPHA CPOL Reset Value
SCLK bits
SCLK Selection. Selection tCLK divider generation SCLK Master mode.
SCLK2 SCLK1 SCLK0 SCLK PERIOD tCLK/2 tCLK/4 tCLK/8 tCLK/16 tCLK/32 tCLK/64 tCLK/128 tCLK/256
FIFO ORDER MSTR CPHA CPOL
Enable FIFO on-chip indirect memory. Both transmit receive double buffers Circular FIFO used transmit receive bytes Order Transmit Receive. Most Significant Bits First Least Significant Bits First Master Mode. Slave Mode Master Mode Serial Clock Phase Control. Valid data starting from half SCLK period before first edge SCLK Valid data starting from first edge SCLK Serial Clock Polarity. SCLK idle logic SCLK idle logic HIGH
Data Register (SPIDATA)
Reset Value
SPIDATA bits
Data Register. Data read from written this location. transmit receive buffers separate registers, both addressed this location.
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Receive Control Register (SPIRCON)
RXCNT7 RXFLUSH RXCNT6 RXCNT5 RXCNT4 RXCNT3 RXCNT2 RXIRQ2 RXCNT1 RXIRQ1 RXCNT0 RXIRQ0 Reset Value
RxCNT bits RXFLUSH RxIRQ bits
Receive Counter. Read only bits which read number bytes receive buffer 128). Flush Receive FIFO. Write only. Action Receive Buffer Empty Read Level. Write only.
Generate Generate Generate Generate Generate Generate Generate Generate when when when when when when when when Receive Receive Receive Receive Receive Receive Receive Receive Count Count Count Count Count Count Count Count more. more. more. more. more. more. more. more.
Transmit Control Register (SPITCON)
TXCNT7 TXFLUSH TXCNT6 TXCNT5 CLK_EN TXCNT4 DRV_DLY TXCNT3 DRV_EN TXCNT2 TXIRQ2 TXCNT1 TXIRQ1 TXCNT0 TXIRQ0 Reset Value
TxCNT bits TXFLUSH CLK_EN DRV_DLY DRV_EN
Transmit Counter. Read only bits which read number bytes transmit buffer 128). Flush Transmit FIFO. This write only. When set, transmit pointer equal FIFO Output pointer. This read operation. SCLK Driver Enable. Disable SCLK Driver (Master Mode) Enable SCLK Driver (Master Mode) Drive Delay. Drive Enable.
DRV_DLY DRV_EN MOSI MISO OUTPUT CONTROL Tristate Immediately Drive Immediately Tristate After Current Byte Transfer Drive After Current Byte Transfer
TxIRQ bits
Transmit Level. Write only bits.
Generate Generate Generate Generate Generate Generate Generate Generate when when when when when when when when Transmit Transmit Transmit Transmit Transmit Transmit Transmit Transmit count count count count count count count count less. less. less. less. less. less. less. less.
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Buffer Start Address (SPISTART)
Reset Value
SPISTART bits SPITP bits
FIFO Start Address. Write only. This specifies start address data buffer. This circular FIFO that located bytes indirect RAM. FIFO starts this address ends address specified SPIEND. Must less than SPIEND. Writing clears transmit receive counters. Transmit Pointer. Read Only. This FIFO address transmissions. This where next byte will written into FIFO buffer. This pointer increments after each write Data register unless that would make equal Receive pointer.
Buffer Address (SPIEND)
Reset Value
SPIEND bits SPIRP bits
FIFO Address. Write only. This specifies address data FIFO. This circular buffer that located bytes indirect RAM. buffer starts SPISTRT ends this address. Receive Pointer. Read Only. This FIFO address received bytes. This location next byte read from FIFO. This increments with each read from Data register until RxCNT zero.
Port (P2)
Reset Value
bits
Port This port functions address during external memory access, general-purpose port. During external memory cycles, this port will contain address. Whether Port used generalpurpose external memory access determined Flash Configuration Register (HCR1.0).
Control (PWMCON)
PPOL PWMSEL SPDSEL TPCNTL.2 TPCNTL.1 TPCNTL.0 Reset Value
PPOL PWMSEL SPDSEL TPCNTL bits
Period Polarity. Specifies starting level pulse. Period. Duty register programs period. Period. Duty register programs period. Register Select. Select which 16-bit register accessed PWMLOW/PWMHIGH. Period Duty Speed Select. 1MHz (ONEUSEC Clock) SYSCLK Tone Generator/Pulse Width Modulation Control.
TPCNTL.2 TPCNTL.1 TPCNTL.0 MODE Disable (default) TONE-Square TONE-Staircase
Tone (TONELOW) /PWM (PWMLOW)
TDIV7 PWM7 TDIV6 PWM6 TDIV5 PWM5 TDIV4 PWM4 TDIV3 PWM3 TDIV2 PWM2 TDIV1 PWM1 TDIV0 PWM0 Reset Value
TDIVxx bits PWMLOW bits
Tone Divisor. order bits that define half-time period. staircase mode output high impedance last this period. Pulse Width Modulator Bits. These bits least significant bits register.
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Tone High (TONEHI)/PWM High (PWMHI)
TDIV15 PWM15 TDIV14 PWM14 TDIV13 PWM13 TDIV12 PWM12 TDIV11 PWM11 TDIV10 PWM10 TDIV09 PWM9 TDIV08 PWM8 Reset Value
TDIVxx bits PWMHI bits
Tone Divisor. high order bits that define half time period. staircase mode output high impedance last this period. Pulse Width Modulator High Bits. These bits high order bits register.
Pending Auxiliary Interrupt (PAI)
PAI3 PAI2 PAI1 PAI0 Reset Value
bits
Pending Auxiliary Interrupt Register. results this register used index vector appropriate interrupt routine. these interrupts vector through address 0033H.
PAI3 PAI2 PAI1 PAI0 AUXILIARY INTERRUPT STATUS Pending Auxiliary Digital Voltage Pending Analog Voltage Pending Receive Pending Transmit Pending Millisecond System Timer Pending Analog Digital Conversion Pending Accumulator Pending Second System Timer Pending
Auxiliary Interrupt Enable (AIE)
ESEC ESUM EADC EMSEC ESPIT ESPIR EALV EDLVB Reset Value
Interrupts enabled EICON.4 (SFR D8H). other interrupts controlled registers. ESEC ESUM EADC EMSEC ESPIT ESPIR EALV EDLVB Seconds Timer Interrupt (lowest priority auxialiary interrupt). Write: mask this interrupt masked, enabled. Read: Current value Seconds Timer Interrupt before masking. Summation Interrupt Bit. Write: mask this interrupt masked, enabled. Read: Current value Summation Interrupt before masking. Interrupt Bit. Write: mask this interrupt masked, enabled. Read: Current value Interrupt before masking. Millisecond System Timer Interrupt Bit. Write: mask this interrupt masked, enabled. Read: Current value Millisecond System Timer Interrupt before masking. Transmit Interrupt Bit. Write: mask this interrupt masked, enabled. Read: Current value Transmit Interrupt before masking. Receive Interrupt Bit. Write: mask this interrupt masked, enabled. Read: Current value Receive Interrupt before masking. Analog Voltage Interrupt Bit. Write: mask this interrupt masked, enabled. Read: Current value Analog Voltage Interrupt before masking. Digital Voltage Breakpoint Interrupt (highest priority auxiliary interrupt). Write: mask this interrupt masked, enabled. Read: Current value Digital Voltage Breakpoint Interrupt before masking.
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Auxiliary Interrupt Status Register (AISTAT)
MSEC SPIT SPIR ALVD DLVD Reset Value
MSEC SPIT SPIR ALVD DLVD
Second System Timer Interrupt Status Flag (lowest priority AI). interrupt inactive masked. Interrupt active. Summation Register Interrupt Status Flag. interrupt inactive masked active, inactive reading lowest byte Summation register). interrupt active. Interrupt Status Flag. interrupt inactive masked active, inactive reading lowest byte Data Output Register). interrupt active active data will written Data Output Register). Millisecond System Timer Interrupt Status Flag. MSEC interrupt inactive masked. MSEC interrupt active. Transmit Interrupt Status Flag. transmit interrupt inactive masked. transmit interrupt active. Receive Interrupt Status Flag. receive interrupt inactive masked. receive interrupt active. Analog Voltage Detect Interrupt Status Flag. ALVD interrupt inactive masked. ALVD interrupt active. Digital Voltage Detect Breakpoint Interrupt Status Flag (highest priority AI). DLVD interrupt inactive masked. DLVD interrupt active.
Interrupt Enable (IE)
Reset Value
Global Interrupt Enable. This controls global masking interrupts except those (SFR A6H). Disable interrupt sources. This overrides individual interrupt mask settings this register. Enable individual interrupt masks. Individual interrupts this register will occur enabled. Enable Serial Port Interrupt. This controls masking serial Port interrupt. Disable serial Port interrupts. Enable interrupt requests generated RI_1 (SCON1.0, C0H) TI_1 (SCON1.1, C0H) flags. Enable Timer Interrupt. This controls masking Timer interrupt. Disable Timer interrupts. Enable interrupt requests generated flag (T2CON.7, C8H). Enable Serial port interrupt. This controls masking serial Port interrupt. Disable serial Port interrupts. Enable interrupt requests generated RI_0 (SCON0.0, 98H) TI_0 (SCON0.1, 98H) flags.
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Enable Timer Interrupt. This controls masking Timer interrupt. Disable Timer interrupt. Enable interrupt requests generated flag (TCON.7, 88H). Enable External Interrupt This controls masking external interrupt Disable external interrupt Enable interrupt requests generated INT1 pin. Enable Timer Interrupt. This controls masking Timer interrupt. Disable Timer interrupts. Enable interrupt requests generated flag (TCON.5, 88H). Enable External Interrupt This controls masking external interrupt Disable external interrupt Enable interrupt requests generated INT0 pin.
Breakpoint Control (BPCON)
PMSEL Reset Value
Writing register sets breakpoint condition specified MCON, BPL, BPH. Breakpoint Interrupt. This indicates that break condition been recognized hardware breakpoint register(s). Read: Status Breakpoint Interrupt. Will indicate breakpoint match breakpoint registers. Write: effect. Clear Breakpoint breakpoint register selected MCON (SFR 95H). Program Memory Select. Write this select memory address breakpoints register selected MCON (SFR 95H). Break address data memory. Break address program memory. Enable Breakpoint. This enables this breakpoint register. Address breakpoint register selected MCON (SFR 95H). Breakpoint disabled. Breakpoint enabled.
PMSEL
Breakpoint (BPL) Address Register Selected MCON (95H)
BPL.7 BPL.6 BPL.5 BPL.4 BPL.3 BPL.2 BPL.1 BPL.0 Reset Value
BPL.7-0 bits
Breakpoint Address. bits breakpoint address.
Breakpoint High Address (BPH) Address Register Selected MCON (95H)
BPH.7 BPH.6 BPH.5 BPH.4 BPH.3 BPH.2 BPH.1 BPH.0 Reset Value
BPH.7-0 bits
Breakpoint High Address. high bits breakpoint address.
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Port Data Direction Register (P0DDRL)
P03H P03L P02H P02L P01H P01L P00H P00L Reset Value
P0.3 bits
Port control.
P03H P03L Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.2 bits
Port control.
P02H P02L Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.1 bits
Port control.
P01H P01L Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.0 bits
Port control.
P00H P00L Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
Port Data Direction High Register (P0DDRH)
P07H P07L P06H P06L P05H P05L P04H P04L Reset Value
P0.7 bits
Port control.
P07H P07L Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.6 bits
Port control.
P06H P06L Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.5 bits
Port control.
P05H P05L Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
P0.4 bits
Port control.
P04H P04L Standard 8051(Pull-Up) CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
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Port Data Direction Register (P1DDRL)
P13H P13L P12H P12L P11H P11L P10H P10L Reset Value
P1.3 bits
Port control.
P13H P13L Standard 8051 CMOS Output Open Drain Output Input
P1.2 bits
Port control.
P12H P12L Standard 8051 CMOS Output Open Drain Output Input
P1.1 bits
Port control.
P11H P11L Standard 8051 CMOS Output Open Drain Output Input
P1.0 bits
Port control.
P10H P10L Standard 8051 CMOS Output Open Drain Output Input
Port Data Direction High Register (P1DDRH)
P17H P17L P16H P16L P15H P15L P14H P14L Reset Value
P1.7 bits
Port control.
P17H P17L Standard 8051 CMOS Output Open Drain Output Input
P1.6 bits
Port control.
P16H P16L Standard 8051 CMOS Output Open Drain Output Input
P1.5 bits
Port control.
P15H P15L Standard 8051 CMOS Output Open Drain Output Input
P1.4 bits
Port control.
P14H P14L Standard 8051 CMOS Output Open Drain Output Input
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Port (P3)
P3.7 P3.6 P3.5 P3.4 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 Reset Value
P3.7-0 bits INT1 INT0 TXD0 RXD0
General-Purpose Port This register functions general-purpose port. addition, pins have alternative function listed below. Each functions controlled several other SFRs. associated Port latch must contain logic before used alternate function capacity. External Data Memory Read Strobe. This provides active read strobe external memory device. Port Port selected external memory HCR1 register, this function will enabled even written this latch bit. When external memory selected, settings P3DRRH ignored. External Data Memory Write Strobe. This provides active write strobe external memory device. Port Port selected external memory HCR1 register, this function will enabled even written this latch bit. When external memory selected, settings P3DRRH ignored. Timer/Counter External Input. transition this will increment Timer Timer/Counter External Input. transition this will increment Timer External Interrupt falling edge/low level this will cause external interrupt enabled. External Interrupt falling edge/low level this will cause external interrupt enabled. Serial Port Transmit. This transmits serial Port data serial port modes emits synchronizing clock serial port mode Serial Port Receive. This receives serial Port data serial port modes bidirectional data transfer serial port mode
Port Data Direction Register (P2DDRL)
P23H P23L P22H P22L P21H P21L P20H P20L Reset Value
P2.3 bits
Port control.
P23H P23L Standard 8051 CMOS Output Open Drain Output Input
P2.2 bits
Port control.
P22H P22L Standard 8051 CMOS Output Open Drain Output Input
P2.1 bits
Port control.
P21H P21L Standard 8051 CMOS Output Open Drain Output Input
P2.0 bits
Port control.
P20H P20L Standard 8051 CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
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Port Data Direction High Register (P2DDRH)
P27H P27L P26H P26L P25H P25L P24H P24L Reset Value
P2.7 bits
Port control.
P27H P27L Standard 8051 CMOS Output Open Drain Output Input
P2.6 bits
Port control.
P26H P26L Standard 8051 CMOS Output Open Drain Output Input
P2.5 bits
Port control.
P25H P25L Standard 8051 CMOS Output Open Drain Output Input
P2.4 bits
Port control.
P24H P24L Standard 8051 CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
Port Data Direction Register (P3DDRL)
P33H P33L P32H P32L P31H P31L P30H P30L Reset Value
P3.3 bits
Port control.
P33H P33L Standard 8051 CMOS Output Open Drain Output Input
P3.2 bits
Port control.
P32H P32L Standard 8051 CMOS Output Open Drain Output Input
P3.1 bits
Port control.
P31H P31L Standard 8051 CMOS Output Open Drain Output Input
P3.0 bits
Port control.
P30H P30L Standard 8051 CMOS Output Open Drain Output Input
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Port Data Direction High Register (P3DDRH)
P37H P37L P36H P36L P35H P35L P34H P34L Reset Value
P3.7 bits
Port control.
P37H P37L Standard 8051 CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
P3.6 bits
Port control.
P36H P36L Standard 8051 CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
P3.5 bits
Port control.
P35H P35L Standard 8051 CMOS Output Open Drain Output Input
P3.4 bits
Port control.
P34H P34L Standard 8051 CMOS Output Open Drain Output Input
Interrupt Priority (IP)
Reset Value
Serial Port Interrupt. This controls priority serial Port interrupt. Serial Port priority determined natural priority order. Serial Port high priority interrupt. Timer Interrupt. This controls priority Timer interrupt. Timer priority determined natural priority order. Timer priority high priority interrupt. Serial Port Interrupt. This controls priority serial Port interrupt. Serial Port priority determined natural priority order. Serial Port high priority interrupt. Timer Interrupt. This controls priority Timer interrupt. Timer priority determined natural priority order. Timer priority high priority interrupt. External Interrupt This controls priority external interrupt External interrupt priority determined natural priority order. External interrupt high priority interrupt. Timer Interrupt. This controls priority Timer interrupt. Timer priority determined natural priority order. Timer priority high priority interrupt. External Interrupt This controls priority external interrupt External interrupt priority determined natural priority order. External interrupt high priority interrupt.
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Serial Port Control (SCON1)
SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 Reset Value
SM0-2 bits
Serial Port Mode. These bits control mode serial Port Modes have start stop addition data bits.
MODE FUNCTION Synchronous Synchronous Asynchronous Asynchronous Asynchronous with Multiprocessor Communication Asynchronous Asynchronous with Multiprocessor Communication LENGTH bits bits bits bits bits bits bits PERIOD pCLK(1) pCLK(1) Timer Baud Rate Equation pCLK(1) pCLK(1) pCLK(1) pCLK(1) (SMOD (SMOD (SMOD (SMOD
Timer Baud Rate Equation Timer Baud Rate Equation
NOTE: pCLK will equal tCLK, except that pCLK will stop IDLE.
REN_1 TB8_1 RB8_1 TI_1 RI_1
Receive Enable. This enables/disables serial Port received shift register. Serial Port reception disabled. Serial Port received enabled (modes Initiate synchronous reception (mode Transmission State. This defines state transmission serial Port modes Received State. This identifies state reception received data serial Port modes serial port mode when SM2_1 RB8_1 state stop bit. RB8_1 used mode Transmitter Interrupt Flag. This indicates that data serial Port buffer been completely shifted out. serial port mode TI_1 data bit. other modes, this last data bit. This must cleared software transmit next byte. Receiver Interrupt Flag. This indicates that byte data been received serial Port buffer. serial port mode RI_1 bit. serial port mode RI_1 after last sample incoming stop subject state SM2_1. modes RI_1 after last sample RB8_1. This must cleared software receive next byte.
Serial Data Buffer (SBUF1)
Reset Value
SBUF1.7-0 Serial Data Buffer Data serial Port read from written this location. serial transmit receive bits buffers separate registers, both addressed this location.
Enable Wake (EWU) Waking from IDLE Mode
EWUWDT EWUEX1 EWUEX0 Reset Value
EWUWDT EWUEX1 EWUEX0
Enable Wake External Wake using external interrupt source don't wake external interrupt source wake external interrupt source Enable Wake External Wake using external interrupt source don't wake external interrupt source wake external interrupt source Enable Wake Watchdog Timer. Wake using watchdog timer interrupt. don't wake watchdog timer interrupt. wake watchdog timer interrupt.
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Timer Control (T2CON)
EXF2 RCLK TCLK EXEN2 C/T2 CP/RL2 Reset Value
EXF2 RCLK
Timer Overflow Flag. This flag will when Timer overflows from FFFFH. must cleared software. will only RCLK TCLK both cleared Writing forces Timer interrupt enabled. Timer External Flag. negative transition T2EX (P1.1) will cause this flag based EXEN2 (T2CON.3) bit. negative transition, this flag must cleared software. Setting this software will force timer interrupt enabled. Receive Clock Flag. This determines serial Port timebase when receiving data serial modes Timer overflow used determine receiver baud rate serial Port Timer overflow used determine receiver baud rate serial Port Setting this will force Timer into baud rate generation mode. timer will operate from divide external clock. Transmit Clock Flag. This determines serial Port timerbase when transmitting data serial modes Timer overflow used determine transmitter baud rate serial Port Timer overflow used determine transmitter baud rate serial Port Setting this will force Timer into baud rate generation mode. timer will operate from divide external clock. Timer External Enable. This enables capture/reload function T2EX Timer generating baud rates serial port. Timer will ignore external events T2EX. Timer will capture reload value negative transition detected T2EX pin. Timer Control. This enables/disables operation Timer Halting this timer will preserve current count TH2, TL2. Timer halted. Timer enabled. Counter/Timer Select. This determines whether Timer will function timer counter. Independent this bit, Timer runs clocks tick when used baud rate generator mode. Timer functions timer. speed Timer determined (CKCON.5). Timer will count negative transitions (P1.0). Capture/Reload Select. This determines whether capture reload function will used Timer either RCLK TCLK set, this will function timer will function auto-reload mode following each overflow. Auto-reloads will occur when Timer overflows falling edge detected T2EX EXEN2 Timer captures will occur when falling edge detected T2EX EXEN2
TCLK
EXEN2
C/T2
CP/RL2
Timer Capture (RCAP2L)
Reset Value
RCAP2L bits
Timer Capture LSB. This register used capture value when Timer configured capture mode. RCAP2L also used 16-bit reload value when Timer configured auto-reload mode.
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Timer Capture (RCAP2H)
Reset Value
RCAP2H bits
Timer Capture MSB. This register used capture value when Timer configured capture mode. RCAP2H also used 16-bit reload value when Timer configured auto-reload mode.
Timer (TL2)
Reset Value
bits
Timer LSB. This register contains least significant byte Timer
Timer (TH2)
Reset Value
bits
Timer MSB. This register contains most significant byte Timer
Program Status Word (PSW)
Reset Value
RS1, bits
Carry Flag. This when last arithmetic operation resulted carry (during addition) borrow (during subtraction). Otherwise cleared arithmetic operations. Auxiliary Carry Flag. This last arithmetic operation resulted carry into (during addition), borrow (during substraction) from high order nibble. Otherwise cleared arithmetic operations. User Flag This bit-adressable, general-purpose flag software control. Register Bank Select 1-0. These bits select which register bank addressed during register accesses.
REGISTER BANK ADDRESS 00H-07H 08H-0FH 10H-17H 18H-1FH
Overflow Flag. This last arithmetic operation resulted carry (addition), borrow (subtraction), overflow (multiply divide). Otherwise cleared arithmetic operations. User Flag This bit-addressable, general-purpose flag software control. Parity Flag. This modulo-2 bits accumulator (odd parity); cleared even parity.
Offset Calibration Register Byte (OCL)
Reset Value
bits
Offset Calibration Register Byte. This byte word that contains offset calibration. value which written this location will offset calibration value.
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Offset Calibration Register Middle Byte (OCM)
Reset Value
OCRM bits
Offset Calibration Register Middle Byte. This middle byte 24-bit word that contains offset calibration. value which written this location will offset calibration value.
Offset Calibration Register High Byte (OCH)
Reset Value
OCRH bits
Offset Calibration Register High Byte. This high byte 24-bit word that contains offset calibration. value which written this location will offset calibration value.
Gain Calibration Register Byte (GCL)
Reset Value
GCRL bits
Gain Calibration Register Byte. This byte 24-bit word that contains gain calibration. value which written this location will gain calibration value.
Gain Calibration Register Middle Byte (GCM)
Reset Value
GCRM bits
Gain Calibration Register Middle Byte. This middle byte 24-bit word that contains gain calibration. value which written this location will gain calibration value.
Gain Calibration Register High Byte (GCH)
Reset Value
GCRH bits
Gain Calibration Register High Byte. This high byte 24-bit word that contains gain calibration. value which written this location will gain calibration value.
Multiplexer Register (ADMUX)
INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 Reset Value
INP3-0 bits
Input Multiplexer Positive Channel. This selects positive signal input.
INP3 INP2 INP1 INP0 POSITIVE INPUT AIN0 (default) AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM Temperature Sensor (Requires ADMUX FFH)
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INN3-0 bits
Input Multiplexer Negative Channel. This selects negative signal input.
INN3 INN2 INN1 INN0 NEGATIVE INPUT AIN0 AIN1 (default) AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM Temperature Sensor (Requires ADMUX FFH)
Enable Interrupt Control (EICON)
SMOD1 WDTI Reset Value
SMOD1
Serial Port Mode. When this serial baud rate Port will doubled. Standard baud rate Port (default). Double baud rate Port Enable Auxiliary Interrupt. Auxiliary Interrupt accesses nine different interrupts which masked identified registers (SFR A5H), (SFR A6H), AISTAT (SFR A7H). Auxiliary Interrupt disabled (default). Auxiliary Interrupt enabled. Auxiliary Interrupt Flag. must cleared software before exiting interrupt service routine, after source interrupt cleared. Otherwise, interrupt occurs again. Setting software generates Auxiliary Interrupt, enabled. Auxiliary Interrupt detected (default). Auxiliary Interrupt detected. Watchdog Timer Interrupt Flag. WDTI must cleared software before exiting interrupt service routine. Otherwise, interrupt occurs again. Setting WDTI software generates watchdog time interrupt, enabled. Watchdog timer generate interrupt reset. interrupt available only reset action disabled HCR0. Watchdog Timer Interrupt Detected (default). Watchdog Timer Interrupt Detected.
WDTI
Results Register Byte (ADRESL)
Reset Value
ADRESL bits
Results Byte. This byte word that contains Converter Results. Reading from this register resets interrupt.
Results Register Middle Byte (ADRESM)
Reset Value
ADRESM bits
Results Middle Byte. This middle byte word that contains Converter Results.
Results Register High Byte (ADRESH)
Reset Value
ADRESH bits
Results High Byte. This high byte word that contains Converter Results.
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Control Register (ADCON0)
EVREF VREFH EBUF PGA2 PGA1 PGA0 Reset Value
Burnout Detect. When enabled this connects positive current source positive channel negative current source negative channel. channel open circuit then results will full-scale. Burnout Current Sources (default). Burnout Current Sources Enable Internal Voltage Reference. internal voltage reference used, should turned save power reduce noise. Internal Voltage Reference Off. Internal Voltage Reference (default). Voltage Reference High Select. internal voltage reference selected 2.5V 1.25V. REFOUT 1.25V. REFOUT 2.5V (default). Enable Buffer. Enable input buffer provide higher input impedance limits input voltage range dissipates higher power. Buffer disabled (default). Buffer enabled. Programmable Gain Amplifier. Sets gain from 128.
PGA2 PGA1 PGA0 GAIN (default)
EVREF
VREFH EBUF
PGA2-0 bits
Control Register (ADCON1)
CAL2 CAL1 CAL0 Reset Value x000 0000B
Polarity. Polarity results Summation register. Bipolar. Unipolar. Resolution (LSB size) resolution Bipolar.
ANALOG INPUT +FSR ZERO -FSR +FSR ZERO -FSR DIGITAL OUTPUT 0x7FFFFF 0x000000 0x800000 0xFFFFFF 0x000000 0x000000
SM1-0 bits
Settling Mode. Selects type filter auto select which defines digital filter settling characteristics.
SETTLING MODE Auto Quick Convert Sinc2 Filter Sinc3 Filter
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CAL2-0 bits
Calibration Mode Control Bits.
CAL2 CAL1 CAL0 CALIBRATION MODE Calibration (default) Self Calibration, Offset Gain Self Calibration, Offset Only Self Calibration, Gain Only System Calibration, Offset Only System Calibration, Gain Only Reserved Reserved
Read Value-000B.
Control Register (ADCON2)
Reset Value
DR7-0 bits
Decimation Ratio LSB.
Control Register (ADCON3)
DR10 Reset Value
DR10-8 bits
Decimation Ratio Most Significant Bits. output data rate (ACLK 64/Decimation Ratio.
Accumulator ACC)
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Reset Value
ACC.7-0 bits
Accumulator. This register serves accumulator arithmetic logic operations.
Summation/Shifter Control (SSCON)
SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 Reset Value
Summation register powered down when powered down. zeroes written this register 32-bit SUMR3-0 registers will cleared. Summation registers will sign extend Bipolar selected ADCON1. SSCON1-0 Summation/Shift Control. bits SOURCE SSCON1 SSCON0 MODE
Values written registers accumulated when SUMR0 value written. Summation register Enabled. Source ADC, summation count working. Shift Enabled. Summation register shifted Count bits. takes four system clocks execute. Accumulate Shift Enable. Values accumulated Count times then shifted Count.
SCNT2-0 bits
Summation Count. When summation complete interrupt will generated unless masked. Reading SUMR0 register clears interrupt.
SCNT2 SCNT1 SCNT0 SUMMATION COUNT
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SHF2-0 bits
Shift Count.
SHF2 SHF1 SHF0 SHIFT DIVIDE
Summation Register (SUMR0)
Reset Value
SUMR0 bits
Summation Register This least significant byte 32-bit summation register bits Write: will cause values SUMR3-0 added summation register. Read: will clear Summation Count Interrupt.
Summation Register (SUMR1)
Reset Value
SUMR1 bits
Summation Register This most significant byte lowest bits summation register bits 8-15.
Summation Register (SUMR2)
Reset Value
SUMR2 bits
Summation Register This most significant byte lowest bits summation register bits 16-23.
Summation Register (SUMR3)
Reset Value
SUMR3 bits
Summation Register This most significant byte 32-bit summation register bits 24-31.
Offset Register (ODAC)
Reset Value
ODAC bits
Offset Register. This register will shift input half input range. least significant equal input voltage range divided 256. input range will depend setting PGA. With VREF 2.5V unipolar mode, gain range range 40mV. ODAC signed magnitude register with providing sign offset bits providing magnitude.
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Voltage Detect Control (LVDCON)
ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 Reset Value
ALVDIS ALVD2-0 bits
Analog Voltage Detect Disable. Enable Detection Analog Supply Voltage, ABOD HCR1 set. Disable Detection Analog Supply Voltage. Analog Voltage Detection Level.
ALVD2 ALVD1 ALVD0 VOLTAGE LEVEL AVDD 2.7V (default) AVDD 3.0V AVDD 3.3V AVDD 4.0V AVDD 4.2V AVDD 4.5V AVDD 4.7V External Voltage AIN7 Compared 1.2V
DLVDIS
Digital Voltage Detect Disable. Enable Detection Digital Supply Voltage, DBOD HCR1 set. Disable Detection Digital Supply Voltage. Digital Voltage Detection Level.
DLVD2 DLVD1 DLVD0 VOLTAGE LEVEL DVDD 2.7V (default) DVDD 3.0V DVDD 3.3V DVDD 4.0V DVDD 4.2V DVDD 4.5V DVDD 4.7V External Voltage AIN6 Compared 1.2V
DLVD2-0 bits
Extended Interrupt Enable (EIE)
EWDI Reset Value
EWDI
Enable Watchdog Interrupt. This enables/disables watchdog interrupt. Watchdog timer enabled WDTCON (SFR FFH) PDCON (SFR F1H) registers. Disable Watchdog Interrupt Enable Interrupt Request Generated Watchdog Timer External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt
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Hardware Product Code Register (HWPC0)
HWPC0.7 HWPC0.6 HWPC0.5 HWPC0.4 HWPC0.3 HWPC0.2 Reset Value 0000_00xx MEMORY SIZE
HWPC0.7-0 bits
Hardware Product Code LSB. Read only.
MEMORY SIZE
MODEL MSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5
FLASH MEMORY 16kB 32kB
Hardware Product Code Register (HWPC1)
HWPC1.7 HWPC1.6 HWPC1.5 HWPC1.4 HWPC1.3 HWPC1.2 HWPC1.1 HWPC1.0 Reset Value
HWPC1.7-0 bits
Hardware Product Code MSB. Read only.
Flash Memory Control (FMCON)
PGERA FRCM BUSY Reset Value
PGERA FRCM BUSY
Page Erase. Available both user program modes. Disable Page Erase Mode Enable Page Erase Mode Frequency Control Mode. bypass only used slow clocks save power. Bypass (default) Delay Line. Saves power (Recommended). Write/Erase BUSY Signal. Idle Available Busy
Flash Memory Timing Control Register (FTCON)
FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 Reset Value
Refer Flash Timing Characteristics FER3-0 bits FWR3-0 bits Erase. Flash Erase Time FER) (MSEC tCLK. Write. Flash Write Time FWR) (USEC tCLK.
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Register
Reset Value
B.7-0 bits
Register. This register serves second accumulator certain arithmetic operations.
Power-Down Control Register (PDCON)
PDPWM PDAD PDWDT PDST PDSPI Reset Value
Turning peripheral modules puts MSC1210 lowest power mode. PDPWM PDAD PDWDT PDST PDSPI Pulse Width Module Control. Power Down Control. ADC, VREF, Summation registers, Analog Brownout powered down. Analog current Watchdog Timer Control. Watchdog Timer Watchdog Timer Power Down System Timer Control. System Timer System Timer Power Down System Control. System System Power Down
PSEN/ALE Select (PASEL)
PSEN2 PSEN1 PSEN0 ALE1 ALE0 Reset Value
PSEN2-0 bits
PSEN Mode Select.
PSEN2 PSEN1 PSEN0 PSEN MODCLK HIGH
ALE1-0 bits
Mode Select.
ALE1 ALE0 HIGH
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Analog Clock (ACLK)
FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 Reset Value
FREQ4-0 bits
Clock Frequency This value divides system clock create clock. Clock System CLK/(FREQ fMOD [System CLK/(FREQ 1)]/64.
System Reset Register (SRST)
RSTREQ Reset Value
RSTREQ
Reset Request. Setting this then will generate system reset.
Extended Interrupt Priority (EIP)
PWDI Reset Value
PWDI
Watchdog Interrupt Priority. This controls priority watchdog interrupt. watchdog interrupt priority. watchdog interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority.
Seconds Timer Interrupt (SECINT)
SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 Reset Value
This system clock divided value 16-bit register MSEC. Then that timer tick divided register HMSEC which provides 100ms signal used this seconds timer. Therefore, this seconds timer generate interrupt which occurs from 100ms 12.8 seconds. Reading this register will clear Seconds Interrupt. This Interrupt monitored register. Write Control. Determines whether write value immediately wait until current count finished. Read Delay Write Operation. value loaded when current count expires. Write Immediately. counter loaded once completes write operation.
SECINT6-0 Seconds Count. Normal operation would 100ms clock interval. bits Seconds Interrupt SEC) (HMSEC (MSEC tCLK.
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Milliseconds Interrupt (MSINT)
MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 Reset Value
clock used this timer clock which results from dividing system clock values registers FDH. Reading this register will clear interrupt. MSINT6-0 bits Write Control. Determines whether write value immediately wait until current count finished. Read Delay Write Operation. MSINT value loaded when current count expires. Write Immediately. MSINT counter loaded once completes write operation. Seconds Count. Normal operation would clock interval. Interrupt Interval MSINT) (MSEC tCLK
Microsecond Register (USEC)
FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 Reset Value
FREQ4-0 bits
Clock Frequency This value divides system clock create Clock. USEC CLK/(FREQ This clock used Flash write time. FTCON (SFR EFH).
Millisecond Register (MSECL)
MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 Reset Value
MSECL7-0 bits
Millisecond Low. This value combination with next register used create Clock. Clock (MSECH MSECL tCLK. This clock used Flash erase time. FTCON (SFR EFH).
Millisecond High Register (MSECH)
MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 Reset Value
MSECH7-0 Millisecond High. This value combination with previous register used create clock. bits (MSECH MSECL tCLK.
Hundred Millisecond Register (HMSEC)
HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 Reset Value
HMSEC7-0 Hundred Millisecond. This clock divides clock create 100ms clock. bits 100ms (MSECH MSECL (HMSEC tCLK.
Watchdog Timer Register (WDTCON)
EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 Reset Value
EWDT DWDT RWDT WDCNT4-0 bits
Enable Watchdog. Read: WDEN current value. Write 1/Write sequence sets Watchdog Enable Counting bit. Disable Watchdog. Read: WDDIS current value. Write 1/Write sequence clears Watchdog Enable Counting bit. Reset Watchdog. Read: WDRST current value. Write 1/Write sequence restarts Watchdog Counter. Watchdog Count. Watchdog expires (WDCNT HMSEC (WDCNT HMSEC, sequence asserted. There uncertainty count.
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PACKAGE DRAWING (S-PQFP-G64)
0,50 0,27 0,17
MTQF006A JANUARY 1995 REVISED DECEMBER 1996
PLASTIC QUAD FLATPACK
0,08
0,13 7,50 10,20 9,80 12,20 11,80 1,05 0,95 Seating Plane Gage Plane 0,25 0,05 0,75 0,45
1,20
0,08 4040282 11/96
NOTES: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026
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