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8101/8104 Gigabit Ethernet Controller
This document contains proprietary information Logic Corporation. information contained herein used disclosed third parties without express written permission officer Logic Corporation. Document DB14-000123-04, Fourth Edition (November 2001) This document describes revision/release Logic Corporation 8101/8104 Gigabit Ethernet Controller will remain official reference source revisions/releases this product until rescinded update. Logic Corporation reserves right make changes products herein time without notice. Logic does assume responsibility liability arising application product described herein, except expressly agreed writing Logic; does purchase product from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties. Copyright 2000-2001 Logic Corporation. rights reserved. Portions TRADEMARK ACKNOWLEDGMENT Logic logo design registered trademark Logic Corporation. other brand product names trademarks their respective companies. receive product literature, visit http://www.lsilogic.com. current list distributors, sales offices, design resource centers, view page located
Copyright 2000-2001 Logic Corporation. rights reserved.
Preface
This book primary reference technical manual 8101/8104 Gigabit Ethernet Controller. contains complete functional description includes complete physical electrical specifications 8101/8104. 8104 functionally same 8101, except that 8104 208-pin Ball Grid Array (BGA) package 8101 208-pin Plastic Quad Flat Pack (PQFP) package
Audience This document assumes that have some familiarity with application specific integrated circuits related support devices. people benefit from this book are:
Engineers managers evaluating 8101/8104 Gigabit Ethernet Controller possible system Engineers designing 8101/8104 Gigabit Ethernet Controller into system
Organization This document following chapters:
Chapter Introduction, describes 8101/8104 Gigabit Ethernet Controller, basic features benifits. This chapter also describes differences between 8101 8104. Chapter Functional Description, provides high level description 8101/8104 Gigabit Ethernet Controller.
8101/8104 Gigabit Ethernet Controller
Copyright 2000-2001 Logic Corporation. rights reserved.
Chapter Signal Descriptions, provides description signals used generated 8101/8104 Gigabit Ethernet Controller. Chapter Registers, provides description register addresses definitions. Chapter Application Information, provides application considerations. Chapter Specifications, describes specifications 8101/8104 Gigabit Ethernet Controller.
Abbreviations Used This Manual 100BASE-FX 100BASE-TX 10BASE-T 4B5B CSMA CWRD IETF IREF Mbit/s Fiber Optic Ethernet Mbit/s Twisted-Pair Ethernet Mbit/s Twisted-Pair Ethernet 4-Bit 5-Bit Ball Grid Array Clock Cyclic Redundancy Check Carrier Sense Carrier Sense Multiple Access Codeword Destination Address Emitter-Coupled Logic Frame Stream Delimiter Frame Check Sequence Full-Duplex Fault Fast Link Pulse Fiber Half-Duplex High Impedance Individual/Group Internet Engineering Task Force Interpacket Reference Current Length Type Least Significant
Preface
Copyright 2000-2001 Logic Corporation. rights reserved.
MLT3 NRZI R/LH R/LHI R/LL R/LLI R/LT R/LTI R/WSC RJ-45 RMON SNMP Split-32
Management Information Base Multilevel Transmission levels) Most Significant millivolt Normal Link Pulse Nonreturn Zero Inverted Nonreturn Zero Opcode Printed Circuit Board picofarad Preamble Read Latched High Read Latched High with Interrupt Read Latched Read Latched with Interrupt Read Latched Transition Read Latched Transition with Interrupt Read/Write Self Clearing Request Comments Registered Jack-45 Remote Monitoring Start Address Station Address Start Frame Delimiter Simple Network Management Protocol Start Idle Independent 32-bit input output busses; transmit receive Start Stream Delimiter Shielded Twisted Pair Twisted Pair microHenry microprocessor Unshielded Twisted Pair
Conventions Used This Manual first time word phrase defined this manual, italicized.
Preface
Copyright 2000-2001 Logic Corporation. rights reserved.
word assert means drive signal true active. word deassert means drive signal false inactive. Signals that active "n." Hexadecimal numbers indicated prefix "0x" -for example, 0x32CF. Binary numbers indicated prefix "0b" -for example, 0b0011.0010.1100.1111.
Preface
Copyright 2000-2001 Logic Corporation. rights reserved.
Contents
CChapter
Introduction Overview Features Functional Description Overview Transmit Data Path Receive Data Path Register Structure Ethernet Frame Format 2.5.1 Preamble 2.5.2 Destination Address 2.5.3 Source Address 2.5.4 Length/Type Field 2.5.5 Data 2.5.6 Frame Check Sequence (FCS) 2.5.7 Interpacket (IPG) System Interface 2.6.1 Data Format Order 2.6.2 Transmit Timing 2.6.3 Receive Timing 2.6.4 Width 2.6.5 System Interface Disable Transmit 2.7.1 Preamble Generation 2.7.2 AutoPad 2.7.3 Generation 2.7.4 Interpacket 2.7.5 Control Frame Generation
Chapter
2-11 2-14 2-14 2-15 2-15 2-15 2-15 2-16 2-17
8101/8104 Gigabit Ethernet Controller
Copyright 2000-2001 Logic Corporation. rights reserved.
2.10
2.11
2.12
2.13
Receive 2.8.1 Preamble Stripping 2.8.2 Stripping 2.8.3 Unicast Address Filter 2.8.4 Multicast Address Filter 2.8.5 Broadcast Address Filter 2.8.6 Reject Accept Packets 2.8.7 Frame Validity Checks 2.8.8 Maximum Packet Size 2.8.9 Control Frame Check Transmit FIFO 2.9.1 AutoSend 2.9.2 Watermarks 2.9.3 Underflow 2.9.4 Overflow 2.9.5 Link Down FIFO Flush Receive FIFO 2.10.1 Watermarks 2.10.2 Overflow 2.10.3 Underflow 8B10B 2.11.1 8B10B Encoder 2.11.2 8B10B Decoder 2.11.3 Start Packet 2.11.4 Packet 2.11.5 Idle 2.11.6 Receive Word Synchronization 2.11.7 AutoNegotiation 10-Bit Interface 2.12.1 Data Format Order 2.12.2 Transmit 2.12.3 Receive 2.12.4 Lock Reference 2.12.5 Loopback 2.12.6 Signal Detect 2.12.7 Disable Packet Discard 2.13.1 Transmit Discards
2-17 2-17 2-17 2-18 2-18 2-19 2-20 2-20 2-21 2-21 2-22 2-22 2-22 2-23 2-23 2-24 2-24 2-24 2-25 2-25 2-25 2-26 2-28 2-29 2-30 2-30 2-31 2-31 2-31 2-32 2-32 2-32 2-33 2-33 2-33 2-34 2-34 2-34
viii
Contents
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2.14
2.15
2.16 2.17
2.18 2.19
2.20 2.21 Chapter
2.13.2 Receive Discards 2.13.3 Discard Output Indication 2.13.4 AutoClear Mode 2.13.5 AutoAbort Mode Receive Status Word 2.14.1 Format 2.14.2 Append Options 2.14.3 Status Word Discarded Packets 2.14.4 Status Word RXABORT Packets AutoNegotiation 2.15.1 Next Page 2.15.2 Negotiation Status 2.15.3 AutoNegotiation Restart 2.15.4 AutoNegotiation Enable 2.15.5 Link Indication Flow Control Control Frames 2.17.1 Automatic Pause Frame Generation 2.17.2 Transmitter Pause Disable 2.17.3 Pass Through FIFO 2.17.4 Reserved Multicast Address Disable 2.17.5 Control Frame AutoSend Reset Counters 2.19.1 Counter Half Full 2.19.2 Counter Reset Read 2.19.3 Counter Rollover 2.19.4 Counter Maximum Packet Size 2.19.5 Counter Reset Loopback Test Modes
2-35 2-36 2-36 2-36 2-37 2-37 2-38 2-38 2-38 2-39 2-40 2-41 2-41 2-42 2-42 2-42 2-42 2-43 2-44 2-44 2-46 2-46 2-46 2-47 2-57 2-57 2-58 2-58 2-58 2-59 2-59
Signal Descriptions System Interface Signals 10-Bit Interface Signals Register Interface Signals Micellaneous Signals
Contents
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Chapter
Power Supply Signals
3-10
Registers Register 4.1.1 4.1.2 4.1.3 Register Register 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 4.3.14 4.3.15 4.3.16 4.3.17 4.3.18 4.3.19 4.3.20 4.3.21 4.3.22 4.3.23 4.3.24 4.3.25
Interface Types Interrupt Register Structure Addresses Definitions Register 0-MAC Address Register 1-MAC Address Register 2-MAC Address Register 3-MAC Address Filter Register 4-MAC Address Filter Register 5-MAC Address Filter Register 6-MAC Address Filter Register 7-Configuration Register 8-Configuration Register 9-Configuration Register 10-Configuration Register 11-Status Register 14-Status Mask Register 17-Transmit FIFO Threshold Register 18-Receive FIFO Threshold Register 19-Flow Control Register 20-Flow Control Register 21-AutoNegotiation Base Page Transmit Register 22-AutoNegotiation Base Page Receive Register 23-AutoNegotiation Next Page Transmit Register 24-AutoNegotiation Next Page Receive Register 32-Device Register 112-115-Counter Half Full Registers 120-123-Counter Half Full Mask Registers 128-233-Counter 1-53
4-11 4-11 4-12 4-12 4-12 4-13 4-14 4-14 4-15 4-17 4-19 4-22 4-23 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-33 4-34 4-35 4-36 4-36 4-37
Contents
Copyright 2000-2001 Logic Corporation. rights reserved.
Chapter
Application Information Typical Ethernet Port 10-Bit Interface 5.2.1 External Physical Layer Devices 5.2.2 Printed Circuit Board Layout System Interface 5.3.1 Watermarks 5.3.2 Layout Reset Loopback AutoNegotiation 5.6.1 AutoNegotiation Power 5.6.2 Negotiating with Non-AutoNegotiation Capable Device Management Counters Packet Octet Counters Power Supply Decoupling Specifications Absolute Maximum Ratings Electrical Characteristics Electrical Characteristics 8101/8104 Pinouts Listings Package Mechanical Dimensions Customer Feedback
5-16 5-16
Chapter
6-17 6-21
Contents
Copyright 2000-2001 Logic Corporation. rights reserved.
Contents
Copyright 2000-2001 Logic Corporation. rights reserved.
Figures 6.10 6.11 6.12 6.13 6.14 6.15 8101/8104 Block Diagram Ethernet Frame Format Frame Formats Ordering Little Endian Endian Format RXSOF/RXEOF Position AutoNegotiation Data Format Autogenerated Pause Frame Format 8101/8104 Interface Diagram Gigabit Ethernet Switch Port Using 8101/8104 Decoupling Recommendations Input Clock Timing Transmit System Interface Timing Receive System Interface Timing Receive System Interface RXABORT Timing Receive System Interface RXOEn Timing System Interface RXDC/TXDC Timing Transmit 10-Bit Interface Timing Receive 10-Bit Interface Timing Register Interface Timing (Excluding Counter Read Cycle) Register Interface Timing, Counter Read Cycle Same Counter) Register Interface Timing, Counter Read Cycle (Between Different Counters) 8101 208-Pin PQFP Pinout 8104 208-Pin Pinout 208-Pin PQFP Mechanical Drawing mini-BGA (HG) Mechanical Drawing 2-13 2-39 2-45 5-17 6-10 6-11 6-12 6-14 6-15 6-16 6-17 6-19 6-21 6-22
xiii
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Copyright 2000-2001 Logic Corporation. rights reserved.
Tables 2.10 2.11 2.12 2.13 2.14 2.15 Length/Type Field Definition Byte Enable Valid Byte Position TXRC TXCRCn Logic Transmit Selection Multicast Address Filter Receive Maximum Packet Size Selection 8B10B Coding Table Defined Ordered Sets Transmit Discard Conditions Receive Discard Conditions Receive Status Word Definition AutoNegotiation Status Bits Reset Description Counter Definition Counter Maximum Packet Size Selection Register Type Definition Register Addresses Register Default Values Compatible SerDes Devices Reset Procedure SerDes Loopback Procedure AutoNegotiation Power Procedure Objects Counter Location RMON Statistics Group (RFC 1757) Objects Counter Location SNMP Interface Group (RFC 1213 1573) Objects Counter Location Ethernet-Like Group (RFC 1643) Objects Counter Location Ethernet (IEEE 802.3z, Clause Electrical Characteristics Input Clock Timing Characteristics Transmit System Interface Timing Characteristics Receive System Interface Timing Characteristics System Interface RXDC/TXDC Timing Characteristics Transmit 10-Bit Interface Timing Characteristics 2-10 2-16 2-16 2-19 2-21 2-27 2-28 2-34 2-35 2-37 2-41 2-47 2-49 2-58 4-10 5-10 5-11 5-13 5-14 6-10 6-11
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6.10
Receive 10-Bit Interface Timing Characteristics Register Interface Timing Characteristics 8101 208-Pin PQFP List (Alphabetical Listing) 8104 208-Pin List (Alphabetical Listing)
6-12 6-13 6-18 6-21
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Chapter Introduction
This chapter contains brief introduction 8101/8104 Gigabit Ethernet Controller. consists following sections:
Section 1.1, "Overview" Section 1.2, "Features"
Overview
8101/8104 Gigabit Ethernet Controller complete media access controller (MAC sublayer) with integrated coding logic fiber short haul copper media bit/10 Physical Coding Sublayer) (8B10B PCS) 1000 Mbits/s Gigabit Ethernet systems. 8104 functionally same 8101 except that 8104 208-pin Ball Grid Array (BGA) package 8101 208-pin Plastic Quad Flat Pack (PQFP) package Controller consists 32-bit system interface, receive/transmit First First (FIFO) buffers, full-duplex Ethernet Media Access Controller (MAC), bit/10 PCS, 10-bit Physical Layer Device (PHY) interface, 16-bit register interface. controller also contains necessary circuitry implement IEEE 802.3x Flow Control Algorithm. Flow control messages sent automatically without host intervention. controller contains counters which satisfy management objectives Remote Monitoring (RMON) Statistics Group MIB, (RFC 1757), Simple Network Management Protocol (SNMP) Interfaces Group (RFC 1213 1573), Ethernet-Like Group (RFC 1643), Ethernet (IEEE 802.3z Clause 30). controller also contains
8101/8104 Gigabit Ethernet Controller
Copyright 2000-2001 Logic Corporation. rights reserved.
internal 16-bit registers that accessed through register interface. These registers contain configuration inputs, status outputs, management counter results. 8101/8104 ideal Ethernet controller Gigabit Ethernet switch ports, uplinks, backbones, adapter cards.
Features
8101/8104 provides following features.
Pin-compatible upgrade 8100 Combined Ethernet 8B10B 1000 Mbits/s data rate 64-bit, external interface Gbits/s bandwidth) 10-bit interface external SerDes chip 16-bit interface internal registers management counters Full RMON, SNMP, Ethernet management counter support Independent receive transmit FIFOs with programmable watermarks Kbytes receive FIFO size Kbytes transmit FIFO size
AutoNegotiation algorithm chip Full duplex only Flow control IEEE 802.3x Automatic generation checking Automatic packet error discarding Programmable transmit start threshold Interrupt capability Support fiber short haul copper media power supply, tolerant inputs IEEE 802.3 802.3z specification compliant
Introduction
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Chapter Functional Description
This chapter provides high level description 8101/8104 Gigabit Ethernet Controller consists following sections:
Section 2.1, "Overview" Section 2.2, "Transmit Data Path" Section 2.3, "Receive Data Path" Section 2.4, "Register Structure" Section 2.5, "Ethernet Frame Format" Section 2.6, "System Interface" Section 2.7, "Transmit MAC" Section 2.8, "Receive MAC" Section 2.9, "Transmit FIFO" Section 2.10, "Receive FIFO" Section 2.11, "8B10B PCS" Section 2.12, "10-Bit Interface" Section 2.13, "Packet Discard" Section 2.14, "Receive Status Word" Section 2.15, "AutoNegotiation" Section 2.16, "Flow Control" Section 2.17, "MAC Control Frames" Section 2.18, "Reset" Section 2.19, "Counters" Section 2.20, "Loopback" Section 2.21, "Test Modes"
8101/8104 Gigabit Ethernet Controller
Copyright 2000-2001 Logic Corporation. rights reserved.
Overview
8101/8104 complete Media Access Controller (MAC) sublayer with integrated coding logic fiber short haul copper media (8B10B sublayer) 1000 Mbits/s Gigabit Ethernet systems. controller seven main sections:
System interface FIFOs 8B10B 10-bit interface Register interface. Management counters
block diagram shown Figure 2.1. controller transmit data path receive data path. transmit data path goes system interface 10-bit interface, shown half Figure 2.1. receive data path goes 10-bit interface system interface, shown bottom half Figure 2.1.
Transmit Data Path
Data input system from external bus. data then sent transmit FIFO. transmit FIFO provides temporary storage data until sent transmit section. transmit formats data into Ethernet packet according IEEE 802.3 specification shown Figure 2.2. transmit also generates control frames includes logic AutoNegotiation. Ethernet frame packet then sent 8B10B PCS. 8B10B encodes data adds appropriate framing delimiters create 10-bit symbols specified IEEE 802.3 shown Figure 2.3. 10-bit symbols then sent 10-bit interface transmission external device.
Functional Description
Copyright 2000-2001 Logic Corporation. rights reserved.
Figure
RESETn SCLK TXENn TXD[31:0] TXBE[3:0] TXSOF TXEOF TXWM1n TXWM2n TXDC CLR_TXDC TXCRCn FCNTRL RXENn RXD[31:0] RXBE[3:0] RXSOF RXEOF RXWM1 RXWM2 RXDC CLR_RXDC RXABORT RXOEn
8101/8104 Block Diagram
TCLK 8B10B
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Transmit FIFO Generator
Packet Generator
8B10B Encoder
Transmit
TX[9:0]
Functional Description
Control Frame Gen.
System Interface
Transmit Receive
Transmit Receive
10-Bit Interface
EWRAP LCK_REFn
Control Frame Check Address Filter Receive FIFO Check Link Configuration EN_CDET
Receive Sync.
REGCLK REGCSn REGD[15:0] REGAD[7:0] REGRDn REGWRn REGINT
Packet Decompose Register Interface Registers Management Counters
8B10B Decoder
RX[0:9] Receive RBC[1:0] LINKn
Figure
Ethernet Frame Format
Frame Format Bytes Byte Preamble Start Frame Delimiter (SFD) Destination Address (DA) Source Address (SA) Length/Type (L/T) Data Frame Check Sequence (FCS)
Bytes
Below
Bytes Bytes 46-1500 Bytes Bytes
Bytes Within Frame Transmitted Bottom
Bits Within Frame Transmitted Left Right
Address Field Format Bits Registers
40-Bit Address
Multicast Broadcast Unicast
Broadcast Multicast
Functional Description
Copyright 2000-2001 Logic Corporation. rights reserved.
Figure
Frame Formats Ordering
System Interface 10-Bit Interface
10101010 10101010 10101010 10101010 10101010 10101010 10101010 10101011 [0:7] [8:15] [16:23] [24:31] [32:39] [40:47] [0:7] [8:15] [16:23] [24:31] [32:39] [40:47] [0:7] [8:15] DATA[0:7] DATA[8:15] DATA[16:23] DATA[24:31]
TXD[0] RXD[0] TXD[31] RXD[31] DA[16:23] SA[0:7] SA[32:39] DATA[0:7] DA[24:31] SA[8:15] SA[40:47] DATA[7:15]
/I2/ /I2/ D21.2 D21.2 D21.2 D21.2 D21.2 D21.2 D21.6 [0:7]> [8:15]> [16:23]> [24:31]> [32:39]> [40:47]> [0:7]> [8:15]> [16:23]> [24:31]> [32:39]> [40:47]> [0:7]> [8:15]> <DATA[0:7]> <DATA[8:15]> <DATA[16:23]> <DATA[24:31]>
DA[0:7] DA[8:15] DA[32:39] DA[40:47] SA[16:23] SA[24:31] LT[0:7] LT[8:16] DATA[16:23] DATA[24:31]
FCS[31:24] FCS[23:16] FCS[7:0] INVALID STATUS WORD
FCS[15:8]
DATA
FCS[31:24] FCS[23:16] FCS[15:8] FCS[7:0]
<FCS[31:24]> <FCS[23:16]> <FCS[15:8]> <FCS[7:0]> /I1/ /I2/ /I2/ /I2/
Notes: Status word receive only programmable position programmable Little endian format (default) Second added only transmit packet ends number bytes preamble appended Receive preamble stripped appended Receive stripped Means encoded /I1/ /I2/, depends running disparity
ABCDEFGH Bytes Transmitted
abcdefghij TX[0] RX[0]
TX[9] 10-Bit RX[9] Interface
Bits Transmitted
Transmit Data Path
Copyright 2000-2001 Logic Corporation. rights reserved.
Receive Data Path
10-bit interface receives incoming encoded data from external device. incoming encoded data must encoded 10-bit format specified IEEE 802.3z, shown Figure 2.3. incoming encoded data then sent receive 8B10B block, which strips framing delimiters, decodes data, converts encoded data into Ethernet packet according IEEE 802.3 specifications, shown Figure 2.2. Ethernet packet data then sent receive section. receive section disassembles packet, checks validity packet against certain error criteria address filters, checks control frames. receive then sends valid packets receive FIFO. receive FIFO provides temporary storage data until demanded system interface. system interface outputs data external bus.
Register Structure
controller internal 16-bit registers. registers available setting configuration inputs reading status outputs. remaining registers associated with management counters. register interface separate internal register bidirectional data configuration inputs, read status outputs, access management counters. location registers described Register Addressing Table Section 4.2, "Register Addresses". description each each register described Section 4.3.1 through Section 4.3.25.
Ethernet Frame Format
Information Ethernet network transmitted received packets frames. basic function controller process Ethernet frames. Ethernet frame defined IEEE 802.3 consists preamble, start frame delimiter (SFD), destination address (DA),
Functional Description
Copyright 2000-2001 Logic Corporation. rights reserved.
source address (SA), length/type field (L/T), data, frame check sequence (FCS), interpacket (IPG). format Ethernet frame shown Figure 2.2. Ethernet frame specified IEEE 802.3 have minimum length bytes maximum length 1518 bytes, exclusive preamble SFD. Packets that less than bytes greater than 1518 bytes referred undersize oversize packets, respectively.
2.5.1 Preamble
preamble combined 64-bit field consisting alternating ones zeros followed 0b11 preamble indicator. first 56-bits ones zeros considered preamble, last bits (0b10101011) considered SFD.
2.5.2 Destination Address
destination address 48-bit field containing address station(s) which frame directed. format address field same defined IEEE 802.3 shown Figure destination address either unicast address specific station, multicast address group stations, broadcast address stations. first second bits determine whether address unicast, multicast broadcast, remaining bits actual address bits, shown Figure
2.5.3 Source Address
source address 48-bit field containing specific station address from which frame originated. format address field same defined IEEE 802.3 shown Figure
2.5.4 Length/Type Field
16-bit length/type field takes meaning either packet length packet type, depending numeric value, described Table 2.1.
Ethernet Frame Format
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Table
Length/Type Field Value (Decimal) 0-1500 1501-1517 1518
Length/Type Field Definition
Length Type Length Neither Type
Definition Total number bytes data field minus padding Undefined Frame type
2.5.5 Data
data 46-1500 byte field containing actual data transmitted between stations. actual data less than bytes, extra zeros added increase data field byte minimum size. Adding these extra zeros referred padding.
2.5.6 Frame Check Sequence (FCS)
32-bit cyclic redundancy check (CRC) value computed entire frame, exclusive preamble SFD. algorithm defined IEEE 802.3. appended frame determines frame validity.
2.5.7 Interpacket (IPG)
time interval between packets. minimum value bits, where Gigabit Ethernet. There maximum limit.
System Interface
system interface 64-bit wide data interface consisting separate 32-bit data busses transmit receive.
2.6.1 Data Format Order
format data word TXD[31:0] RXD[31:0] relationship frame format 10-bit interface format
Functional Description
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shown Figure 2.3. Note that controller programmed append additional 32-bit status word receive packet. Refer Section 2.14, "Receive Status Word," more details this status word. program byte ordering data bits, endian "Register 10-Configuration Section 4.3.11. byte order shown Figure with little endian format mode (default). controller placed endian format, byte order shown Figure reversed, DA[0:7] occurs pins RXD[24:31], DA[24:31] occurs pins RXD[0:7]and endian affects bytes frame including receive status word appended). difference between little endian endian format illustrated Figure 2.4. Figure Little Endian Endian Format
TXD[8] TXD[15] RXD[8] RXD[15] Little Endian (Default) TXD[0] TXD[7] RXD[0] RXD[7] TXD[24] TXD[31] RXD[2]4 RXD[31] TXD[8] TXD[15] RXD[8] RXD[15] TXD[16] RXD[16]
TXD[16] TXD[23] RXD[16] RXD[23]
TXD[0] TXD[7] RXD[0] RXD[7]
Preamble
DA15
DA16 DA23
DA24 DA31
DA32 DA39
DA40 DA47
Source Address
Endian
TXD[24] TXD[31] RXD[24] RXD[31]
TXD[8] TXD[15] RXD[8] RXD[15]
TXD[24] TXD[31] RXD[24] RXD[31]
TXD[15] RXD[15]]
TXD[16]. TXD[23] RXD[16] RXD[23]
TXD[0] TXD[7] RXD[0] RXD[7]
TXD[16] TXD[23] RXD[16] RXD[23]
2.6.2 Transmit Timing
transmit portion system interface consists signals: transmit data input bits (TXD[31:0]), transmit enable (TXENn), four transmit byte enable inputs (TXBE[3:0]), transmit start frame frame inputs (TXSOF TXEOF), transmit FIFO watermark outputs (TXWM1n TXWM2n), transmit discard output (TXDC), transmit discard clear input (CLR_TXDC), transmit enable input (TXCRCn), flow control enable input (FCNTRL). receive transmit data clocked rising edge system clock, SCLK. SCLK must operate between 33-66 MHz. SCLK input needs continuously input controller 33-66 MHz. When TXENn deasserted, transmit interface selected subsequently, controller accepts input data from
System Interface
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transmit system interface inputs. When TXENn asserted, data word TXD[31:0] input clocked into transmit FIFO each rising edge SCLK clock input. Multiple packets clocked TXENn assertion. TXD[31:0] input data 32-bit wide packet data whose format relationship packet 10-bit data described Figure 2.3. TXBE[3:0] pins determine which bytes 32-bit TXD[31:0] data word contain valid data. TXBE[3:0] clocked rising edge SCLK along with each TXD[31:0] data word. correspondence between byte enable inputs valid bytes each data word TXD[31:0] defined Table 2.2. logic combination TXBE[3:0] inputs allowed, with exception that TXBE[3:0] must 0b0000 SCLK cycle when TXSOF TXEOF asserted. Table Byte Enable Valid Byte Position
Valid Bytes TXD[31:0]/RXD[31:0] Pins TXD[31:24]/RXD[31:24] TXD[23:16]/RXD[23:16] TXD[15:8]/RXD[15:8] TXD[7:0]/RXD[7:0]
TXBE[3:0]/RXBE[3:0] Byte Enable Pins TXBE[3]/RXBE[3] Asserted TXBE[2]/RXBE[2] Asserted TXBE[1]/RXBE[1] Asserted TXBE[0]/RXBE[0] Asserted
TXSOF TXEOF signals indicate controller which data words start Ethernet data packet, respectively. These signals input same SCLK rising edge first last word data packet. TXWM1n TXWM2n signals indicate when transmit FIFO exceeded programmable watermark thresholds. controller asserts watermarks rising edge SCLK, depending fullness transmit FIFO. Refer Section 2.9, "Transmit FIFO," more details these watermarks.
2-10
Functional Description
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TXDC transmit packet discard output. TXDC asserted every time transmission packet being input system interface halted packet discarded some error. This signal latched HIGH. cleared when clearing signal, CLR_TXDC, asserted cleared automatically controller placed AutoClear mode. Section 2.13, "Packet Discard," more details discards TXDC. TXCRCn input that enable internal generation appending 4-byte value onto data packet. TXCRCn sampled rising edge SCLK asserted beginning packet, coincident with TXSOF, remove that packet. Setting transmit enable (TXCRC) Configuration register also enables generation. Refer Section 2.7.3, "CRC Generation" more details generation interaction between TXCRCn TXCRC bit. FCNTRL input that causes automatic generation transmission control pause frame. FCNTRL input rising edge SCLK. Section 2.17, "MAC Control Frames," more details about this feature.
2.6.3 Receive Timing
receive portion system interface consists signals:
receive output data bits (RXD[31:0]) receive enable input (RXENn) Four receive byte enable outputs (RXBE[3:0]) receive start frame frame outputs (RXSOF RXEOF) receive FIFO watermark outputs (RXWM1 RXWM2) receive discard output (RXDC) receive discard clear input (CLR_RXDC) receive packet abort input (RXABORT) receive output enable (RXOEn)
receive transmit data clocked with system clock, SCLK, which must operate between 33-66 MHz.
System Interface
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2-11
SCLK input must continuously operate 33-66 MHz. When RXENn deasserted, receive interface selected and, subsequently, data from receive FIFO output over system interface. receive watermarks RXWM1 RXWM2 asserted while RXENn deasserted, next data word from receive FIFO appears RXD[31:0] outputs until RXENn asserted. When RXENn asserted, data word from receive FIFO clocked onto RXD[31:0] outputs after each rising edge SCLK input. After entire packet been clocked out, more data clocked RXD[31:0] until RXENn deasserted reasserted, which allows extra dribble SCLK clock cycles occur after packet. RXD[31:0] output data 32-bit wide packet data whose format relationship packet 10-bit data described Figure 2.3. RXBE[3:0] signals determine which bytes 32-bit RXD[31:0] data word contain valid data. RXBE[3:0] clocked rising edge SCLK along with each RXD[31:0] data word. Note that RXBE[3:0] 0b1111 words packet except last word, which 4-byte boundaries 32-bit data word. correspondence between byte enable inputs valid data bytes each data word RXD[31:0] defined Table 2.2. RXSOF RXEOF signals indicate which words start Ethernet data packet, respectively. These signals generally clocked same SCLK rising edge first last word data packet, respectively. However, their exact position relative data packet dependent programming PEOF STSWRD[1:0] bits Register "Configuration exact RXSOF RXEOF position combinations these bits shown Figure 2.5. More details about definition these bits found "Register 7-Configuration Section 4.3.8, more details about status word found Section 2.14, "Receive Status Word,".
2-12
Functional Description
Copyright 2000-2001 Logic Corporation. rights reserved.
Figure
RXSOF/RXEOF Position
FIFO Data First Data Word RXSOF/RXEOF Position Bits (STSWRD [1:0], PEOF)
Packet Data
Last Data Word Status Word Discard Status Word
SOF,
SOF,
Note: Status words exist with this combination
RXWM1 RXWM2 signals indicate when receive FIFO exceeded programmable watermark thresholds. watermarks asserted deasserted rising edge SCLK, depending fullness receive FIFO. Refer Section 2.10, "Receive FIFO," more details these watermarks. RXDC asserted every time received packet being output over system interface halted packet discarded some error. This signal latched HIGH cleared either asserting clearing signal, CLR_RXDC, cleared automatically controller placed AutoClear mode. Section 2.13, "Packet Discard," section more details discards RXDC. RXABORT input, when asserted, discards current packet being output system interface. When RXABORT asserted, packet discarded remaining contents that packet receive FIFO flushed. process flushing receive packet from receive FIFO with RXABORT requires extra SCLK cycles equal (packet length bytes)/8 Refer Section 2.13, "Packet Discard," more information about discarded packets. Clearing discard RXABORT enable "Register 8-Configuration Section 4.3.9, programs controller ignore RXABORT signal. Setting
System Interface
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2-13
RXABORT definition "Register 9-Configuration Section 4.3.10, also programs controller discard either data packet status word just data packet exclusive status word. RXOEn signal, when asserted, places certain receive outputs high-impedance state. RXOEn affects RXD[31:0], RXBE[3:0], RXSOF, RXEOF output pins.
2.6.4 Width
Setting BUSSIZE "Register 10-Configuration Section 4.3.11, changes receive word width from 32-bits 16-bits. When width configured 16-bits, receive system interface data outputs appear RXD[15:0] data words 16-bits wide instead 32-bits wide. Note: transmit word width adjusted appropriately setting transmit byte enable inputs, TXBE[3:0], described Table 2.2.
2.6.5 System Interface Disable
disable system interface, SINTF_DIS "Register Configuration Section 4.3.10. When system interface disabled, controller:
Places system interface outputs high-impedance state (TXWMn[1:2], TXDC, RXD[31:0], RXBE[3:0], RXSOF, RXEOF, RXWM1/2, RXDC) Ignores inputs (SCLK, TXENn, TXD[31:0], TXBE[3:0], TXSOF, TXEOF, CLR_TXDC, FCNTRL, TXCRCn, RXENn, RXOEn, CLR_RXDC, RXABORT) Transmits (see Table 2.8) ordered sets with remote fault bits RF[1:0] 0b10 over 10-bit interface outputs
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Functional Description
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Transmit
generate Ethernet frame from transmit FIFO, transmit section:
Generates preamble Pads undersize packets with zeros meet minimum packet size requirements Calculates appends value packet Maintains minimum interpacket
Each above four operations individually disabled altered desired. transmit then sends fully formed Ethernet packet 8B10B block encoding. transmit section also generates control frames.
2.7.1 Preamble Generation
transmit normally appends preamble packet. program controller append preamble transmit packet, clear TXPRMBL "Register Configuration Section 4.3.8.
2.7.2 AutoPad
transmit normally AutoPads packets. AutoPadding process automatically adding enough zeroes packets with data fields less than bytes make data field exactly bytes length which meets 46-byte minimum data field requirement IEEE 802.3. program controller AutoPad, clear APAD "Register 7-Configuration Section 4.3.8.
2.7.3 Generation
transmit normally appends value packet. program controller append value packet from transmit FIFO, assert TXCRCn clear TXCRC Register "Configuration described Table described "Register 7-Configuration Section 4.3.8.
Transmit
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Table
TXCRC Bit1
TXRC TXCRCn Logic
TXCRCn2 Appended Packet?
Append, append append, Append
2.7.4 Interpacket
packets from transmit FIFO arrive transmit sooner than minimum time transmit adds enough time between packets equal minimum value. default time bits ns).To program other values, transmit select bits IPG[2:0] "Register 7-Configuration Section 4.3.8, summarized Table 2.4. Table
IPG[2:0] Bits
Transmit Selection
Value (ns) IEEE minimum specification IEEE minimum specification IEEE minimum specification
Comments IEEE minimum specification
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Functional Description
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2.7.5 Control Frame Generation
transmit automatically generate transmit control pause frames, which used flow control. This function described more detail Section 2.17, "MAC Control Frames".
Receive
receive section performs following operations disassemble Ethernet packets received from receive 8B10B section:
Strips preamble Strips Checks destination address against address filters determine packet validity Checks frame validity against discard conditions Checks length/type field control frames
Each above operations individually disabled altered, desired. receive then sends valid packets receive FIFO storage.
2.8.1 Preamble Stripping
transmit normally strips preamble from receive packet. program controller strip preamble RXPRMBL "Register 7-Configuration Section 4.3.8. When this set, preamble left receive packet stored receive FIFO part packet.
2.8.2 Stripping
receive normally strips from receive packet. program controller strip field, RXCRC "Register 7-Configuration Section 4.3.8. When this last four bytes packet containing value left receive packet stored receive FIFO part packet.
Receive
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2.8.3 Unicast Address Filter
Comparing destination address receive packet against 48-bit value stored three Address registers (registers filters unicast packets. When destination address unicast packet matches value stored these registers unicast packet deemed valid passed receive FIFO; otherwise, packet rejected. correspondence between bits Address registers incoming bits destination address receive packet defined Address register definitions. program controller always reject unicast packets, REJUCST "Register 8-Configuration Section 4.3.9. When this unicast packets rejected regardless their address. Unicast packet address filtering functions affect reception control frames. Other bits described Section 2.17, "MAC Control Frames," control reception control frames.
2.8.4 Multicast Address Filter
multicast address filter function computes incoming Destination Address produces 6-bit number that compared against values stored Address Filter registers (Registers When multicast packet destination address passes address filter, packet deemed valid passed receive FIFO; otherwise, packet rejected. multicast address filter requires address filter bits written into Address Filter registers. multicast address filtering algorithm follows: Compute separate 32-bit destination address field using same IEEE 802.3 defined method that computes transmit CRC. bits [0:2] destination address select bytes 64-bit address filter, shown Table 2.5. bits [3:5] destination address select bits within byte selected (2), shown Table 2.5.
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Functional Description
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selected "one" destination address passes filter; otherwise, address fails filter packet rejected discarded. Note: bits address filter programmed ones, address filter passes multicast addresses. Multicast Address Filter
Address Filter Byte2 F0[7:0] F1[7:0] F2[7:0] F3[7:0] F4[7:0] F5[7:0] F6[7:0] F7[7:0] Bits [3:5]1 Address Filter Bit3 Fx[0] Fx[1] Fx[2] Fx[3] Fx[4] Fx[5] Fx[6] Fx[7]
Table
Bits [0:2]1
Bits least-significant bits CRC. F[7:0] bytes Address Filter Registers. Fx[7:0] bits within each byte Address Filter Registers.
Setting REJMCST "Register 8-Configuration Section 4.3.9, programs controller reject multicast packets regardless their address. When this multicast packets rejected regardless their address. Multicast packet address filtering functions affect reception control frames. Other bits described Section 2.17, "MAC Control Frames," control reception control frames.
2.8.5 Broadcast Address Filter
controller does filtering broadcast packets. program controller reject broadcast packets, REJBCST "Register 8-Configuration Section 4.3.9. When this broadcast packets rejected regardless their address.
Receive
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Broadcast address filtering functions affect reception control frames. Other bits described Section 2.17, "MAC Control Frames," control reception control frames.
2.8.6 Reject Accept Packets
Setting ACPTAL REJALL bits "Register 8-Configuration Section 4.3.9, programs controller accept reject packets regardless type whether packet passes address filter. These bits affect reception control frames. Other bits described Section 2.17, "MAC Control Frames," control reception control frames.
2.8.7 Frame Validity Checks
receive checks following determine validity each receive packet:
Valid Oversize packet Undersize packet
Computing value incoming receive packet according IEEE 802.3 specifications comparing against actual value field received packet determines validity FCS. values same, frame determined invalid packet discarded. Refer Section 2.13, "Packet Discard" more information about discards. Clearing DIS_CRC error "Register 8-Configuration Section 4.3.9, programs controller discard packet with FCS. Oversize packets packets whose length greater than maximum packet size. received packet oversize packet, then packet determined invalid discarded. Refer Section 2.13, "Packet Discard" more information about discards. Clearing DIS_OSIZE "Register 8-Configuration Section 4.3.9, programs controller discard oversize packet allow packets unlimited length.
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Functional Description
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Undersize packets packets whose length less than minimum packet size. Minimum packet size defined bytes, exclusive preamble SFD. received packet undersize packet, frame determined invalid discarded. Refer Section 2.13, "Packet Discard" more information about discards. Clearing DIS_USIZE "Register 8-Configuration Section 4.3.9, programs controller discard undersize packet.
2.8.8 Maximum Packet Size
maximum packet size used receive frame validity checking programmed four values, 1518, 1522, 1535 unlimited bytes. Setting RMXPKT[1:0] receive maximum packet size select bits "Register 9-Configuration Section 4.3.10, DIS_OSIZE "Register 8-Configuration Section 4.3.9, shown Table 2.6. programs controller discard packets that exceed maximum packet size selected. This selection also described register descriptions those registers. bits shown Table affect receive section only; maximum packet size management counters described Section 2.19, "Counters". Table Receive Maximum Packet Size Selection
Register RMXPKT [1:0] Bits 0b10 0b01 0b00 Maximum Packet Size (Bytes) unlimited 1535 1522 1518
Register DIS_OSIZE Don't Care
2.8.9 Control Frame Check
length/type field checked detect whether packet valid control frame. Refer Section 2.17, "MAC Control Frames" more details control frames.
Receive
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Transmit FIFO
transmit FIFO acts temporary buffer between system interface transmit section. transmit FIFO size Kbytes. Data clocked into transmit FIFO with 33-66 system interface clock, SCLK. Data automatically clocked transmit FIFO with 8B10B clock whenever full packet been loaded into FIFO written into FIFO system interface), FIFO data exceeds transmit FIFO AutoSend threshold. There programmable watermark outputs, TXWM1n TXWM2n, which managing data flow into transmit FIFO.
2.9.1 AutoSend
AutoSend feature causes packet transmit FIFO automatically transmitted when data transmit FIFO exceeds certain threshold. transmit AutoSend threshold programmable over lower Kbytes transmit FIFO. AutoSend threshold programmed with TASND[5:0] bits that reside Transmit FIFO Threshold register. Whenever data FIFO exceeds this threshold, packet automatically transmitted 8B10B section 10-bit interface. packet also automatically transmitted written into transmit FIFO that packet, regardless AutoSend threshold setting. settings transmit AutoSend threshold evenly distributed over lower half transmit FIFO range, except 0b000000 setting. 0b000000 setting automatically starts transmission when transmit FIFO full, thus facilitating transmission oversize packets. Refer "Register 17-Transmit FIFO Threshold," Section 4.3.14, description more details AutoSend (TASND[5:0]) settings.
2.9.2 Watermarks
There transmit watermarks transmit FIFO which output TXWM1n TXWM2n pins. These watermarks asserted when transmit FIFO data exceeds thresholds associated with watermarks.
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Functional Description
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transmit watermark thresholds TXWM1n TXWM2n programmed over entire Kbyte FIFO range. Each watermark thresholds independently programmed with five bits that reside Transmit FIFO Threshold register. Whenever data FIFO exceeds threshold either watermark, respective watermark TXWM1n TXWM2n asserted LOW. watermark signals stay asserted until data FIFO goes below respective thresholds.
2.9.3 Underflow
transmit FIFO underflow condition occurs when FIFO empty still requesting data complete transmission packet. transmit FIFO underflows:
Packet transmission 8B10B halted code (see Table 2.8) appended partially transmitted packet data partially transmitted packet discarded
Refer Section 2.13, "Packet Discard" more information about discards.
2.9.4 Overflow
transmit FIFO overflow condition occurs when FIFO full additional data still being written into from system interface. transmit FIFO overflows:
input FIFO blocked does accept more data from system interface until FIFO space freed data already stored FIFO partially loaded last packet transmitted with code (see Table 2.8) appended packet indicate error data partially loaded last packet discarded
Refer Section 2.13, "Packet Discard" more information about discards.
Transmit FIFO
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2.9.5 Link Down FIFO Flush
When link down (also referred link fail) defined either receiver lost sync AutoNegotiation process completed, transmitter 10-bit interface occupied with sending either idle AutoNegotiation codes (/I/ Table 2.8). result, data cannot exit transmit FIFO transmit section. data continues input transmit FIFO from system interface while controller link fail mode transmit FIFO overflow. Enabling link down FIFO flush feature causes data exiting transmit FIFO automatically discarded when controller link fail mode, thus preventing possible overflow transmit FIFO. Setting Link Down FIFO Flush Enable (LNKDN) "Register 10-Configuration Section 4.3.11, enables link down FIFO flush mode.
2.10 Receive FIFO
receive FIFO acts temporary buffer between receive section system interface. receive FIFO size Kbytes. Data clocked into receive FIFO with 8B10B clock. Data clocked receive FIFO with 33-66 system interface clock, SCLK. There programmable watermark outputs, RXWM1 RXWM2, which managing data flow receive FIFO.
2.10.1 Watermarks
There watermarks receive FIFO. which output RXWM1 RXWM2 pins. These watermarks asserted when receive FIFO data exceeds thresholds associated with watermarks. receive watermark thresholds RXWM1 RXWM2 programmed over entire Kbyte receive FIFO range. Each watermark thresholds independently programmed with eight bits that reside Receive FIFO Threshold register. Whenever data FIFO exceeds threshold either watermark, respective watermark either RXWM1 RXWM2 asserted HIGH. RXWM2 also asserted complete packet loaded into receive FIFO from
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Functional Description
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8B10B section. watermarks stay asserted until data FIFO goes below respective thresholds, RXWM2 also stays asserted until packets (EOF) have been read receive FIFO. After EOFs have been read receive FIFO, watermarks cannot active again until RXENn deasserted.
2.10.2 Overflow
receive FIFO overflow condition occurs when receive FIFO full additional data still being written into from MAC. receive FIFO overflows:
input FIFO blocked does accept more data from 8B10B until FIFO space freed data already stored FIFO partially loaded last packet normally discarded data partially loaded last packet also normally discarded
Refer Section 2.13, "Packet Discard" more information about discards. Clearing DIS_OVF "Register 8-Configuration Section 4.3.9, programs controller discard packet corrupted overflow.
2.10.3 Underflow
receive FIFO underflow condition occurs when system interface attempting read data FIFO when empty. FIFO underflows, data read FIFO while underflow condition persists invalid, data partially loaded last packet stored FIFO discarded.
2.11 8B10B
8B10B transmit section receive section. transmit 8B10B section accepts Ethernet formatted packet data from transmit and:
Encodes data with 8B10B encoder Adds start packet delimiter
8B10B
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Adds packet delimiter Adds idle code stream Formats packet according format defined IEEE 802.3z shown Figure
8B10B encoded data stream then sent transmit 10-bit interface transmission. transmit 8B10B section also generates AutoNegotiation code stream when controller AutoNegotiation process. receive 8B10B section takes 8B10B encoded packet data from incoming 10-bit interface and:
Acquires maintains word synchronization Strips start packet delimiter Strips packet delimiter Strips idle code stream Decodes data with 8B10B decoder Converts packet Ethernet packet format shown Figure
Ethernet packet then sent receive processing. receive 8B10B section also decodes AutoNegotiation code stream when controller AutoNegotiation process.
2.11.1 8B10B Encoder
8B10B encoder converts each data byte packet into unique 10-bit word defined IEEE 802.3z shown Table abbreviated form).
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Functional Description
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Table
8B10B Coding Table
Bytes Codes CurrentRD- abcdei fghj 100111 0100 011101 0100 101101 0100 110001 1011 001110 1110 101110 0001 011110 0001 101011 0001 CurrentRD+ abcdei fghj 011000 1011 100010 1011 010010 1011 110001 0100 001110 0001 010001 1110 100001 1110 010100 1110
Data Byte Name D0.0 D1.0 D2.0 D3.0 D28.7 D29.7 D30.7 D31.7
Bits HGFEDCBA 00000 00001 00010 00011 11100 11101 11110 11111
encoder also converts start packet delimiter, packet delimiter, idle code streams, AutoNegotiation code streams into unique code words. These unique code words referred ordered sets. Table describes ordered sets defined used IEEE 802.3z. 8B10B encoder also keeps running disparity outgoing word close possible zero. Running disparity difference between number ones zeros transmitted outgoing stream. algorithm calculating running disparity defined 802.3z. After each word transmitted, running disparity recalculated. current running disparity negative, next word chosen from "Current RD-" column Table abbreviated form). current running disparity positive, next word chosen from "Current RD+" column Table 2.7.
8B10B
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2.11.2 8B10B Decoder
8B10B decoder performs reverse process 8B10B encoder. 8B10B decoder converts each 10-bit word back into 8-bit byte using code conversion tables defined IEEE 802.3z shown Table abbreviated form) Table 2.8. 8B10B decoder also checks running disparity incoming word insure that correct. codeword error results 8B10B decoder detects following:
word that valid (does appear Table 2.7) ordered that valid (does appear Table 2.8) error running disparity
Packets with codeword errors normally discarded. Refer Section 2.13, "Packet Discard" more details discards. Clearing DIS_CWRD "Register 8-Configuration Section 4.3.9, programs controller discard packet with codeword errors. Table
Code Symbol /C1/
Defined Ordered Sets
Begin flip2
Description Link Configuration
Codes /K28.5/1 /D21.5/ config_word1 config_word2 /K28.5/1 /D2.2/ config_word1 config_word2 Alternating /C1/ /C2/ /K28.5/ /D5.6/ /K28.5/ /D16.2/ /I1/ /I2/
/C2/
Link Configuration
same2
/I1/ /I2/
Link Configuration Idle Idle Idle
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Functional Description
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Table
Code Symbol
Defined Ordered Sets (Cont.)
Begin same same same same
Description Start packet delimiter (SPD) packet delimiter (EPD) Error (void)
Codes /K27.7/ /K29.7/ /K23.7/ /K30.7/
config_word contain 16-Bit AutoNegotiation data word. AutoNegotiation section details. determined characters only, config_word.
2.11.3 Start Packet
unique start packet delimiter (SPD) indicates start packet. consists single code inserted beginning packet place first preamble octet, defined IEEE 802.3z shown Figure 2.3. code defined Table 2.8. transmit 8B10B section inserts code beginning each transmit packet place first word preamble. receive 8B10B section constantly monitors incoming bitstream. code detected, start packet indication given receive MAC, preamble octet substituted place code beginning packet. 8B10B receiver detects transition from idle pattern (/I/ code stream) nonidle pattern without intervening code, packet assumed have SPD. Packets with normally discarded codeword errors. Refer Section 2.13, "Packet Discard" more information about discards. Clearing DIS_CWRD "Register 8-Configuration Section 4.3.9, programs controller discard packets with codeword errors.
8B10B
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2.11.4 Packet
Packet Delimiter, referred indicates packet. consists codes, /R/, inserted packet, defined IEEE 802.3z shown Table 2.8, also shown Figure 2.3. maintain synchronization proper word boundaries, outgoing packet must also have even number 10-bit words transmitted. packet number 10-bit words transmitted after /T/R/ codes, extra code inserted after /T/R/ (now /T/R/R/) meet even word requirement, defined IEEE 802.3z shown Figure 2.3. transmit 8B10B section appends either /T/R/ /T/R/R/ codes each transmit packet. receive 8B10B section constantly monitors incoming bitstream. /T/R/ codes detected, packet indication given receive MAC, /T/R/ /T/R/R/ codes stripped from packet. 8B10B receiver detects transition from nonidle pattern idle pattern (/I/ code stream) without intervening /T/R/ codes, packet assumed have EPD. Packets with discarded controller programmed. Refer Section 2.13, "Packet Discard" more details discards. Clearing DIS_CWRD "Register 8-Configuration Section 4.3.9, programs controller discard packets with errors.
2.11.5 Idle
interpacket time filled with continuous stream codes referred idle pattern. idle pattern consists continuous stream /I2/ codes, defined IEEE 802.3z shown Figure 2.3. running disparity during idle defined negative. running disparity after last code packet positive, single /I1/ code must transmitted first idle code make running disparity negative. subsequent idle codes must /I2/, defined IEEE 802.3z shown Figure 2.3. /I1/ /I2/ codes defined Table 2.8. transmit 8B10B section inserts continuous stream /I1/I2/I2/I2/.or /I2/I2/I2/I2/.codes between packets.
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Functional Description
Copyright 2000-2001 Logic Corporation. rights reserved.
receive 8B10B section constantly monitors incoming bitstream. /I2/ /I1/ code detected, packet indication given receive /I1/ /I2/ codes stripped from packet.
2.11.6 Receive Word Synchronization
order correctly decode incoming encoded data, 8B10B receiver must identify word boundaries incoming data stream. process detecting these word boundaries referred word synchronization. receiver uses state machine compatible with algorithm defined IEEE 802.3z acquire maintain word synchronization. comma code used acquire maintain receive word synchronization, specified IEEE 802.3z. comma code consists unique 7-bit pattern that only appears defined ordered sets shown Table 2.8, comma code does appear normal data words across data word boundaries. When 8B10B receiver lost word synchronization, EN_CDET asserted signal external device. Reading RSYNC "Register 11-Status Section 4.3.12, also determines word synchronization.
2.11.7 AutoNegotiation
AutoNegiotation algorithm uses ordered sets, defined Table 2.8, configure link correct operation. Refer Section 2.15, "AutoNegotiation" more details this process.
2.12 10-Bit Interface
10-bit interface standardized interface between 8B10B section external physical layer device. 10-bit interface meets requirements outlined IEEE 802.3z. controller directly connect, without external logic, physical layer device that also complies with IEEE 802.3z 10-bit interface specifications. 10-bit interface frame format defined IEEE 802.3z shown Figure 2.3.
10-Bit Interface
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10-bit interface consists signals follows:
transmit data output bits (TX[9:0]) Transmit clock output (TBC) receive data input bits (RX[9:0]) receive clock inputs (RBC0 RBC1) Comma detect enable output (EN_CDET) Loopback output (EWRAP) Receiver lock output (LCK_REFn)
2.12.1 Data Format Order
format order data word TX[9:0] RX[9:0] relationship frame system interface data words shown Figure 2.3. Note that Figure assumes controller Little Endian format (default). controller Endian format, byte order system interface data word reversed. Section 2.6, "System Interface" more details.
2.12.2 Transmit
transmit side, output clock generated from TCLK input clock runs continuously MHz. Data TX[9:0] clocked controller rising edge clock output.
2.12.3 Receive
receive side, RX[9:0] data clocked rising edges RBC[1:0] input clocks. RBC1 RBC0 required frequency 62.5 180° phase. data RX[9:0] clocked effective using alternate rising edges RBC[1:0] clocks latch data RX[9:0]. incoming data RX[9:0] also required word aligned RBC1 clock, (the words that contain comma codes must clocked with RBC1 clock, specified IEEE 802.3z).
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Functional Description
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comma detect output, EN_CDET, asserted when receiver 8B10B section lost word synchronization.Setting CDET "Register 9-Configuration Section 4.3.10, also asserts EN_CDET. EN_CDET output used enable synchronization process external physical layer device. controller does have designated standardized comma detect input, COM_DET, because receive 8B10B section necessary logic acquire word synchronization from contents receive data stream alone.
2.12.4 Lock Reference
Setting LCKREFn "Register 9-Configuration Section 4.3.10, exclusively controls LCK_REFn output. This output typically used enable locking process external physical layer device.
2.12.5 Loopback
Setting EWRAP "Register 9-Configuration Section 4.3.10, exclusively controls EWRAP output. This output typically used enable loopback function external physical layer device. When EWRAP asserted, signal detect input pin, from external physical layer device unknown state. counteract this, SD_EN Register "Configuration should also cleared when EWRAP assert set.
2.12.6 Signal Detect
There additional signal detect input pin, which indicates controller that receive data detected RXD[9:0] contains valid data. asserted, input data assumed valid receive 8B10B section unaffected. deasserted, data assumed invalid receive 8B10B section forced into loss sync state. Although part IEEE-defined 10-bit interface, typically sourced from external physical layer device. controller powers with disabled affect receive word synchronization state machine). enable pin, SD_EN must "Register 9-Configuration Section 4.3.10.
10-Bit Interface
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There also status "Register 11-Status Section 4.3.12, which reflects state input pin. HIGH forced also forced
2.12.7 Disable
transmit side 10-bit interface disabled TBC_DIS "Register 10-Configuration Section 4.3.11. When this set, TX[9:0] outputs placed high-impedance state.
2.13 Packet Discard
controller programmed discard receive transmit packets when certain error conditions detected. detection these error conditions occur MAC, FIFO, 8B10B sections.
2.13.1 Transmit Discards
Transmit packets automatically discarded certain error conditions detected. These error conditions described Table 2.9. When discard error detected transmit packet, remaining data that packet being input from system interface ignored, code appended packet indicate error remote station, TXDC asserted packet being input from system interface when discard occurred. Table Transmit Discard Conditions
Description FIFO empty. Packet transmission 8B10B halted. Partially transmitted packet terminated with code, followed normal codes. FIFO full. more data accepted from system interface. Partially transmitted packet terminated with code, followed normal codes.
Discard Condition Transmit FIFO Underflow
Transmit FIFO Overflow
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Functional Description
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2.13.2 Receive Discards
Receive packets discarded error conditions listed Table 2.10 detected. discard behavior dependent whether packet being output system interface when discard condition detected. packet containing error being output system interface when discard condition detected internal discard) packet discarded, (all data from packet containing error flushed from receive FIFO). packet containing error being output system interface when discard condition detected external discard) RXDC asserted indicate error condition. Asserting RXABORT setting AUTORXAB "Register 9-Configuration Section 4.3.10, automatically discards packet. both internal external discarded packets, appended status word updated reflect discard error condition. Table 2.10 Receive Discard Conditions
Description Receive FIFO full. more data accepted from 8B10B PCS. Receive packet error. Receive packet less than bytes, exclusive preamble SFD. Receive packet greater than maximum packet size, exclusive preamble SFD. Receive packet contains least word with 8B10BPCS coding error.
Discard Condition Receive FIFO overflow error Undersize packet Oversize packet codeword error
RXABORT asserted RXABORT asserted while receive packet read system interface. process flushing receive packet with RXABORT requires extra SCLK cycles equal (packet length bytes)/8
Each receive discard conditions individually removed discard condition appropriately clearing appropriate discard "Register 8-Configuration Section 4.3.9, associated with corresponding condition. When these bits cleared, packet that afflicted with error condition indicated that discarded.
Packet Discard
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controller programmed send status words discarded packets receive FIFO. Section 2.14, "Receive Status Word" more details status word configuration. Note: Receive FIFO underflow listed discard condition Table 2.10, (packets discarded when corrupted receive FIFO underflow). However, receive FIFO underflow does cause assertion RXDC.
2.13.3 Discard Output Indication
When discard condition detected packet being received transmitted over system interface, TXDC RXDC output pins asserted indicate that discard error detected. TXDC RXDC normally latched HIGH when discard takes place. Asserting CLR_TXDC CLR_RXDC clearing pins, clears TXDC RXDC outputs.
2.13.4 AutoClear Mode
Programming controller AutoClear mode automatically self clears TXDC RXDC pins. program controller AutoClear mode, AUTOCLR "Register 9-Configuration Section 4.3.10. When controller AutoClear mode, TXDC RXDC automatically cleared three SCLK cycles after next packet occurs.
2.13.5 AutoAbort Mode
When AutoAbort mode enabled controller also automatically abort current packet system interface receive FIFO when discard condition detected RXDC asserted. AUTORXAB "Register 9-Configuration Section 4.3.10, enable AutoAbort mode.
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Functional Description
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2.14 Receive Status Word
32-bit status word appended each good receive data packet stored receive FIFO. This status word contains byte count error information receive data packet.
2.14.1 Format
format status word shown Table 2.11. upper sixteen bits contain actual byte count packet lower sixteen bits contain status information related packet. Note that endian select affects byte order status word same that affects normal data byte order system interface. byte count value status word (upper sixteen bits) total number actual bytes received packet minus preamble, SFD, bytes. byte count independent whether receive stripped preamble CRC. packet overflows receive FIFO, byte count stops counting moment that receive FIFO overflow been detected remaining bytes incoming packet counted.
Table 2.11
RXD31
Receive Status Word Definition
RXD16 BC[15:0]
RXD15 RESERVED MPKT CWRD OSIZE USIZE OVFL
RXD0
Symbol BC[15:0] MPKT
Name Byte count Multiple packet reject Codeword error
Definition Contains actual byte count receive packet Reserved FIFO full multiple consecutive packets were discarded. Status word indicates error condition first packet discarded group. Receive packet coding error
Position RXD[31:0]1 RXD[31:16] RXD[15:6] RXD5
CWRD
RXD4
Receive Status Word
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Symbol OSIZE USIZE OVFL
Name Oversize packet
Definition
Position RXD[31:0]1
Receive packet greater than maximum size RXD3 RXD2 RXD1 RXD0
Undersize packet Receive packet less than minimum size Receive FIFO overflow error Receive FIFO full received additional data Receive packet error
This byte order little endian format. endian format reverses this byte order.
2.14.2 Append Options
status word normally appended good receive packets. However, controller also programmed store status word receive FIFO discarded packets well append status word good (nondiscarded) packets. controller also programmed append status word all. Setting STSWRD [1:0] bits "Register 7-Configuration Section 4.3.8, select appropriate status word option.
2.14.3 Status Word Discarded Packets
When controller programmed status word discarded packets, only status word stored receive FIFO each discarded packet. status word discarded packet contains indication error that caused discard. receive FIFO full more than consecutive packet discarded, then more status word stored receive FIFO next consecutive group discarded packets. status word indicating that multiple status words multiple packets have been discarded. When status word multiple discard set, other status bits reflect status second discarded packet only.
2.14.4 Status Word RXABORT Packets
When RXABORT asserted, both packet data associated status word normally flushed from receive FIFO. Setting RXAB_DEF "Register 9-Configuration Section 4.3.10, programs controller allow RXABORT discard packet only leave status word discarded packet receive FIFO.
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Functional Description
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2.15 AutoNegotiation
AutoNegotiation algorithm negotiation sequence between stations over 10-bit interface that establishes good link between stations, configures both stations same mode operation. AutoNegotiation algorithm controller meets specifications defined IEEE 802.3z. AutoNegotiation uses stream ordered sets pass AutoNegotiation data word from remote station. ordered stream consists alternating sequence /C1/ /C2/ ordered sets. /C1/ /C2/ ordered sets contain unique code words plus 16-bit AutoNegotiation data word, defined IEEE 802.3z shown Figure 2.6. Figure
K28.5 D21.5 <Bits[0:7]> <Bits[8:15]> K28.5 D2.2 <Bits[0:7]> <Bits[8:15]> ABCDEFGH abcdefghij TX[0] RX[0] TX[9] RX[9] Codes Codes PHY. INT. PHY. INT. From Registers From Registers
AutoNegotiation Data Format
Note: Means Encoded
AutoNegotiation
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following conditions iniatiate AutoNegotiation algorithm:
Controller reset AutoNegotiation restart ordered sets received from remote Controller reacquires receive word synchronization
After negotiation been initiated controller uses contents "Register 21-AutoNegotiation Base Page Transmit," Section 4.3.18, advise remote device capabilities. remote device does same, capabilities read back from remote device stored AutoNegotiation Base Page Receive register. controller's capabilities then externally compared capabilities received from remote device, device then configured compatible mode operation. controller also next page capability. complete description AutoNegotiation algorithm controller, refer IEEE 802.3z specification, clause 8B10B receiver lost word synchronization, controller needs acquire synchronization before AutoNegotiation words successfully received. While loss synchronization state, transmitter outputs ordered sets with remote fault bits RF[1:0] 0b01 indicate link failure condition remote end. After 8B10B receiver acquired word synchronization, negotiation process ready begin.
2.15.1 Next Page
controller also next page capability defined IEEE 802.3z. next page feature allows transfer additional 16-bit data words between stations during negotiation sequence addition original base page message information. These additional 16-bit data words referred next pages contain arbitrary data. next page transmitted, must "Register 21-AutoNegotiation Base Page Transmit," Section 4.3.18, indicate this remote station. Conversely, remote station wants send next page controller, sets base page, which stored "Register 22-AutoNegotiation Base Page Receive," Section 4.3.19. next pages transmitted remote station have written into "Register 23-AutoNegotiation Next Page
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Functional Description
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Transmit," Section 4.3.20, order transmitted. next pages received from remote station stored "Register AutoNegotiation Next Page Receive," Section 4.3.21. Both stations must have next page functionality successful next page transfer. Next page operation complicated; refer IEEE 802.3z full description this feature works Chapter Registers description associated registers. There status bits related next page operation. Section 2.15.2, "Negotiation Status" details.
2.15.2 Negotiation Status
There bits "Register 11-Status Section 4.3.12, that indicate status AutoNegotiation. These bits summarized Table 2.12 described more detail Status register description. Some bits related AutoNegotiation programmed cause interrupt, described Status register description. Table 2.12
Register
AutoNegotiation Status Bits
Name LINK AN_NP AN_TX_NP AN_RX_NP AN_RX_BP AN_RMTRST
What Indicates Link autoNegotiation completed next page been exchanged next page been transmitted next page been received Base page been received AutoNegotiation restarted remote station
2.15.3 AutoNegotiation Restart
Setting ANRST "Register 7-Configuration Section 4.3.8, restarts AutoNegotiation algorithm. ANRST clears itself automatically after AutoNegotiation process starts transmitting ordered sets.
AutoNegotiation
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2.15.4 AutoNegotiation Enable
Setting AN_EN "Register 9-Configuration Section 4.3.10, enables AutoNegotiation algorithm. When AutoNegotiation disabled transmitter will output ordered sets.
2.15.5 Link Indication
successful completion AutoNegotiation process (and definition receiver also acquired word synchronization) indicated asserting LINKn LOW, setting LINK "Register 11-Status Section 4.3.12. LINK output drive from well drive another digital input.
2.16 Flow Control
Flow control causes remote station temporarily halt sending packets order prevent packet loss congested system. controller uses control frames flow control, according IEEE 802.3x specifications. Refer Section 2.17, "MAC Control Frames" more details control frame flow control scheme.
2.17 Control Frames
control frames packets that pass signaling information between stations specified IEEE 802.3, Clause control frames used primarily flow control. control frames differentiated from other packets because they have unique value 0x8808 length/type field. control frames have same format normal Ethernet packets, except data field, consists opcode field parameter field. opcode field contains opcode command parameter field contains value associated with opcode command. only opcode command defined date IEEE 802.3x pause opcode; parameter field pause opcode defines pause time. control frames with pause opcode, referred pause frames, only allowed have destination address equal specific reserved multicast address address receive station itself. value reserved multicast address 0x0180C2000001.
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Functional Description
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controller normally treats control frames according IEEE 802.3, clause algorithm. When receive detects control frame with pause opcode destination address equals reserved multicast address address stored Address registers, then transmitter paused time equal number pause times specified parameter field. Each unit pause time equals bits (512 Gigabit Ethernet). pause frame received while another packet being transmitted, transmission completed current packet being transmitted, then transmitter paused. there other packets transmit FIFO their transmission delayed until pause timer expired. control frames normally passed into receive FIFO; they terminated receive MAC. controller also incorporated some additional features facilitate control frame operation. These features described following sections.
2.17.1 Automatic Pause Frame Generation
Pause frames automatically generated when either FCNTRL asserted receive FIFO data exceeds control AutoSend threshold. These automatically generated pause frames, referred autogenerated pause frames, internally generated transmitted over 10-bit interface. reception receive pause frame does affect transmission autogenerated pause frames. Receive pause frames only inhibit transmission regular packets from transmit FIFO. packet transmission progress when autogenerated pause frame transmitted, controller waits until transmission that packet completed then transmits autogenerated pause frame before other subsequent packets FIFO transmitted. When first autogenerated pause frame begins transmission, internal timer starts whose value equal pause_time value pause frame (and obtained from "Register Flow Control Section 4.3.17). FCNTRL still asserted control frame AutoSend threshold still exceeded when internal pause timer expires, another autogenerated pause frame transmitted. This process continues long FCNTRL remains asserted control frame AutoSend threshold exceeded.
Control Frames
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When FCNTRL deasserted control AutoSend threshold exceeded, last autogenerated pause frame pause_time transmitted. compensate latency, internal pause timer internally shortens itself units from value programmed "Register 20-Flow Control Section 4.3.17. Clearing MCENDPS "Register 19-Flow Control Section 4.3.16 programs controller eliminate last autogenerated pause frame with pause_time structure autogenerated pause frame described Figure 2.7. Note: source address pause_time parameter fields programmable through internal registers shown Figure 2.7.
FCNTRL control AutoSend threshold individually disabled, (they programmed longer initiate transmission autogenerated pause frames). FCNTRL enabled default. Setting FCNTRL_DIS "Register Configuration Section 4.3.10, disables FCNTRL pin. control AutoSend disabled default. Appropriately setting control MCASND[3:0] bits "Register 19-Flow Control Section 4.3.16, enables control AutoSend.
2.17.2 Transmitter Pause Disable
Receive pause frames normally pause transmitter. Clearing MCNTRL "Register 19-Flow Control Section 4.3.16, programs controller pause transmitter. When MCNTRL received pause frames affect transmitter.
2.17.3 Pass Through FIFO
Receive pause frames normally discarded passed receive FIFO. Appropriately setting MCPASS[1:0] bits "Register 19-Flow Control Section 4.3.16, allows receive pause frames passed receive FIFO. These bits allow either control frames, nonpause frames only, pause frames only passed receive FIFO.
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Functional Description
Copyright 2000-2001 Logic Corporation. rights reserved.
Figure
Autogenerated Pause Frame Format
10-Bit Interface
10101010 10101010 10101010 10101010 10101010 10101010 10101010 10101011 10000000 00000001 01000011 00000000 00000000 10000000 A[0:7]REG2 A[8:15]REG2 A[16:23]REG1 A[24:31]REG1 A[32:39]REG0 A[40:47]REG0 00010001 00010000 00000000 10000000 P[8:15]REG20 P[0:7]REG20 00000000
/I2/ /I2/ D21.2 D21.2 D21.2 D21.2 D21.2 D21.2 D21.6 D1.0 D0.4 D2.6 D0.0 D0.0 D1.0 <A[0:7]REG2> <A[8:15]REG2> <A[16:23]REG1> <A[24:31]REG1> <A[32:39]REG0> <A[40:47]REG0> D8.4 D8.0 D0.0 D1.0 <P[8:15]REG20> <P[0:7]REG20> D0.0
PARAM DATA Bytes)
00000000 FCS[31:24] FCS[23:16] FCS[15:8] FCS[7:0]
D0.0 <FCS[31:24]> <FCS[23:16]> <FCS[15:8]> <FCS[7:0]> /I1/ /I2/ /I2/ /I2/
ABCDEFGH
Bytes Transmitted Notes: Means encoded /I1/ /I2/, depends running disparity Bits Transmitted abcdefghij TX[0] RX[0] TX[9] RX[9] 10-Bit Interface
Control Frames
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2.17.4 Reserved Multicast Address Disable
Receive pause frames normally rejected invalid they have reserved multicast address destination address field. Setting MCFLTR "Register 19-Flow Control Section 4.3.16, programs controller accept receive pause frames regardless contents destination address field. When this cleared, value destination address field accepted valid address.
2.17.5 Control Frame AutoSend
level data receive FIFO also triggers transmission autogenerated pause frames. This feature referred control frame AutoSend. Appropriately setting MCASEND[3:0] bits "Register 19-Flow Control Section 4.3.16, enable AutoSend feature. When control frame AutoSend enabled, autogenerated pause frames transmitted when receive FIFO data exceeds programmable threshold level called control AutoSend threshold. control AutoSend threshold with four MACSEND bits "Register 19-Flow Control Section 4.3.16. automatic pause frame generation mechanism described more detail Section 2.17.1, "Automatic Pause Frame Generation".
2.18 Reset
controller four resets which described Table 2.13. controller should ready normal operation after reset sequence been completed that bit.
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Functional Description
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Table 2.13
Name Controller Reset
Reset Description
Initiated RESETn asserted Register (Configuration Reset Action Reset datapath Flush transmit FIFO Flush receive FIFO Reset bits default values Reset counters
Transmit Reset
TXRST Register (Configuration
Reset transmit data path Flush transmit FIFO Reset counters
Receive Reset
RXRST Register (Configuration
Reset receive data separate path Flush receive FIFO Reset counters
AutoNegotiation Restart Counter Reset
ANRST Register (Configuration CTRRST Register (Configuration
Starts AutoNegotiation sequence Reset counters
2.19 Counters
controller management counters. Each counter tabulates number times specific event occurs. complete list counters along with their definitions shown Table 2.14. described Chapter Registers.These counters provide necessary statistics completely support following specifications:
RMON Statistics Group (IETF RFC1757) SNMP Interfaces Group (IETF RFC1213 1573) Ethernet-Like (IETF RFC1643) Ethernet (IEEE 802.3z, clause
Counters
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counters bits wide. obtain each 32-bit counter result, perform read operation over register interface. address locations each counter shown both Table 2.14 Table 4.2. 16-bit register locations associated with each 32-bit counter, register with lower value address always contains least significant bits counter result. Thus, lower value address register counter LSB; higher value address register counter MSB. When counter read operation initiated, 32-bit counter result accessed transferred internal 16-bit holding registers. These holding registers freeze store counter result duration read operation, while allowing internal counter continue increment needed. When counter read, count can, under program control, automatically reset zero remain unchanged. Counters programmed either stop counting when they reach their maximum count roll over. Burst reading only supported high value address same counter. read value multiple counters, either REGCSn REGRDn must deasserted then reasserted. Each counter associated status that when counter becomes half full. These status bits individually programmed cause interrupt. counter Table 2.14 includes packet octet statistics transmit receive sides. RMON specification literally states that packet octet counters should only tabulate received information. This sometimes interpreted mean both transmitted received information because Ethernet originally shared media protocol. such, packet octet counters both transmit receive available controller, transmit receive packet octet counts summed together desired. exact correspondence actual objects from IETF IEEE specifications actual controller counters locations described Chapter Application Information.
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Functional Description
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Table 2.14
Counter Definition
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Size (Bits)
RMON Statistics Group (RFC 1757)
Packets with receive FIFO overflow error. Bytes, exclusive preamble, good packets. Bytes packets with excluded.1 0b10000000 0b10000001
etherStatsDropEvents
etherStatsOctets
0b10000010 0b10000011 0b10000100 0b10000101 0b10000110 0b10000111 0b10001000 0b10001001
etherStatsPkts
packets, good bad.1
etherStatsBroadcastPkts
Broadcast packets, good only.1
etherStatsMulticastPkts
Multicast packets, good only.1 Packets legal-length with error alignment error. There alignment errors 8B10B Gigabit Ethernet, this counter will only count errors legal length packets. Packets length bytes with other errors. Packets length Max_Packet_Length with other errors. Packets length bytes with error alignment error. There alignment errors 8B10B Gigabit Ethernet, this counter will only count errors with length Packets length Max_Packet_Length with error alignment error.
etherStatsCRCAlignErrors
0b10001010 0b10001011 0b10001100 0b10001101 0b10001110 0b10001111
etherStatsUndersizePkts
etherStatsOversizePkts
etherStatsFragments
0b10010000 0b10010001
etherStatsJabber
There jabber function Gigabit Ethernet, this counter undefined.
0b10010010 0b10010011
Counters
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Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
asserted more collsions occurred.
Size (Bits)
etherStatsCollisions
Since controller Full Duplex only, this counter undefined. Packets length bytes, good bad.1 Packets length between 65-127 bytes, inclusive, good bad.1 Packets length between 128-255 bytes, inclusive, good bad.1 Packets length between 256-511 bytes, inclusive, good bad.1 Packets length between 512-1023 bytes, inclusive, good bad.1 Packets length between 1024 Max_Packet_Length, inclusive, bad.1 Bytes, exclusive preamble, good packets.1
0b10010100 0b10010101 0b10010110 0b10010111 0b10011000 0b10011001 0b10011010 0b10011011 0b10011100 0b10011101 0b10011110 0b10011111 0b10100000 0b10100001 0b10100010 0b10100011 0b10100100 0b10100101 0b10100110 0b10100111 0b10101000 0b10101001 0b10101010 0b10101011 0b10101100 0b10101101 0b10101110 0b10101111 0b10110000 0b10110001
etherStatsPkts64Octets
etherStatsPkts65to127Octets
etherStatsPkts128to255Octets
etherStatsPkts256to511Octets
etherStatsPkts512to1023Octets
etherStatsPkts1024to1518Octets
etherStatsOctets_TX
etherStatsPkts_TX
packets, good bad.1
etherStatsBroadcastPkts_TX
Broadcast packets, good only.1
etherStatsMulticastPkts_TX
Multicast packets, good only.1 Packets length bytes, good bad.1 Packets length between 65-127 bytes, inclusive, good bad.1 Packets length between 128-255, inclusive, good bad.1 Packets length between 256-511 bytes, inclusive, good bad.1
etherStatsPkts64Octets_TX
etherStatsPkts65to127Octets_TX
etherStatsPkts128to255Octets_TX
etherStatsPkts256to511Octets_TX
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Functional Description
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Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
0b10110010 0b10110011
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Packets length between 512-1023 bytes, inclusive, good bad.1 Packets length between 1023 Max_Packet _Length, inclusive, good bad.1
Size (Bits)
etherStatsPkts1024to1518Octets_
0b10110100 0b10110101
SNMP Interfaces Group (RFC 1213 1573)
Bytes, including preamble, good packets. 0b10110110 0b10110111 0b10111000 0b10111001
ifInOctets
ifInUcastPkts
Unicast packets, good only. Multicast packets, good only. Equivalent "etherStatsMulticastPkts" Broadcast packets, good only. Equivalent "etherStatsBroadcastPkts" Broadcast multicast packets, good only. Equivalent "etherStatsBroadcastPkts etherStatsMulticastPkts" Packets with receive FIFO overflow error. Equivalent "etherStatsDropEvents" packets, only. Equivalent "etherStatsCRCAlignError etherStatsUndersizePkts etherStatsOversizePkts" Bytes, including preamble, good packets.
ifInMulticastPkts
Ctr.
ifInBroadcastPkts
Ctr.
ifInNUcastPkts
Ctr.
ifInDiscards
Ctr.
ifInErrors
Ctr. 0b10111010 0b10111011 0b10111100 0b10111101 0b10111110 0b10111111
ifOutOctets
ifOutUcastPkts
Unicast packets, good bad.
ifOutMulticastPkts
Multicast packets, good bad.
Counters
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Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
0b11000000 0b11000001
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Size (Bits)
ifOutBroadcastPkts
Broadcast packets, good bad. Broadcast multicast packets, good bad. Equivalent "ifOutMulticastPkts ifOutBroadcastPkts" Packets with transmit FIFO underflow error. Packets, only, exclusive legal-length errors.
ifOutNUcastPkts
Ctr. 0b11000010 0b11000011 0b11000100 0b11000101
ifOutDiscards
ifOutErrors
Ethernet-Like Group
(RFC 1643)
Packets with alignment error only. There alignment errors 8B10B Gigabit Ethernet, this counter undefined. Packets with error only. Equivalent "etherStatsCRCAlignErrors" Packets successfully transmitted after only collision (ie: attempt value dot3StatsSingleCollisionFrames Since controller Full Duplex only, this counter undefined. Packets successfully transmitted after more than collision (ie: 2<attempt value<16). Since controller Full Duplex only, this counter undefined. Number times asserted. dot3StatsSQETestErrors There Gigabit Ethernet, this counter undefined. Packets deferred, i.e. packets whose transmission delayed busy medium, first attempt only. dot3StatsDeferredTransmissions Since controller Full Duplex only, this counter undefined. 0b11010000 0b11010001 0b11001110 0b11001111 0b11001100 0b11001101 0b11001010 0b11001011 0b11000110 0b11000111
dot3StatsAlignmentErrors
dot3StatsFCSErrors
Ctr.
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Functional Description
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Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Packets that encounter late collision, i.e. encountered collisions more than 512-bit times into transmitted packet. late collision counted twice: collision late collision.
Size (Bits)
dot3StatsLateCollisions
Since controller Full Duplex only, this counter undefined. Packets successfully transmitted after more than collisions (ie: attempt value=16).
0b11010010 0b11010011
dot3StatsExcessiveCollisions
Since controller Full Duplex only, this counter undefined. Packets with transmit FIFO underflow error. Equivalent "ifOutDiscards" Carrier sense dropout errors, i.e. number times that carrier sense asserted deasserted during packet transmission, without collision. This counter only incremented once packet, regardless number dropout errors packet.
0b11010100 0b11010101
Ctr.
dot3StatsCarrierSenseErrors
There loopback 8B10B Ethernet, this counter undefined. Packets length Max_Packet_Length with other errors. Equivalent "etherStatsOversizePkts" Packets with receive FIFO overflow error. Equivalent "etherStatsDropEvents"
0b11010110 0b11010111
dot3StatsFrameTooLongs
Ctr.
Ctr.
Ethernet
(IEEE 802.3z Clause
packets, good only. Equivalent "etherStatsPkts_TX ifOutErrors" Packets successfully transmitted after only collision (ie: attempt value Equivalent Ctr. through
aFramesTransmittedOK
aSingleCollisionFrames
Ctr.
Counters
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Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Packets successfully transmitted after more than collision (ie: 2<attempt value <16). Equivalent packets, good only. Equivalent "ifInUcastPkts etherStatsBroadcastPkts etherStatsMulticastPkts" Packets with error only. Equivalent "dot3StatsFCSErrors" Packets with alignment error only. Equivalent "dot3StatsAlignmentErrors" Bytes, exclusive preamble, good packets only. Packets deferred, i.e. packets whose transmission delayed busy medium, first attempt only. Equivalent Packets that encounter late collision, i.e. encountered collisions more than 512-bit times into transmitted packet. late collision counted twice, collision late collision. Equivalent "dot3StatsLateCollisions" Packets successfully transmitted after more than collisions (ie: attempt value=16). Equivalent "dot3StatsExcessiveCollisions" Packets with transmit FIFO underflow error. Equivalent "ifOutDiscards"
Size (Bits)
aMultipleCollisionFrames
Ctr.
aFramesReceivedOK
Ctr.
aFrameCheckSequenceErrors
Ctr.
aAlignmentErrors
Ctr. 0b11011000 0b11011001
aOctetsTransmittedOK
aFramesWithDeferredXmissions
Ctr.
aLateCollisions
Ctr.
aFrameAbortedDueToXSCollisions
Ctr.
aFrameAbortedDueToIntMACXmit Error
Ctr.
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Functional Description
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Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Carrier sense dropout errors, i.e. number times that carrier sense asserted deasserted during packet transmission, without collision. This counter only incremented once packet, regardless number dropout errors packet. Equivalent "dot3StatsCarrierSenseErrors" Bytes, exclusive preamble, good packets only. Packets with receive FIFO overflow error. Equivalent "etherStatsDropEvents" Multicast packets, good only. Equivalent "etherStatsMulticastPkts_TX" Broadcast packets, good only. Equivalent "etherStatsBroadcastPkts_TX" Packets with excessive deferral, i.e. packets waiting transmission longer than packet times.
Size (Bits)
aCarrierSenseErrors
Ctr. 0b11011010 0b11011011
aOctetsReceivedOK
aFramesLostDueToIntMACRcvr Error
Ctr.
aMulticastFrameXmittedOK
Ctr.
aBroadcastFramesXmittedOK
Ctr.
aFramesWithExcessiveDefferal
Since controller Full Duplex only, this counter undefined. Multicast packets, good only. Equivalent "etherStatsMulticastPkts" Broadcast packets, good only. Equivalent "etherStatsBroadcastPkts" Packets legal-length whose actual length different from length/type field value. Packets with length/type field value Max_Packet_Length. Packets length Max_Packet_Length with other errors. Equivalent "etherStatsOversizePkts"
0b11011100 0b11011101
aMulticastFramesReceivedOK
Ctr.
aBroadcastFramesReceivedOK
Ctr.
aInRangeLengthErrors
0b11011110 0b11011111 0b11100000 0b11100001
aOutOfRangeLengthField
aFrameTooLongErrors
Ctr.
Counters
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Table 2.14
Counter Definition (Cont.)
Counter Description Register Address REGAD[7:0] (Low/High)
Counter Number
Counter Name (MIB Object Name)
RX/TX
Definition
Number times asserted. Equivalent "dot3StatsSQETestError" more symbol errors received from during packet reception, exclusive collision. This counter only incremented once packet, regardless number symbol errors that packet. Valid Control packets. Equivalent Valid Control packets. Equivalent "apauseMACCtrlFramesReceived" Valid Control packets with non-pause opcode. Valid Control packets with pause opcode. Valid Control packets with pause opcode.
Size (Bits)
aSQETestErrors
Ctr.
aSymbolErrorDuringCarrier
0b11100010 0b11100011
aMACControlFramesTransmitted
Ctr.
aMACControlFramesReceived
Ctr. 0b11100100 0b11100101 0b11100110 0b11100111 0b11101000 0b11101001
aUnsupportedOpcodesReceived
apauseMACCtrlFramesTransmitted
apauseMACCtrlFramesReceived
Footnotes packet legal-length error, error, receive FIFO overflow, symbol error. Where: Error with integral number octets. Alignment Error with nonintegral number octets. Symbol Error invalid codeword /V/. packet legal-length error, transmit FIFO underflow. Legal-length packet between Max_Packet_Length bytes. Preamble included length count. Max_Packet_Length counters programmed either 1518, 1522, 1535, unlimited bytes. 1518 default both transmit receive. counter result stored 16-bit registers. Thus, there register addresses each counter. registers given counter, register with lower value address contains least significant counter bits. RMON specs explicitly states that packet octet counters should only tabulate received information. This sometimes interpreted mean both transmitted received information because Ethernet originally shared media. such, transmit packet octet counters also available counters 18-27 summed with receive packet octet counts desired.
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Functional Description
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2.19.1 Counter Half Full
Each 32-bit counter half-full status output associated with half-full bits stored "Register 112-115-Counter Half Full 1-4," Section 4.3.23. half-full when counter value reaches 0x80000000 (MSB goes from when counter becomes half full. counter half-full bits latch themselves when they set. Each stays latched until either read counter register with which associated read. Counter half-full bits also interrupt bits (the setting counter half-full programmed cause assertion interrupt pin, REGINT). When read clears counter half-full bit, interrupt also cleared. Note: REGINT stays asserted until interrupt bits cleared.
Each counter half-full individually programmed assert assert) REGINT pin. Setting appropriate mask associated with counter half full "Registers 120-123-Counter Half Full Mask 14," Section 4.3.24, programs controller mask (disable) interrupt caused corresponding counter half full detect bit.
2.19.2 Counter Reset Read
read operation counter does normally affect counter values. However, setting CTR_RD "Register 9-Configuration Section 4.3.10, programs counter automatically reset zero when read. When CTR_RD set, counter cleared whenever 16-bit counter registers associated with 32-bit counter read. internal holding register stores entire 32-bit counter result that result correctly read long successive 16-bit counter register reads performed from same counter. order read cleared value, read operation needs deasserted then reasserted (i.e., REGCSn REGRDn). When CTR_RD cleared (default), read does affect count counter, long counter maximum count. counter maximum count, count always reset when counter read.
Counters
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2.19.3 Counter Rollover
Counters normally roll over zero when they exceed their maximum count, (receive increment when counter maximum count). counters programmed freeze stop counting once they reach their maximum count. Setting CTR_ROLL "Register Configuration Section 4.3.10, programs counters freeze when they reach their maximum count.
2.19.4 Counter Maximum Packet Size
maximum packet size used management counter statistics programmed four values. Setting CMXPKT[1:0] bits "Register 10-Configuration Section 4.3.11, select maximum packet size. This selection described register descriptions those registers also summarized Table 2.15. bits Table 2.15 affect maximum packet size counters only; maximum packet size section described Section 2.8, "Receive MAC". Table 2.15 Counter Maximum Packet Size Selection
Maximum Packet Size (bytes) Unlimited 1535 1522 1518
CMXPKT [1:0]
2.19.5 Counter Reset
Setting CTRRST "Register 7-Configuration Section 4.3.8, resets counters zero. Asserting controller reset pin, RESETn, also resets counters zero.
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Functional Description
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2.20 Loopback
enable diagnostic loopback mode, LPBK "Register 10-Configuration Section 4.3.11. When loopback mode enabled, transmit data input transmit system interface output from 8B10B encoder internally looped back into receive 8B10B decoder available read from receive system interface.
2.21 Test Modes
TEST reserved factory test, must tied normal operation. Asserting HIGH, sets inputs outputs high-impedance state. This intended controller board diagnostic testing.
Loopback
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2-60
Functional Description
Copyright 2000-2001 Logic Corporation. rights reserved.
Chapter Signal Descriptions
This chapter describes 8101/8104 Gigabit Ethernet Controller signals following sections:
Section 3.1, "System Interface Signals" Section 3.2, "10-Bit Interface Signals" Section 3.3, "Register Interface Signals" Section 3.4, "Micellaneous Signals" Section 3.5, "Power Supply Signals"
Figure diagram 8101/8104 signals.
8101/8104 Gigabit Ethernet Controller
Copyright 2000-2001 Logic Corporation. rights reserved.
Figure
8101/8104 Interface Diagram
SCLK TXENn TXD[31:0] TXBE[3:0] TXSOF TXEOF TXWM1n TXWM2n TXDC CLR_TXDC FCNTRL TXCRCn RXENn RXOEn RXD[31:0] RXBE[3:0] RXSOF RXEOF RXWM1 RXWM2 RXDC CLR_RXDC RXABORT TX[9:0]] RBC[1:0] RX[9:0] EN_CDET EWRAP LCK_REFn REGCSn REGCLK REGD[15:0] REGA[7:0] REGRDn REGWRn REGINT TCLK LINKn RESETn TEST
10-Bit Interface
System Interface
Register Interface
Miscellaneous
GND[30:0]
Ground
Signal Descriptions
Copyright 2000-2001 Logic Corporation. rights reserved.
System Interface Signals
This section describes 8101/8104 system interface signals. CLR_RXDC Clear RXDC Input When CLR_RXDC asserted, RXDC cleared. Wheh CLR_RXDC LOW, RXDC cleared. CLR_RXDC clocked rising edge system clock, SCLK. This only clears RXDC when AutoClear mode disabled. When AutoClear mode enabled, this ignored RXDC automatically cleared clock cycles after RXEOF asserted. CLR_TXDC Clear TXDC Input When CLR_TXDC HIGH, TXDC cleared. When CLR_TXDC LOW, TXDC cleared. TXDC clocked rising edge system clock, SCLK. This only clears TXDC when AutoClear mode disabled. When AutoClear mode enabled, this ignored TXDC automatically cleared clock cycles after TXEOF asserted. FCNTRL Flow Control Enable Input When FCNTRL HIGH, transmitter automatically transmits control pause frame. When FCNTRL LOW, controller resumes normal operation. FCNTRL clocked rising edge system clock, SCLK. Receive FIFO Data Abort Input When RXABORT asserted, packet being read RXD[31:0] aborted discarded. When LOW, packet aborted discarded. RXABORT clocked rising edge system clock, SCLK. Receive Byte Enable Output These outputs determine which bytes current data RXD[31:0] contain valid data. RXBE[3:0] clocked device rising edge system interface clock, SCLK.
RXABORT
RXBE[3:0]
System Interface Signals
Copyright 2000-2001 Logic Corporation. rights reserved.
RXD[31:0]
Receive Data Output This output contains 32-bit received data word that clocked rising edge system interface clock, SCLK. Receive Packet Discard Output When HIGH, device detects that current packet being output system interface error should discarded. When LOW, discard. Asserting RXABORT setting AUTORXAB "Register 9-Configuration Section 4.3.10, automatically discards packet being output. RXDC clocked rising edge system clock, SCLK. AutoClear mode enabled, this output latched HIGH stays latched until cleared with assertion CLR_RXDC pin. AutoClear mode enabled, this output latched HIGH automatically clears itself clock cycles after RXEOF asserted. RXDC also cleared with RXABORT programmed
RXDC
RXENn
Receive Enable Input This input must asserted active enable current data word clocked receive FIFO RXD[31:0]. RXENn clocked rising edge system interface clock, SCLK. Receive Frame Output This output asserted same clock cycle last word packet being read receive FIFO RXD[31:0]. RXEOF clocked device rising edge system interface clock, SCLK. Receive Output Enable Input When LOW, receive outputs active. When HIGH, receive outputs (RXD[31:0], RXBE[3:0], RXSOF, RXEOF) high-impedence. Receive Start Frame Output This output asserted same clock cycle first word packet being read receive FIFO RXD[31:0]. RXSOF clocked device rising edge system interface clock, SCLK.
RXEOF
RXOEn
RXSOF
Signal Descriptions
Copyright 2000-2001 Logic Corporation. rights reserved.
RXWM1
Receive FIFO Watermark Output When RXWM1 LOW, receive FIFO data less than equal receive FIFO watermark threshold. When HIGH, receive FIFO data greater than watermark. RXWM1 clocked rising edge system clock, SCLK. Data valid RXD[31:0] when either RXWM1 RXWM2 asserted, independent RXENn. Receive FIFO Watermark Output When RXWM2 LOW, receive FIFO data less than equal receive FIFO watermark threshold FIFO. When HIGH, receive FIFO data greater than watermark. RXWM2 clocked rising edge system clock, SCLK. Data valid RXD[31:0] when either RXWM1 RXWM2 asserted, independent RXENn. System Interface Clock Input This input clocks data transmit receive FIFOs TXD[31:0] RXD[31:0], respectively. system interface inputs outputs also clocked rising edge SCLK, with exception RXOEn. SCLK clock frequency must between 33-66 MHz. Transmit Byte Enable Input These inputs determine which bytes current 32-bit word TXD[31:0] contain valid data. TXBE[3:0] clocked into device rising edge system interface clock, SCLK. Transmit Enable Input When TXCRC LOW, calculated appended current packet being input system interface. When TXCRC HIGH, calculated. TXCRCn clocked rising edge system clock, SCLK, must asserted same SCLK clock cycle TXSOF. Transmit Data Input This input contains 32-bit data word that clocked into transmit FIFO rising edge system interface clock, SCLK.
RXWM2
SCLK
TXBE[3:0]
TXCRCn
TXD[31:0]
System Interface Signals
Copyright 2000-2001 Logic Corporation. rights reserved.
TXDC
Transmit Packet Discard Output When TXDC HIGH, controller detects that current packet being input system interface error, rest packet ignored. When LOW, packet discarded. TXDC clocked rising edge system clock. AutoClear mode enabled, this output latched HIGH stays latched until cleared with assertion CLR_TXDC pin. AutoClear mode enabled, this output latched HIGH automatically clears itself clock cycles after TXEOF asserted.
TXENn
Transmit Enable Input This input must enable current data word TXD[31:0] clocked into transmit FIFO. TXENn clocked rising edge system interface clock, SCLK. Transmit Frame Input This input must asserted same clock cycle last word packet being clocked TXD[31:0]. TXEOF clocked into device rising edge system interface clock, SCLK. Transmit Start Frame Input This input must asserted same clock cycle first word packet being clocked TXD[31:0]. TXSOF clocked into device rising edge system interface clock, SCLK. Transmit FIFO Watermark Output When TXWM1n HIGH, transmit FIFO data less than equal transmit FIFO watermark When LOW, transmit FIFO data above watermark. TXWM1n clocked rising edge system clock, SCLK. Transmit FIFO Watermark Output When TXWM2n HIGH, transmit FIFO data less than equal transmit FIFO watermark When LOW, transmit FIFO data above watermark. TXWM2n clocked rising edge system clock, SCLK.
TXEOF
TXSOF
TXWM1n
TXWM2n
Signal Descriptions
Copyright 2000-2001 Logic Corporation. rights reserved.
10-Bit Interface Signals
This section describes 8101/8104 10-Bit interface signals. EN_CDET Comma Detect Enable Output This output asserted when either receive 8B10B state machine loss synchronization state CDET "Register 9-Configuration Section 4.3.10. This output typically used enable comma detect function external physical layer device. Loopback Output Enable Output This output asserted whenever EWRAP "Register 9-Configuration Section 4.3.10. This output typically used enable loopback external physical layer device. Receiver Lock Output This output asserted whenever LCK_REFn "Register 9-Configuration Section 4.3.10. This output typically used enable receive lock-to-reference mechanism external physical layer. Receive Clock Input RBC[1:0] signals clock receive data into controller clock rising edge. RBC[1:0] 62.5 clocks, 180° phase, that clock data into controller RX[9:0] effective rate MHz. device acquire synchronization, comma code must input RXD[9:0] RBC1 rising edges. Receive Data Input These inputs contain receive data that clocked rising edges RBC[1:0]. Transmit Clock Output This output clock transmits data TX[0:9] rising edge. clock generated from TCLK.
EWRAP
LCK_REFn
RBC[1:0]
RX[9:0]
10-Bit Interface Signals
Copyright 2000-2001 Logic Corporation. rights reserved.
TX[9:0]
Transmit Data Output These interface outputs transmit data rising edge TBC.
Register Interface Signals
This section describes 8101/8104 register interface signals. REGA[7:0] Register Interface Address Input These inputs provide address specific internal register accessed, clocked into device rising edge REGCLK. Register Interface Clock Input This input clocks data REGD[15:0], REGA[7:0], REGRDn, REGWRn rising edge. REGCLK frequency must between 5-40 MHz. Register Interface Chip Select Input This input must asserted enable reading writing data REGD[15:0] REGA[7:0]. This input clocked rising edge REGCLK. Register Interface Data Bidirectional This bidirectional 16-bit data path from internal registers. Data read written from internal registers rising edge register clock, REGCLK. Register Interface Interrupt Output This output asserted when certain interrupt bits registers set, remains latched HIGH until interrupt bits read cleared. Register Interface Read Input When this input asserted, accessed internal register read (data output from register). This input clocked into device rising edge REGCLK. Register Interface Write Input When this input asserted, accessed internal register written (data input register). This input clocked into device rising edge REGCLK.
REGCLK
REGCSn
REGD[15:0]
REGINT
REGRDn
REGWRn
Signal Descriptions
Copyright 2000-2001 Logic Corporation. rights reserved.
Micellaneous Signals
This section describes 8101/8104 micellaneous signals. LINKn Receive Link Output When this signal HGH, there link. When this signal asserted, receive link synchronized configured. Reserved These pins reserved must left floating. Reset Input When this signal HIGH, controller normal operation. When this signal asserted, controller resets, FIFO's cleared, counters cleared, register bits default values. Signal Detect Input When this signal asserted, data detected receive 10-bit valid. When LOW, data valid 8B10B receiver forced loss sync state. This signal ignored (assumed high) unless SD_EN "Register 9-Configuration Section 4.3.10, cleared. 3-state pins Input This used testing purposes only. When asserted, output bidirectional pins placed high-impedence state. Test Mode Input This used factory test must tied proper operation. Transmit Clock Input This input clock used 8B10B section generates transmit output
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