Semiconductor ML9040-Axx/-Bxx Semiconductor SEGMENT DRIVER T

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Semiconductor ML9040-Axx/-Bxx Semiconductor SEGMENT DRIVER T

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E2B0048-29-21
Semiconductor ML9040-Axx/-Bxx
Semiconductor SEGMENT DRIVER
This version: Feb. 1999 ML9040-Axx/-Bxx Previous version: Mar. 1996
MATRIX CONTROLLER WITH 16-DOT COMMON DRIVER 40-DOT
GENERAL DESCRIPTION
ML9040-Axx/-Bxx matrix controller which fabricated power CMOS silicon gate technology. Character display matrix character type controlled combination with 4-bit 8-bit microcontroller. This consists 16-dot COMMON driver, 40-dot SEGMENT driver, display data RAM, character generator RAM, character generator control circuit. ML9040-Axx/-Bxx character generator that programmed custom mask. ML9040-Axx/-Bxx standard version having characters with lowercase dots), characters with uppercase dots) this ROM.
FEATURES
Easy interface with 8-bit 4-bit microcontroller. matrix controller/driver lowercase dots) uppercase dots). Automatic power reset. COMMON signal drivers (16) SEGMENT signal drivers (40). control characters when used combination with MSM5259. Character generator characters with lowercase dots) characters with uppercase dots). Character patterns programmable character generator RAM. (Lowercase: dots, patterns, uppercase: dots, patterns). Built-in oscillation circuit connect with external resistor ceralock. duty line; dots cursor), 1/11 duty line; dots cursor), 1/16 duty lines; dots cursor), selectable. Clear display even bias, 3.0V driving voltage. driving waveform ML9040-Axx: mode ML9040-Bxx: mode Package options: 80-pin plastic (QFP80-P-1420-0.80-BK) (Product name: ML9040-Axx/-BxxGA) indicates code number.
OSC1 OSC2
Timing generation circuit Cursor blink control Instruction decoder (ID) Character generator RAM) 16-bit shift register Common signal driver COM1~16
ML9040-Axx/-Bxx
BLOCK DIAGRAM
Input/ output buffer
Instruction register (IR)
Parallel/ serial conversion
Data register (DR) Character generator RAM)
40-bit shift register
40-bit latch
Busy flag (BF)
Seg- ment signal SEG1~40 driver
Address counter (ADC)
Display data RAM)
Semiconductor
Semiconductor
ML9040-Axx/-Bxx
INPUT OUTPUT CONFIGURATION
Applicable
Applicable pins
Applicable pins
Applicable pins DB7.
ML9040-Axx/-Bxx
Semiconductor
CONFIGURATION (TOP VIEW)
ML9040-Axx/-Bxx
SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38
SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 OSC1
SEG39 SEG40 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
OSC2
80-Pin Plastic
Semiconductor
ML9040-Axx/-Bxx
DESCRIPTIONS
Symbol OSC1, OSC2 COM1 COM16 SEG1 SEG40 Read/write selection input pin. Read, Write Register selection input pin. Data register, Instruction register Input data input/output with instruction register activation. Input/output pins data send/receive with Clock oscillating pins required internal operation upon receipt drive signal instruction. COMMON signal output pins. SEGMENT signal output pins. Output connected MSM5259 expand number characters displayed. Clock output used when data output shifts inside MSM5259. Clock output serially transferred data latched MSM5259. alternating current signal (Display Frequency) output pin. Power supply pin. Ground pin. Bias voltage input pins drive LCD. Description
ML9040-Axx/-Bxx
Semiconductor
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Driving Voltage Symbol TSTG Condition 25°C 25°C Rating -0.3 -0.3 Unit Applicable VDD, R/W, Input Voltage Power Dissipation Storage Temperature 25°C OSC1
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Data Holding Voltage*1 Driving Voltage*2 Operating Temperature Symbol VHOLD VLCD Condition bias, VDD-V5*3 bias, VDD-V5*4 Range Unit Applicable VDD, VDD, VDD,
Voltage assure oscillation register data retention. Voltage between Voltages applicable follows. (VDD (VDD (VDD (VDD (VDD (VDD (VDD
Semiconductor
ML9040-Axx/-Bxx
ELECTRICAL CHARACTERISTICS
Characteristics
Parameter Input Voltage Input Voltage Input Voltage Input Voltage Output Voltage Output Voltage Output Voltage Output Voltage Driver Resistor (COM pins) Driver Resistor (SEG pins)
Input Leakage Current
(VDD 5.5V, +75°C) Condition -0.205mA 1.2mA -40mA 40mA ±50mA, VLCD ±50mA, VLCD 5.0V Min. -0.3 VDD-1.0 -0.3 0.9VDD Typ. -125 Max. 0.1VDD -250 Unit R/W, Applicable R/W, OSC1 OSC2 COM1 COM16 SEG1 SEG40
Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 RCOM RSEG
Input Current
IIL2
VDD, excluding current flowing over pullup resistor output drive 5.0V, resistor oscillation external clock input OSC1.
Supply Current
IDD1
fOSC 270kHz. level. Other inputs open. Output pins load. 5.0V, ceramic oscillation, fOSC 250kHz.
0.35
Supply Current
IDD2
level. Other pins open. Output pins load. bias bias
0.55
Driving Bias Input Voltage Schmitt voltage width Built-in reset detection voltage
VLCD1 VLCD2 VSUM VRES
VDD-V5
VDD,
ML9040-Axx/-Bxx Characteristics
Semiconductor
(VDD 5.5V, +75°C) Parameter Clock Oscillation Frequency Clock Input Frequency Input Clock Duty Input Clock Rise Time Input Clock Fall Time Ceramic Unit Oscillation Frequency fOSC Symbol fOSC1 fDUTY 510kW, 30kW, Ceralock CSB250A. OSC1 OSC2 Condition 91kW OSC2 open. Input from OSC1 Min. Typ. Max. Unit Applicable OSC1 OSC2 OSC1 OSC1 OSC1 OSC1
Applicable current that flows when power input follows: 3.4V, 1.8V, 0.2V, -1.4V, -3V.
OSC1 OSC2 Rf=91kW±2% Minimum wiring required between OSC1 between OSC2
Semiconductor
Applied pulse input OSC1.
ML9040-Axx/-Bxx
waveform
0.5VDD
0.5VDD
0.5VDD
fDUTY tHW/ (tHW tLW) 100(%) Applied pulse input OSC1.(-Axx/-Bxx) VDD-1.0V waveform 1.0V OSC1 OSC2 Ceralock VDD-1.0V 1.0V
Ceralock CSB250A (mfd. MURATA MFG.Co.) 510kW 30kW 200pF ±10% 200pF ±10% Please contact when using this circuit.
Input voltage listed table below
(LCD lines) 1-line mode VLCD VLCD 3VLCD VLCD VLCD 2VLCD 3VLCD 4VLCD VLCD 2-line mode
VLCD driving voltage. (For (number lines), refer initial instruction code.)
ML9040-Axx/-Bxx Timing output
Semiconductor
(VDD 4.5V, +75°C) Parameter setup time pulse width hold time rise time fall time pulse width cycle time data output delay time data output hold time Symbol Min. Typ. Max. Unit
Values design specification actually determined after sample evaluation.
VIH1
VIH1
VIH1
VIL1
VIH1
VIL1
VIH1 DB0-DB7
VIH1
VIL1
VIL1
VIL1
VOH1 VOL1 Output data VOH1 VOL1
Semiconductor
ML9040-Axx/-Bxx
Switching Characteristics
Timing input from
(VDD 5.5V, +75°C) Parameter setup time pulse width hold time rise time fall time pulse width cycle time input data setup time input data hold time Symbol Min. Typ. Max. Unit
Values design specification actually determined after sample evaluation.
VIL1
VIL1
VIH1
VIL1 VIL1
VIH1 VIH1
VIH1
VIL1
VIH1
VIL1
VIH1
VIL1
VIL1 Input data
VIL1
ML9040-Axx/-Bxx Timing output MSM5259
Semiconductor
(VDD 5.5V, +75°C) Parameter pulse width pulse width setup time holding time clock set-up time clock hold time pulse width delay time Symbol tHW1 tHW2 Min. -1000 Typ. Max. 1000 Unit
tHW1
VOH2 VOH2
VOH2 VOL2
VOH2 VOL2
VOL2 VOL2
VOH2 VOL2
VOH2 VOH2 VOH2 tHW2 VOH2
VOL2
Semiconductor
ML9040-Axx/-Bxx
FUNCTIONAL DESCRIPTION Instruction Register (IR) Data Register (DR)
These registers selected REGISTER SELECTION (RS) pin. selected when level input selected when level input. used store address display data RAM) character generator RAM) instruction code. written, read microcomputer (CPU). used write read data from RAM. data written automatically written internal operation. When address code written data specified address) automatically transferred from Next, when reads possible verify data from data. After writing CPU, next adress selected ready next writing. Likewise, after reading CPU, data read ready next reading. Write/read from both registers carried READ/WRITE (R/W) pin. Table pins functions
write Read busy flag (BF) address counter (ADC) write read Function
Busy Flag (BF) When busy flag "H", indicates that ML9040-Axx/-Bxx engaged internal operation. When busy flag "H", instruction ignored. When "L", busy flag output from DB7. instruction should input when busy flag level. When busy flag "H", output code address counter (ADC) undefined. Address Counter (ADC) address counter (ADC) allocates address write/ read also cursor display. When instruction code address address setting input after deciding whether RAM, address code transferred from ADC. After writing (reading) display data (from) RAM, incremented (decremented) internally. data output conditions that "H", "L", "L".
ML9040-Axx/-Bxx
Semiconductor
Timing Generator Circuit
This circuit used generate timing signals activate internal operations upon receipt instruction also from such internal circuits RAM, RAM, ROM. designed that internal operation caused accessing from will interfer with internal operation caused driving. Consequently, when data written from RAM, flickering does occur display area other than display area where data written. addition, this circuit generates transfer signal MSM5259 display character expansion.
Display Data RAM)
This used store display data 8-bit character codes (see Table address corresponds display position LCD. correspondence between described following. address (set ADC) expressed hexadecimal notation shown below:
Hexadecimal notation (Example) When address Hexadecimal notation
Corresponden between address display position 1-line display mode
First digit Display position address (hex.)
(2)When ML9040-Axx/-Bxx alone used, characters displayed from first eighth digit.
First digit
When display shifted instruction, correspondence between display position address changes shown below:
(Display shifted right) (Display shifted left) First digit First digit
Semiconductor
ML9040-Axx/-Bxx
(3)When ML9040-Axx/-Bxx used with MSM5259, characters displayed from first sixteenth digit shown below:
First digit
ML9040-Axx/-Bxx display
MSM5259 display
When display shifted instruction, correspondence between display address changes shown below:
First digit ML9040-Axx/-Bxx display (Display shifted left) MSM5259 display
(Display shifted right)
(4)Since ML9040-Axx/-Bxx capacity characters, MSM5259 devices connected ML9040-Axx/-Bxx that characters displayed.
First digit ML9040-Axx/-Bxx display MSM5259 display MSM5259 display MSM5259 display
ML9040-Axx/-Bxx
Semiconductor
Correspondence between address display position 2-line display mode
First digit First line Second line Display position address (hex.)
(Note) last address first line consecutive head address second line. (6)When ML9040-Axx/-Bxx alone used, characters characters lines) displayed from first eighth digit.
First digit
First line Second line
When display shifted instruction, correspondence between display position address changes shown below:
First digit First digit (Display shifted left) First line Second line
(Display shifted right)
First line Second line
(7)When ML9040-Axx/-Bxx used with MSM5259, characters characters lines) displayed from first sixteenth digit.
First digit First line Second line
ML9040-Axx/-Bxx display
MSM5259 display
Semiconductor
ML9040-Axx/-Bxx
When display shifted instruction, correspondence between display position address changes shown below:
(Display shifted right) First digit First line Second line
ML9040-Axx/-Bxx display (Display shifted left) First digit
MSM5259 display
First line Second line
ML9040-Axx/-Bxx display
MSM5259 display
Since ML9040-Axx/-Bxx capacity characters, MSM5259 devices connected ML9040-Axx/-Bxx 2-line display mode.
First digit First line Second line ML9040-Axx/-Bxx display MSM5259 display MSM5259 display MSM5259 display
Character Generator ROM)
used generate dots (160 kinds) dots kinds) character patterns from 8-bit character code signal. correspondence between 8-bit character codes character patterns shown Table When 8-bit character code written RAM, character pattern corresponding code displayed display position corresponding address.
Lower bits Upper bits
ML9040-Axx/-Bxx
Table Relationship Between Character Codes Characters (Character Patterns) ML9040-A01/-B01
0000
0010
0011
0100
0101
0110
0111
1010
1011
1100
1101
1110
1111
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Semiconductor
Semiconductor
ML9040-Axx/-Bxx
Character Generator RAM)
used display user's original character patterns other than character patterns ROM. capacity bytes bits) writing kinds characters dots kinds characters dots. When displaying character patterns stored RAM, write 8-bit character codes hex.) left side shown Table Then possible output character pattern display position corresponding address. following explains write read character patterns from RAM. When character pattern dots (see Table 3-1). method writing character pattern CPU: Three bits addresses correspond line position character pattern. First, increment decrement CPU, then input address. After this, write character patterns through line line. correspond data Table 3-1. displayed when input data displayed when input data. Since automatically incremented decremented after writing data RAM, necessary address again. line, which addresses ("7" hexadecimal notation), cursor position. ORed with cursor cursor position displayed LCD. this reason, necessary input data that become cursor positions "L". Although data bits output display data, data bits output. latter written read from RAM, therefore allowed used data RAM. method displaying character pattern LCD: selected when upper bits character codes "L". character code invalid, display Table 3-1, selected character code "00" (hex.) "08" (hex.). When 8-bit character code written RAM, character pattern displayed display position corresponding address. data, bits correspond address, bits 3-5.)
ML9040-Axx/-Bxx When character pattern dots (see Table 3-2).
Semiconductor
method writing character pattern into CPU: Four bits address, bits 0-3, correspond line position character pattern. First, increment decrement with CPU, then input address RAM. After this, write character pattern code into RAM, line line from DB0DB7. correspond data, bits 0-7, Table 3-2. displayed when input data, while displayed when input data. automatically incremented decremented after writing data RAM, necessary address again. line, CGRAM addresses which hexadecimal notation, cursor position. CGRAM data 0Red with cursor cursor position displayed LCD. this reason, necessary input data that become cursor positions "L". When data, bits 0-4, addresses, bits 0-3, "A", they displayed display data. When data, bits 5-7, RAM, data address data "F", output LCD. this case, used written into/read out. used data RAM. method displaying character pattern LCD: selected when 4-upper order bits character code "L". character code bits invalid, display selected character codes "00", "01", "08", "09" (hex.) Table 3-2. When character code written RAM, character pattern displayed display position corresponding address. data bits correspond address bits
Semiconductor
ML9040-Axx/-Bxx
Table Relationship between data (character pattern), address data when character pattern dots. example below indicates "OKI".
data
(character pattern)
address
data
(character code)
Don't Care
ML9040-Axx/-Bxx
Semiconductor
Table Relationship between data (character pattern), address data when character pattern dots. examples below indicate
data
(character pattern)
address
Don't Care
data
(character code)
Semiconductor
ML9040-Axx/-Bxx
Cursor/Blink Control Circuit
This circuit that generates cursor blink. This circuit under control program. display cursor blink made position corresponding address that ADC. figure below shows example cursor/blink position when value "07" (hex.).
First digit 1-line display mode
Cursor blink position First digit 2-line display mode First line Second line
Cursor blink position
(Note) cursor blink displayed even when address ADC. this reason, necessary inhibit cursor blink display while address ADC.
Display Circuit (COM1 COM16, SEG1 SEG40,
ML9040-Axx/-Bxx provides signal outputs outputs) signal outputs outputs), display characters (1-line display) characters (2line display) unit. SEG1 SEG40 used display 8-digit display LCD. expand display, MSM5259 used. MSM5259, 40-dot segment driver, used expansion signal output. Interface with MSM5259 made through data output (DO), clock output (CP), latch output (L), display frequency (DF). character pattern data serially transferred MSM5259 through When data characters 360-bit 5bit/ch. 1-line display) characters 160-bit (5-bit/ch. 2-line display) output, latch pulse also output through this latch pulse, data transferred serially MSM5259 latched used display data. display frequency signal (DF) required when displayed also output from synchronously with this latch pulse.
ML9040-Axx/-Bxx
Semiconductor
Built-in Reset Circuit
ML9040-Axx/-Bxx automatically initialized when power turned During initialization, busy flag (BF) holds does accept instructions (other than busy flag read). busy flag holds after reaches 4.5V more. During initialization, ML9040-Axx/-Bxx executes follwing instructions: Display clear Data length interface with CPU: bits (8B/4B "H") LCD: 1-line display "L") Character font: dots "L") ADC: Increment (I/D "H") display shift "L") Display: "L") Cursor: "L") blink "L")
required satisfy following power supply conditions.
4.5V
0.2V
0.2V
0.2V
tOFF
0.1ms 100ms
tOFF
Fig. Power ON/OFF Waveform
Semiconductor
ML9040-Axx/-Bxx
Data Connected with
data connected with available either once bits twice bits. This allows ML9040-Axx/-Bxx interfaced with either 8-bit 4-bit CPU. When interface data bits Data lines) used data input/output carried step. When interface data bits 8-bit data input/output carried steps using only high-order bits data lines) first time data input/output made 4-high order bits (DB4 DB7) second time data input/output made low-order bits (DB0 DB3). Even when data input/output completed through high-order bits, sure make another input/output low-order bits. (Example: Busy flag Read). Since data input/output carried steps execution, normal data transfer executed from next input/output accessed only once.
ML9040-Axx/-Bxx
Semiconductor
Busy (internal operation)
Busy
Busy
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
Instruction register(IR) write
Busy flag(BF)and address counter(ADC)read
Data register (DR)write
Fig. 8-Bit Data Transfer
Semiconductor
Busy(internal operation)
Busy
Busy
ADC3
ADC6
ADC2
ADC5
ADC1
ADC4
ADC0
Instruction register (IR)write
Busy flag(BF)and address counter(ADC)read
Data register (DR)write
ML9040-Axx/-Bxx
Fig. 4-Bit Data Transfer
ML9040-Axx/-Bxx
Semiconductor
Instruction Code
instruction code defined signal through which ML9040-Axx/-Bxx accessed CPU. ML9040-Axx/-Bxx begins operation upon receipt instruction code input. internal processing operation ML9040-Axx/-Bxx starts timing that does affect display, busy status continues longer than cycle time. Under busy status (when busy flag "H"), ML9040-Axx/-Bxx does execute instructions other than busy flag read. Therefore, verify that busy flag prior input instruction code. Display clear:
Instruction code
When this instruction executed, display cleared. entry mode setting (increment). does change. When cursor blink display, blinking position moves left (the left first line 2-line display mode). (Note) data goes "20" (hex.), while address counter (ADC) goes "00" (hex.). execution time 1.64 (max.), when oscillation frequency kHz.
Cursor home
Instruction code
Don't Care
When this instruction executed while cursor blink being displayed, blinking position moves left left first line 2line display mode). While display shift, display returns original position before shifting. (Note) address counter (ADC) goes "00" (hex.). execution time 1.64 (max.), when oscillation frequency kHz.
Semiconductor Entry mode setting
ML9040-Axx/-Bxx
Instruction code
When set, 8-bit character code written read from RAM, cursor blink shift right character position (I/D "H"; increment) left character position (I/D "L"; decrement). address counter incremented (I/D "H") decremented (I/D "L") this time. Even after character pattern code written read from RAM, address counter (ADC) incremented (I/D "H") decremented (I/D "L") When set, character code written RAM. Then cursor blink stop entire display shifts left (I/D "H") right "L") character position. When character read from during "H", when character pattern data written read from during "H", entire display does shift, normal write/read performed (the entire display does shift, cursor blink shift right (I/D "H") left (I/D "L") character position. When set, display does shift, normal write/read performed. execution time when oscillation frequency
Display mode setting
Instruction code
controls whether character pattern displayed displayed. When "H", this makes display character pattern. When "L", character pattern displayed. cursor blink also cancelled this time. (Note) Unlike display clear, character code rewritten all. cursor displayed when displayed when "H". blink cancelled when executed when "H". blink mode, dots (including cursor) displaying character pattern cursor displayed alternately 409.6 dots character font) 563.2 dots character font) when oscillation frequency kHz. execution time when oscillation frequency
ML9040-Axx/-Bxx Cursor display shift
Instruction code
Semiconductor
Don't Care
When "L", cursor blink positions shifted left character position (ADC decremented When "H", cursor blink positions shifted right character position (ADC incremented When "L", entire display shifted left character position. cursor blink positions also shifted with display (ADC remains unchanged). When "H", entire display shifted right character position. cursor blink positions also shifted with display (ADC remains unchanged). 2-line display mode, cursor blink positions shifted from first second line when cursor shifted right next fortieth digit (27; hex.) first line. such shifting made other cases. When shifting entire display, display pattern, cursor, blink positions case shifted between lines (from first second line vice versa). execution time, when oscillation frequency kHz,
Initial setting
Instruction code 8B/4B
Don't Care
When 8B/4B "H", data input/output from carried simultaneously means bits DB0. When 8B/4B "L", data input/output from carried steps through bits DB4. 2-line display mode selected when "H", while 1-line display mode selected when "L". dots character font selected when "L", while dots character font selected when "L". This initial setting accessed prior other instructions except busy flag read after power supplied ML9040-Axx/-Bxx.
Number display lines line line lines lines Character font dots dots dots dots Duty ratio 1/11 1/16 1/16 Number biases Number COMMOM signals
Semiconductor
ML9040-Axx/-Bxx
Generate biases externally input them VDD, When number biases input same potential execution time, when oscillation frequency kHz,
address setting
Instruction code
When addresses, bits (binary), set, specified, until address set. Write/read character pattern from begins with addresses, bits starting from selection. execution time, when oscillation frequency kHz,
address setting
Instruction code
When addresses (binary) selected, specified until address set. Write/read character code from begins with addresses starting from selection. 1-line display mode however, (binary) must values among "00" "4F" (hex.). Likewise, 2-line mode, (binary) must values among "00" "27" (hex.) "40" "67" (hex.). When value other than above input, impossible make normal write/ read character codes from RAM. execution time, when oscillation frequency kHz,
data write
Instruction code
When (binary) codes written RAM, cursor display move described "(5) Cursor display shift". execution time, when oscillation frequency kHz,
ML9040-Axx/-Bxx (10) Busy flag address counter read (Execution time ms.)
Semiconductor
Instruction code
busy flag (BF) output this instruction indicate whether MSM6222B-xx engaged internal operations "H") "L"). When "H", instruction accepted. therefore necessary verify before inputting instruction. When "L", correct address counter value output. address counter value must match address address. decision whether address address made address previously set. Since address counter value when sometimes incremented decremented during internal operations, always correct value.
(11) data read
Instruction code
Character codes (bits read from RAM, while character patterns from RAM. Selection decided address previously set. After reading those data, address counter (ADC) incremented decremented shift mode mentioned item "(3) shift mode set". execution time, when oscillation frequency kHz, (Note) Conditions reading correct data: When address address input before inputting this instruction. When cursor/display shift input before inputting this instruction case character code read. Data after second reading from when read more than times. Correct data output other case.
Semiconductor Interface with MSM5259
ML9040-Axx/-Bxx
Display examples when setting dots character font 1-line mode, dots character font 1-line mode, dots character font 2-line mode through instructions shown Figures respectively. When dots character font 1-line display mode, signals COM9 COM16 output extinguishing. Likewise, when dots character font (1-line set), signals COM12 COM16 output display-off. display example shows combination characters characters 2-line display mode) LCD. When number MSM5259s increased according increase number characters, possible display maximum characters. Besides, necessary generate bias voltage required operation splitting resistors outside input ML9040-Axx/-Bxx MSM5259. Examples these bias voltages shown Figures Basically, this done dividing voltage resistors shown Figures value resistor made larger reduce system power consumption, operating margin decreases driving waveform distorted. prevent this, by-pass capacitor serially connected resistor lower voltage division impedance caused splitting resistors shown Figures values vary according size used VLCD (LCD drive voltage), these values have determined through actual experimentation combination with LCD. (Example values: 10kW, 30kW, 0.0022 0.047 Figure shows application circuit ML9040-Axx/-Bxx MSM5259 including bias circuit. bias voltage maintain following potential relation: case 1-line characters display dots/font)
COM1 COM8
SEG1 ML9040-Axx/-Bxx/-Cxx/-Dxx
SEG40
LOAD MSM5259
DO20 DI21
Figure
ML9040-Axx/-Bxx case 16-character line) display dots/font)
Semiconductor
COM1
COM11
SEG1 ML9040-Axx/-Bxx
SEG40
LOAD MSM5259 DO20
DI21
Figure
case 16-character lines) display dots/font)
COM1
COM7 COM8 COM9
COM15 COM16
SEG1
SEG40
LOAD DO20 MSM5259
ML9040-Axx/-Bxx
DI21
Figure
Semiconductor Bias voltage circuit (1-line display mode)
ML9040-Axx/-Bxx
ML9040-Axx/-Bxx Bias voltage circuit (2-line display mode)
VLCD
ML9040-Axx/-Bxx
VLCD
Figure
Figure
Bias voltage circuit (1-line display mode)
Bias voltage circuit (2-line display mode)
ML9040-Axx/-Bxx VLCD ML9040-Axx/-Bxx
VLCD
Figure
(VLCD driving voltage)
Figure
COM1-16 SEG1-40 MSM5259 LOAD DO40 DO20 DI21 LOAD MSM5259 DO40 DO20 DI21 LOAD MSM5259 DO40 DO20 DI21
Application circuit
ML9040-Axx/-Bxx
Figure
ML9040-Axx/-Bxx
Semiconductor
Semiconductor Drive Waveforms
ML9040-Axx/-Bxx
Figures show driving waveforms consisting signal, signal, signal (latch pulse waveform) signal, duty 1/8, 1/11 1/16 respectively. relation between duty frame frequency described table below.
Duty 1/11 1/16
Frame frequency 78.1 56.8 78.1
(Note) oscillation frequency assumed kHz.
ML9040-Axx/-Bxx
Semiconductor
COM1 V2,V3
frame
COM2
V2,V3
COM8
V2,V3
COM9
V2,V3
COM16
V2,V3
Display-off waveform (Output V2,V3 example)
Display-on waveform
Figure Driving Waveforms mode) Duty
Semiconductor
ML9040-Axx/-Bxx
COM1 V2,V3
frame
COM2
V2,V3
COM11
V2,V3
COM12
V2,V3
COM16
V2,V3
Display-off waveform (Output example)
V2,V3
Display-on waveform
Figure Driving Waveforms mode) 1/11 Duty
ML9040-Axx/-Bxx
Semiconductor
COM1
frame
COM2
COM16
Display-off waveform (Output example)
Display-on waveform
Figure Driving Waveforms mode) 1/16 Duty
Semiconductor
ML9040-Axx/-Bxx
COM1 V2,V3
frame
COM2
V2,V3
COM8
V2,V3
COM9
V2,V3
COM16
V2,V3
(Output example)
V2,V3
Display turning-off waveform
Display turning-on waveform
Figure Driving Waveforms mode) Duty
ML9040-Axx/-Bxx
Semiconductor
1011 1011 COM1 V2,V3
frame
COM2
V2,V3
COM11
V2,V3
COM12
V2,V3
COM16
V2,V3
(Output example)
V2,V3
Display turning-off waveform
Display turning-on waveform
Figure Driving Waveforms mode) 1/11 Duty
Semiconductor
ML9040-Axx/-Bxx
COM1
frame
COM2
COM16
(Output example)
Display turning-off waveform
Display turning-on waveform
Figure Driving Waveforms mode) 1/16 Duty
ML9040-Axx/-Bxx Initial Setting Instruction
Semiconductor
When data input/output from carried bits (DB0 DB7): Turn power. Wait more after reached 4.5V more. initial setting instruction. Wait more. initial setting instruction. Wait more. initial setting instruction. Check busy flag Busy. line number character font (F). (After this, line number character font cannot changed.) Check Busy. Clear display setting display mode. Check Busy. Clear display. Check Busy. shift mode. Check Busy. Initial setting completed.
Example Instruction Code Steps
Don't Care
Semiconductor
ML9040-Axx/-Bxx
When data input/output from carried bits (DB4 DB7): Turn power. Wait more after reached 4.5V more. initial setting instruction. Wait more. initial setting instruction. Wait more. initial setting instruction. Check busy flag Busy. initial setting instruction. Wait more. line number character font initial setting instruction. (After this, line number character font cannot changed.) Check Busy. Clear display setting display mode. Check Busy. Clear display. Check Busy. shift mode. Check Busy. Initialization completed.
Example Instruction Code Steps
Example Instruction Code Step
Example Instruction Code Step
Execute two-step accesses bits from Step Step
ML9040-Axx/-Bxx
Semiconductor
PACKAGE DIMENSIONS
(Unit QFP80-P-1420-0.80-BK
Mirror finish
Package material Lead frame material treatment Solder plate thickness Package weight
Epoxy resin alloy Solder plating more 1.27 TYP.
Notes Mounting Surface Mount Type Package SOP, QFP, TSOP, TQFP, LQFP, SOJ, (PLCC), SHP, surface mount type packages, which very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
E2Y0002-29-11
NOTICE
information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents cotained herein reprinted reproduced without prior permission. MS-DOS registered trademark Microsoft Corporation.
Copyright 1999 Electric Industry Co., Ltd.
Printed Japan

Semiconductor ML9040-Axx/-Bxx Semiconductor SEGMENT DRIVER T

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