S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver SiGe BiCMOS Tec

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S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver SiGe BiCMOS Tec

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Part Number S3457TT20 Revision June 2001
S3457TT20
OC-48 SONET/SDH/A4-Bit Transceiver
SiGe BiCMOS Technology Complies with Bellcore ITU-T specifications 4-bit LVDS data path 622.08 Mbps On-chip, high-frequency clock generation Supports OC-48 (2.488 Gbps) Reference frequency 155.52 Diagnostic loopback mode Supports line timing Lock detect Signal detect input jitter LVDS interface Internal FIFO decouple transmit clocks Single supply Typical power Compact TQFP package
DEVICE SPECIFICATION
Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
GENERAL DESCRIPTION
S3457 SONET/SDH transceiver chip fully integrated serialization/deserialization SONET OC-48 (2.488 Gbps) interface device. S3457 receives OC-48 scrambled signal. chip performs necessary serial-to-parallel parallel-to-serial functions conformance with SONET/SDH transmission standards. device suitable SONET-based applications. Figure shows typical network application. On-chip clock synthesis performed high-frequency phase-lock loop S3457 transceiver chip, allowing slower external transmit clock reference. chip used with 155.52 reference clock support existing system clocking schemes. jitter LVDS interface guarantees compliance with bit-error rate requirements Bellcore ITU-T standards. S3457 packaged compact TQFP, offering designers small package outline.
APPLICATIONS
Wavelength Division Multiplex (WDM) equipment SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment Aover SONET/SDH Section repeaters
Figure System Block Diagram
AMCC GANGES AMCC S3457 S3056 AMCC S3457 S3056 AMCC S3457 S3056 AMCC S3457 S3056 S3056 AMCC S3457
S3056
AMCC S3457 AMCC GANGES
S3056
AMCC S3457
S3056
AMCC S3457
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S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver SONET OVERVIEW
Synchronous Optical Network (SONET) standard connecting fiber system another optical level. SONET, together with Synchronous Digital Hierarchy (SDH) administered ITU-T, forms single international standard fiber interconnect etwee telephone network ffer countries. SONET capable accommodating variety transmission rates applications. SONET standard layered protocol with four separate layers defined. These are: Photonic Section Line Path
Revision June 2001
DEVICE SPECIFICATION
Frame Byte Boundary Detection SONET/SDH fundamental frame format STS-48 consists transport overhead bytes followed Synchronous Payload Envelope (SPE) bytes. This pattern overhead 4176 bytes repeated nine times each frame. Frame byte boundaries detected using bytes found transport overhead. (See Figure more details SONET operations, refer Bellcore SONET standard document.
Figure SONET Structure
Functions
Payload mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Path layer Line layer Section layer
Path layer Line layer Section layer
Figure shows layers their functions. Each layers overhead bandwidth dedicated administration maintenance. photonic layer easily handles conversion from electrical optical back with overhead. responsible transmitting electrical signals optical form over physical media. section layer handles transport framed electrical signals across optical cable from next. functions this layer framing, scrambling, error monitoring. line layer responsible reliable transmission path layer information stream carrying voice, data, video signals. main functions synchronization, multiplexing, reliable transport. path layer responsible actual transport services appropriate signaling rates. Data Rates Signal Hierarchy Table contains data rates signal designations SONET hierarchy. lowest level basic SONET signal referred synchronous transport signal level-1 (STS-1). STS-N signal made byte-interleaved STS-1 signals. optical counterpart each STS-N signal optical carrier level-N signal (OC-N). S3457 chip supports OC-48 rate (2.488 Gbps).
Photonic layer
Photonic layer
Equipment
Fiber Cable Equipment
Table SONET Signal Hierarchy
Elec. STS-1 STS-3 STS-12 STS-24 STS-48 STM-1 STM-4 STM-8 STM-16 CCITT Optical OC-1 OC-3 OC-12 OC-24 OC-48 Data Rate (Mbps) 51.84 155.52 622.08 1244.16 2488.32
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Figure STS-48/OC-48 Frame Format
Bytes Bytes
Revision June 2001
DEVICE SPECIFICATION
Rows
Synchronous Payload Envelope 4176 Columns Transport Overhead Columns 4176 37,584 bytes 1296 bytes µsec
S3457 OVERVIEW
S3457 transceiver implements SONET/SDH serialization/deserialization transmission functions. block diagram Figure shows basic operation chip. This chip used implement front SONET equipment, which consists primarily serial transmit interface serial receive interface. chip handles functions these elements, including parallel-to-serial serial-to-parallel conversion, clock generation, system timing. system timing circuitry consists management data stream clock distribution throughout front end.
S3457 divided into transmitter section receiver section. sequence operations follows: Transmitter Operations: 4-bit parallel input Parallel-to-serial conversion Serial output Receiver Operations: Serial input Serial-to-parallel conversion 4-bit parallel output Internal clocking control functions transparent user.
Suggested Interface Devices
AMCC AMCC S3056 S19202 OC-48 Clock Recovery Device STS-192 POS/ASONET/SDH Mapper
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Figure S3457 Transceiver Functional Block Diagram
PHINITP/N TXCLK_SEL
Revision June 2001
DEVICE SPECIFICATION
CLOCK SYNTHESIZER
REFCLKP/N POCLK÷4 (Internal) RLPTIME CAP1 CAP2
CLOCKS
LOCKDET TXCLKP/N
TIMGEN
PCLKP/N PHERRP/N
SLPTIME BYPASS PINP/N[3:0] PICLKP/N BYPASSCLKP/N TSCLKP/N (Internal) TSCLKP/N PARALLEL SERIAL TSDP/N (Internal) TSDP/N
LLEB
KILLRXCLK
TIMGEN POCLKP/N
RSDP/N
TSDP/N (Internal)
SERIAL PARALLEL
POUTP/N[3:0]
RSCLKP/N TSCLKP/N (Internal) DLEB SQUELCH
SDLVTTL SDLVPECL
RSTB
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S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver S3457 TRANSCEIVER FUNCTIONAL DESCRIPTION TRANSMITTER OPERATION
S3457 transceiver chip performs serialization stage processing transmit SONET STS-48 data stream. converts 4-bit parallel data into bitserial format 2.488 Gbps. high-frequency clock generated from 155.52 frequency reference using integral frequency synthesizer that contains Phase-Lock Loop (PLL) circuit with divider loop. Diagnostic loopback (transmitter receiver) line loopback (receiver transmitter) provided. Other Operating Modes. Clock Synthesizer clock synthesizer, shown block diagram Figure monolithic that generates serial output clock frequency that locked input Reference Clock (REFCLKP/N). order Transmit Serial Clock (TSCLK) frequency have accuracy required operation SONET system, REFCLKP/N input must generated from crystal oscillator that frequency accuracy that meets value stated Table Lower accuracy crystal oscillators used applications less demanding than SONET/SDH. on-chip consists phase detector, which compares phase relationship between Voltage Controlled Oscillator (VCO) output REFCLKP/N input, loop filter, which converts phase detector output into smooth voltage, VCO, whose frequency varied this voltage. loop filter generates control voltage based average level phase discriminator output pulses. single external clean-up capacitor utilized part loop filter. loop filter's corner frequency optimized minimize output phase jitter. Timing Generator
Revision June 2001
DEVICE SPECIFICATION
timing generation function, seen Figure provides divide-by-4 version transmit serial clock. This circuitry also provides internally generated load signal, which transfers PINP/N[3:0] data from FIFO serial shift register. Parallel Clock (PCLK) output 4-bit parallel rate version transmit serial clock (divide-by-4). PCLK intended 4-bit parallel clock upstream multiplexing overhead processing circuits. Using PCLK upstream circuits will ensure stable frequency phase relationship between data coming into leaving S3457 device. timing generator also produces feedback reference clock clock synthesizer. counter divides synthesized clock down same frequency Reference Clock (REFCLK). clock synthesizer maintains stability synthesized clock comparing phase internal clock with that REFCLK. modulus counter function reference clock frequency operating frequency. Parallel-to-Serial Converter parallel-to-serial converter shown Figure comprised FIFO parallel-to-serial register. FIFO input latches data from PINP/N[3:0] rising edge Parallel Input Clock (PICLK). parallel-to-serial register loadable shift register that takes parallel input from FIFO output. internally generated divide-by-4 clock, which phase aligned TSCLK described timing generator description, activates parallel data transfer between registers. serial data shifted parallel-to-serial register TSCLK rate. FIFO FIFO added decouple internal external (PICLK) clocks. internally generated divide-by-4 clock used clock data from FIFO. Phase Initialization (PHINITP/N) Lock Detect (LOCKDET) used center reset FIFO. PHINITP/N LOCKDET signals will center FIFO after third PICLK pulse. This order insure that PICLK stable. This scheme allows user have infinite PCLK-to-PICLK delay through ASIC. Once FIFO centered, PCLK-toPICLK delay have maximum drift, specified Table Figure
Table Reference Jitter Limits
Frequency Band Maximum Reference Clock Jitter
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FIFO Initialization FIFO initialized following three ways: During power once locked reference clock provided REFCLK pins, LOCKDET will active initialize FIFO. When Reset (RSTB) goes active, entire chip reset. This causes lock thus LOCKDET goes inactive. When reacquires lock, LOCKDET goes active initializes FIFO. Note that PCLK held reset when RSTB active. user also initialize FIFO raising PHINIT. During normal running operation, incoming data passed from PICLK timing domain internally generated divide-by-4 clock timing domain. Although frequency PICLK internally generated clock same, their phase relationship arbitrary. prevent errors caused short setup hold times between timing domains, timing generator circuitry monitors phase relationship between PICLK internally generated clock. When potential setup hold time violation detected, Phase Error (PHERR) pulses high PCLK period. condition persists, PHERR will remain high. When PHERR conditions occur, PHINIT should activated recenter FIFO least PCLK periods). This done connecting PHERR PHINIT. When realignment occurs, bytes data will lost. user also take PHERR signal, process send output PHINIT such that idle bytes lost during realignment process. PHERR will inactive when realignment complete.
Revision June 2001
DEVICE SPECIFICATION
mat. serial data clock inputs differential internally biased terminated signals. rising edge positive serial clock synchronous with input data transitions. Parallel output clock data LVDS signals 622.08 Mbps. falling edge Positive Output Clock (POCLK) synchronous with output parallel register which drives POUTP/N[3:0].
OTHER OPERATING MODES
Diagnostic Loopback When Diagnostic Loopback Enable (DLEB) input active, loopback from transmitter receiver serial data rate diagnostic purposes. differential serial output data clock from transmitter routed serial-toparallel block place normal Receive Serial Data (RSD) Receive Serial Clock (RSCLK). TSD/ TSCLK outputs active. DLEB takes precedence over SDLVPECL SDLVTTL. Line Loopback line loopback circuitry selects source data clock which output TSCLK. When Line Loopback Enable (LLEB) input inactive, selects data clock from parallel-toserial converter block. When LLEB active, forces output data multiplexer select data clock from RSCLK inputs, receive-totransmit loopback established serial data rate. Diagnostic loopback line loopback active same time. Loop Timing Serial Loop Timing (SLPTIME) mode, clock synthesizer S3457 bypassed, timing entire transmitter section controlled RSCLKP/N. This mode entered setting SLPTIME input LVTTL High level. this mode REFCLKP/N input used. should carefully noted that internal continues operate this mode continues source TXCLKP/N. this signal being used, REFCLKP/N input must properly driven. Reference Loop Timing (RLPTIME) mode, parallel clock from receiver (POCLKP/N) used reference clock transmitter. this mode, REFCLKP/N input used. TXCLKP/N generated from POCLKP/N this operating mode.
RECEIVER OPERATION
S3457 transceiver chip provides first stage digital processing receive SONET STS-48 bitserial stream. converts bit-serial 2.488 Gbps data stream into 4-bit parallel data format. loopback mode provided diagnostic loopback (transmitter receiver). line loopback (receiver transmitter) also provided. Both line diagnostic loopback modes active same time. Serial-to-Parallel Converter serial-to-parallel converter consists 4-bit registers. first serial-in, parallel-out shift register that performs serial-to-parallel conversion. S3457 converts bit-serial 2.488 Gbps data stream into 622.08 Mbps, 4-bit wide parallel data for-
Squelched Clock Operation
Some integrated optical receiver/clock recovery modules force their recovered serial receive clock output
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logic state optical signal removed reduced below fixed threshold. This condition accompanied expected deassertion signal detect output. S3457 been designed operation with clock recovery devices that provide continuous serial clock. This ensures seamless downstream clocking event optical signal loss. S3457 operated with optical transceiver that provides Squelched Clock behavior, described above, activating SQUELCH pin. this condition, receive serial clock RSCLKP/N used receiver timing when SDLVPECL/ SDLVTTL inputs active state. When SDLVPECL/SDLVTTL inputs placed inactive state (usually deassertion LOCKDET signal detect from optical transceiver/clock recovery
Revision June 2001
DEVICE SPECIFICATION
unit), transmitter serial clock will used maintain timing receiver section. This will allow POCLK continue parallel outputs flush last received characters. then assumes state imposed serial data input. important note that this mode, there will one-time shortening lengthening POCLK cycle, resulting apparent phase shift POCLK deassertion condition. Another similar phase shift will occur when condition reasserted. normal operating mode, with SQUELCH inactive, there will phase discontinuities POCLK output during signal loss reacquisition (assuming operation with continuous clocking from device such AMCC S3040, S3050, S3056).
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Table S3457 Transmitter Assignments Descriptions
Name PINP0 PINN0 PINP1 PINN1 PINP2 PINN2 PINP3 PINN3 PICLKP PICLKN Level LVDS
Revision June 2001
DEVICE SPECIFICATION
Description Parallel Input Data, aligned parallel input clock (PICLK). PINP/N[3] most significant (corresponding each word, first transmitted). PINP/N[0] least significant (corresponding each word, last transmitted). PINP/N[3:0] sampled rising edge PICLK. Internally terminated.
LVDS
Parallel Input Clock. divide-by-4, nominally duty cycle input clock, which PINP/N[3:0] aligned. PICLK used transfer data PINP/N inputs into holding register parallel-to-serial converter. rising edge PICLK samples PINP/N[3:0]. Internally terminated. Transmitter Loop Filter Capacitor. external loop filter capacitor resistors connected these pins. Figure Phase Initialization. Rising edge will realign internal timing. Internally terminated. Transmit Clock Select. Used select between 155.52 77.76 clock TXCLKP/N output. TXCLK_SEL selects 155.52 TXCLK, High TXCLK_SEL selects 77.76 TXCLK. Transmit Serial Data. Differential serial data stream signals, normally connected optical transmitter module. Transmit Serial Clock. Differential CML. used retime signal. Parallel Clock. reference clock generated dividing internal clock four. normally used coordinate 4-bit wide transfers between upstream logic S3457 device. Phase Error. Active High. Pulses High during each PCLK cycle which there potential setup/hold timing violation between internal byte clock PICLK timing domains. Lock Detect. Goes High after locked clock provided REFCLK pins. LOCKDET asynchronous output.
CAP1 CAP2 PHINITP PHINITN TXCLK_SEL
Analog LVDS LVTTL
TSDP TSDN TSCLKP TSCLKN PCLKP PCLKN PHERRP PHERRN LOCKDET
Diff. Diff. LVDS
LVDS
LVTTL
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Table S3457 Receiver Assignments Descriptions
Name RSDP RSDN RSCLKP RSCLKN SDLVPECL Level Differential Differential Single Ended LVPECL
Revision June 2001
DEVICE SPECIFICATION
Description Receive Serial Data. Data stream signals normally connected optical receiver module. Internally biased terminated. Receive Serial Clock. Used supply clock input RSDP/N inputs. Internally biased terminated. LVPECL Signal Detect. LVPECL signal with internal pull-down. Active High when SDLVTTL held logic single-ended LVPECL input driven external optical receiver module indicate loss received optical power. When SDLVPECL inactive, data Receive Serial Data (RSDP/N) pins will internally forced constant When SDLVPECL active, data RSDP/N pins will processed normally. When SDLVTTL connected optical receiver module instead SDLVPECL, then SDLVPECL should tied High implement active signal detect left unconnected implement active High signal detect. LVTTL Signal Detect. Active High when SDLVPECL unconnected (logic Active when SDLVPECL tied high. single-ended LVTTL input driven external optical receiver module indicate loss received optical power. When SDLVTTL inactive, data RSDP/N pins will internally forced constant When SDLVTTL active, data RSDP/N pins will processed normally. Parallel Output data bus. Aligned Parallel Output Clock (POCLKP/N). POUTP/N[3] most significant (corresponding each word, first received). POUTP/N[0] least significant (corresponding each word, last received). POUTP/N[3:0] updated falling edge POCLK.
SDLVTTL
LVTTL
POUTP0 POUTN0 POUTP1 POUTN1 POUTP2 POUTN2 POUTP3 POUTN3 POCLKP POCLKN
LVDS
LVDS
Parallel Output Clock. divide-by-4, nominally duty cycle, parallel output clock that aligned POUTP/N[3:0] 4-bit parallel output data. POUTP/N[3:0] updated falling edge POCLK.
Table S3457 Common Assignments Descriptions
Name REFCLKP REFCLKN Level Internally Biased Diff. LVPECL LVTTL Description Reference Clock input. Used reference internal clock frequency synthesizer. Internally biased.
DLEB
Diagnostic Loopback Enable. Active Low. Selects diagnostic loopback. When DLEB inactive, S3457 device uses primary data (RSD) clock (RSCLK) inputs. When active, S3457 device uses diagnostic loopback clock data from transmitter. TSD/TSCLK active DLEB mode. Line Loopback Enable. Active Low. Selects line loopback. When LLEB active, S3457 will route data from RSD/RSCLK inputs TSD/TSCLK outputs.
LLEB
LVTTL
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Table S3457 Common Assignments Descriptions (Continued)
Name KILLRXCLK Level LVTTL
Revision June 2001
DEVICE SPECIFICATION
Description Kill Receive Clock input. Active Low. normal operation, KILLRXCLK High. When this input Low, will force POCLK output logic state. Serial Loop Time clock select input. Active High. When active, SLPTIME enables recovered clock from receive section used place synthesized transmit clock. Reference Loop Time clock select input. Active High. When active, RLPTIME enables POCLK from receiver used reference clock input transmitter. RSCLK Clock Squelch. Active High. When SQUELCH active inactive, transmit clock will used place RSCLK. Master Reset. Active Low. Reset input device. During reset, clocks disabled. RSTB should duration REFCLK cycle. Transmit Clock. 155.52 MHz/77.76 Clock output from clock synthesizer. This output should connected reference clock input external clock recovery function. Bypass Clock. Provides alternative serial clock bypassing internal VCO. Internally biased terminated. Bypass Clock select. Active High. Selects between BYPASSCLKP/N clock. REFCLKP/N must high BYPASS mode. should left floating. Ground
SLPTIME
LVTTL
RLPTIME
LVTTL
SQUELCH RSTB
LVTTL LVTTL
TXCLKP TXCLKN BYPASSCLKP BYPASSCLKN BYPASS
Diff. LVPECL Differential LVTTL
AGND
101, 102, 105, 106, 107, 100,
AVCC
+3.3
Power Supply
REFCLK_VCC REFCLK_GND TXCORE_VCC TXCORE_GND LVTTL_VCC LVTTL_GND CMOS_GND CMOS_VCC
+3.3 +3.3 +3.3 +3.3
Power Supply Ground Power Supply Ground Power Supply Ground Ground Power Supply
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Table S3457 Common Assignments Descriptions (Continued)
Name Level 111, 118, 125, +3.3 +3.3 +3.3 +3.3 +3.3 +3.3 +3.3 +3.3 +3.3 +3.3 113, 112, 120, 119, Connected
Revision June 2001
DEVICE SPECIFICATION
Description
TXCLK_GND TXCLK_VCC RSCLK_VCC RSCLK_GND RSD_VCC RSD_GND RXCORE_VCC RXCORE_GND POUT_VCC POUT_GND PCLK_VCC PCLK_GND PIN_VCC PIN_GND BYPCLK_VCC BYPCLK_GND TSCLK_VCC TSCLK_GND TSD_VCC TSD_GND
Ground Power Supply Ground Power Supply Ground Power Supply Ground Power Supply Ground Power Supply Ground Power Supply Ground Power Supply Ground Power Supply Ground Power Supply Ground Power Supply Ground
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Figure S3457 TQFP Pinout
Revision June 2001
DEVICE SPECIFICATION
TXCLK_GND TXCLKN TXCLKP TXCLK_VCC LVTTL_VCC TXCLK_SEL LLEB RSTB DLEB SQUELCH SDLVTTL SDLVPECL KILLRXCLK LVTTL_GND RSCLK_VCC RSCLKP RSCLKN RSCLK_GND RSD_GND RSDP RSDN RSD_VCC RXCORE_VCC RXCORE_GND POUT_VCC POUTP0 POUTN0
POUTP1 POUTN1 POUT_VCC POUT_GND POUTP2 POUTN2 POUTP3 POUTN3 POUT_VCC POCLKP POCLKN POUT_GND RXCORE_VCC RXCORE_GND TXCORE_GND TXCORE_VCC PCLK_VCC PCLKP PCLKN PHERRP PHERRN PCLK_GND PIN_GND PICLKP PICLKN PINP0 PINN0
TXCORE_VCC TXCORE_GND TSD_GND TSD_VCC TSDN TSDP TSD_VCC TSD_GND TSCLK_GND TSCLK_VCC TSCLKN TSCLKP TSCLK_VCC TSCLK_GND AGND AVCC AGND AGND AGND CAP2 CAP1 AGND AGND AVCC AGND AGND AVCC
S3457 Pinout TQFP/TEP VIEW
LVTTL_GND BYPASS LVTTL_GND RLPTIME SLPTIME LVTTL_VCC TXCORE_VCC TXCORE_GND BYPCLK_VCC BYPASSCLKP BYPASSCLKN BYPCLK_GND CMOS_VCC LOCKDET CMOS_GND REFCLK_VCC REFCLKP REFCLKN REFCLK_GND PIN_VCC PHINITP PHINITN PINN3 PINP3 PIN_GND PINN2 PINP2 PINN1 PINP1 PIN_VCC
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Figure Compact TQFP Package Drawing
Revision June 2001
DEVICE SPECIFICATION
Table Thermal Management
Device S3457 Package Power (Still Air) 23.5°C/W
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Table Performance Specifications
Parameter Nominal Center Frequency Clock Synthesizing Unit (CSU) Output Jitter STS-48 Reference Clock Frequency Tolerance Reference Clock Input Duty Cycle Reference Clock Rise Fall Times -100 2.488 Units
Revision June 2001
DEVICE SPECIFICATION
Condition
0.005 +100
(rms)
Output jitter measured SONET operating rate using appropriate filter. jitter, lock. required meet SONET output frequency specification.
amplitude.
Table Absolute Maximum Ratings
Parameter Storage Temperature Voltage with respect Voltage LVPECL/LVDS Input High-Speed LVPECL Output Source Current
Electrostatic Discharge (ESD) Ratings S3457 rated following voltages based human body model: pins rated Volts.
-0.5
+3.6
Units
Table Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Voltage with respect Voltage LVPECL/LVDS Input Voltage LVTTL Input ICC1
Output terminated.
3.135
Units
3.465
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Table LVTTL Input/Output Characteristics
Parameter Description Input High Voltage Input Voltage Input High Current Input Current Output High Voltage -500 LVTTL
Revision June 2001
DEVICE SPECIFICATION
Units
Conditions LVTTL LVTTL -100
Output Voltage
Table Internally Biased Differential LVPECL Input Characteristics
Parameter VINSINGLE VINDIFF Description LVPECL Input Voltage LVPECL Input High Voltage Single Ended Input Voltage Swing Differential Input Voltage Swing Input Bias Input Current Input High Current -1.25 -0.65 -220 -0.5 -1.4 -0.55 1200 2400 -0.35 Units -0.5 Figure Figure Conditions
VBIAS
Table Differential LVPECL Output Characteristics
Parameter VOUTSINGLE VOUTDIFF Description Single Ended Output Voltage Swing Differential Output Voltage Swing Output High Voltage Output Voltage 1000 -1.2 -1.95 1900 -0.65 -1.50 Units Conditions Figure Figure
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Table Single-Ended LVPECL Input Characteristics1
Parameter Description PECL Input Voltage PECL Input Voltage PECL Input High Voltage PECL Input High Voltage Input Current Input High Current -2.0 -2.0 -1.15 -1.023 -100 -1.5 -1.441 -0.75 -0.55
Revision June 2001
DEVICE SPECIFICATION
Units
Conditions Guaranteed -20°C. Guaranteed 85°C. Guaranteed -20°C. Guaranteed 85°C. -0.5
AMCC LVPECL inputs (VIL VIH) non-temperature compensated I/O, which vary mV/°C.
Table LVDS Input Characteristics
Parameter Description Input High Voltage Input Voltage Unit Conditions Over process, voltage temperature range. Over process, voltage temperature range. Figure Over process, voltage temperature range. Figure Over process, voltage temperature range. Over process, voltage temperature range. -0.5
VINDIFF
Input Voltage Differential
2600
VINSINGLE RDIFF
Input Single Ended Voltage Differential Input Resistance Input Current Input High Current
-300
1300
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Table LVDS Output Characteristics1
Parameter VOUTDIFF VOUTSINGLE Description Output High Voltage Output Voltage Output Differential Voltage Output Single-Ended Voltage 1.25 0.85 1100 Unit
Revision June 2001
DEVICE SPECIFICATION
Conditions Over process, voltage temperature range. Over process, voltage temperature range. Over process, voltage temperature range. Figure Over process, voltage temperature range. Figure
Output loading line line.
Table Differential Output Characteristics
Parameter (Data) (Data) VOUTDIFF (Data) VOUTSINGLE (Data) (Clock) (Clock) VOUTDIFF (Clock) VOUTSINGLE (Clock) Description Output Voltage Output High Voltage Serial Output Differential Voltage Swing Serial Output SingleEnded Voltage Swing Output Voltage Output High Voltage Serial Output Differential Voltage Swing Serial Output SingleEnded Voltage Swing -1.0 -0.35 -0.65 -0.2 1600 Units Condition line line. line line. line line. Figure line line 2.488 Gbps. Figure line line. line line. line line. Figure line line 2.488 GHz. Figure
-1.5 -0.5
-0.85 -0.25 1800
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Table Differential Input Characteristics
Parameter VINDIFF VINSINGLE RDIFF Description Input Input High Differential Input Voltage Swing Single-Ended Input Voltage Swing Differential Input Resistance -1.7 -0.55
Revision June 2001
DEVICE SPECIFICATION
-0.6 -0.15 2400 1200
Units
Comments
Figure Figure
Table Transmitter Low-Speed Timing Characteristics (PICLKP/N 622.08 MHz)
Parameter Description PICLKP/N Duty Cycle (See Figure tSPIN tHPIN PINP/N[3:0] Set-up Time w.r.t. rising edge PICLKP (See Figure PINP/N[3:0] Hold Time w.r.t. rising edge PICLKP (See Figure PCLKP/N Duty Cycle LVDS Output Rise Fall Time (20% 80%) TXCLKP/N Duty Cycle PCLK PICLK drift after FIFO centered
Assume load.
Units
3001
Figure Transmitter Input Timing
(622.08 MHz) PICLKP
tSPIN tHPIN
PINP/N[3:0]
When setup time specified LVDS signals between input clock, set-up time time picoseconds from crossover input crossover point clock. When hold time specified LVDS signals between input clock, hold time time picoseconds from crossover point clock crossover input.
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Table Transmitter High-Speed Timing Characteristics
Parameter TSCLK Frequency TSCLK Duty Cycle TSCLK Duty Cycle Distortion w.r.t. RSCLK BYPASSCLK SLPTIME, LLEB BYPASS modes) tSTSD tHTSD Setup Time w.r.t. TSCLKP Rising (See Figure Hold Time w.r.t. TSCLKP Rising (See Figure Output Rise Fall Time (20% 80%) Description
Revision June 2001
DEVICE SPECIFICATION
2.488
Units
Figure Transmitter Output Timing
TSCLKP tSPIN
tHPIN
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Table Receiver Characteristics
Parameter Parameter POCLKP/N TX_CLKP/N Duty Cycle POCLKP/N Rise Time POUTP/N Rise Time POCLKP/N Fall Time POUTP/N Fall Time tSRSD tHRSD POUTP/N Delay from POCLKP/N POUTP/N[3:0] Set-Up Time w.r.t. POCLK POUTP/N[3:0] Hold Time w.r.t. POCLK RSDP/N Setup Time w.r.t. RSCLKP RSDP/N Hold Time w.r.t. RSCLKP RSCLK Duty Cycle RSCLK Frequency 2.488 1000 Units
Revision June 2001
DEVICE SPECIFICATION
Test Conditions line line. 20%-80%, line line.
20%-80%, line line.
Figure Figure Figure Figure Figure
Figure Parallel Data Output Delay from POCLK
POCLKP
POUTP/N[3:0]
tPDmin tPDmin tPDmax 1000 tPDmax
Figure Receiver Input Timing Diagram
RSCLKP tSRSD tHRSD
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S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver
Figure Differential Voltage Measurement
V(+) VSWING V(-)
Revision June 2001
DEVICE SPECIFICATION
V(+) V(-)
VSWING 0.0V
Figure Phase Adjust Timing
4-10 BYTE CLOCKS
BYTE CLOCKS PHERR
PHINIT
PCLKP
PICLKP
TRANSFER (Internal)
Note: byte clock 622.08 MHZ.
AMCC Confidential Proprietary
S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver
Figure Differential Output PECL Input Coupled termination
Revision June 2001
DEVICE SPECIFICATION
+3.3 0.01 Zo=50 0.01 Zo=50
S3457 TSDP/N TSCLKP/N
Figure Differential Output +3.3 LVPECL Input Coupled Termination
+3.3 Zo=50 Zo=50
+3.3
S3457 TSDP/N TSCLKP/N
Figure Differential LVPECL Driver Differential LVPECL Input Termination
+3.3
Zo=50
+3.3
Zo=50
S3457 TXCLKP/N
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S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver
Revision June 2001
DEVICE SPECIFICATION
Figure Differential PECL Driver S3457 Differential Input Coupled Termination
0.01 Zo=50
-0.5
+3.3
0.01 Zo=50
-0.5 S3457 RSDP/N RSCLKP/N
Figure +3.3 Differential Driver S3457 Differential Input Direct Coupled Termination
+3.3
Zo=50
+3.3 -0.5
Zo=50
-0.5 S3457 RSDP/N RSCLKP/N BYPASSCLKP/N
Figure Differential PECL Driver S3457 Internally Biased Differential LVPECL Input Coupled Termination
0.01
Zo=50
-0.5
+3.3
0.01
Zo=50
-0.5 S3457 REFCLKP/N
155.52 OSCILLATOR
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S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver
Revision June 2001
DEVICE SPECIFICATION
Figure +3.3 Differential LVPECL Driver S3457 internally Biased Differential LVPECL Input Coupled Termination
+3.3 Zo=50 Zo=50
-0.5
+3.3
-0.5 S3457 REFCLKP/N
155.52 OSCILLATOR
Figure S3457 LVDS Driver LVDS Input
+3.3
Zo=50 Zo=50
+3.3
S3457 POUTP/N[3:0] POCLKP/N PCLKP/N PHERRP/N
LVDS Input
Figure LVDS Driver S3457 LVDS Inputs
+3.3
Zo=50 Zo=50
+3.3
LVDS
S3457 PINP/N[3:0] PICLK PHINIT
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S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver
Figure External Loop Filter Components
Revision June 2001
DEVICE SPECIFICATION
CAP1
CAP2
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S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver
Ordering Information
Prefix Integated Circuit Device 3457 Package
TQFP
Revision June 2001
DEVICE SPECIFICATION
Revision
Prefix
XXXX
Part
Package
Revision
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPO APPLICATIO DEVICES SYSTEMS THER CRIT ICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 2001 Applied Micro Circuits Corporation. D507/R740 AMCC Confidential Proprietary

S3457TT20 OC-48 SONET/SDH/A4-Bit Transceiver SiGe BiCMOS Tec

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