User's Manual 11.97 2161 Revision History: Previous Version: Page
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Audio Ringing Codec Filter Basic Function ARCOFI®-BA 2161 Version
User's Manual 11.97
2161 Revision History: Previous Version: Page Page previous current Version) Version)
Current Version: 1997-11-01 Preliminary Data Sheet 08.95 Subjects (major changes since last revision)
bypass mode MIC, HOC, reserved internal tests
Edition 1997-11-01 This edition realized using software system FrameMaker®. Published Siemens Bereich Halbleiter, MarketingKommunikation, 81541 Siemens 1997. Rights Reserved. Attention please! patents other rights third parties concerned, liability only assumed components, applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. questions technology, delivery prices please contact Semiconductor Group Offices Germany Siemens Companies Representatives worldwide (see address list). technical requirements components contain dangerous substances. information types question please contact your nearest Siemens Office, Semiconductor Group. Siemens approved CECC manufacturer. Packing Please recycling operators known you. also help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred. Components used life-support devices systems must expressly authorized such purpose! Critical components1 Semiconductor Group Siemens only used life-support devices systems2 with express written approval Semiconductor Group Siemens critical component component used life-support device system whose failure reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain human life. they fail, reasonable assume that health user endangered.
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Table Contents 1.8.1 1.8.2 1.8.3 1.8.4 1.8.5 1.8.6 1.8.7 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 2.2.4 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.4.5 2.2.4.6 2.3.1 2.3.2 2.3.3 2.3.4
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Overview Comparison between 2161 2160 Table Symbols Features Configurations Definitions Functions Logic Symbol Functional Block Diagram System Integration ISDN-Voice Terminal Digital PABX Voice Terminal Terminal Adapter Analog Telephones Voice/Data Terminal (PC-Card) Multifunctional ISDN Terminal IOM®-2 Line Card Application Group Fax/Modem Adapter Functional Description Analog Front (AFE) Description Description Analog Attenuation Plan Interface Acoustic Transducers ARCOFI® Signal Processor (ASP) Description Transmit Signal Processing Receive Signal Processing Programmable Coefficients Tone Generation Tone Generation Architecture Control Generator Tone Generator Tone Filter Tone Level Adjustment DTMF Generator (transmit) ARCOFI® Digital Interface (ADI) PCI-Interface IOM®-2 Frame Structure Timing Modes Serial Control Interface Serial Data Interface Test Functions
Semiconductor Group
1997-11-01
2161
Table Contents 3.4.1 3.4.2 3.4.2.1 3.4.2.2 3.4.2.3 3.4.3 4.10 4.11 4.12 4.13 7.3.1 7.3.2 7.3.3 8.2.1
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Operational Description Reset Initialization ARCOFI® Operating Modes IOM®-2 Interface Protocol IC-Channels (IOM®-2 Mode) Monitor Channel Channel Data Structure Transfer Protocol Implementation MON-Channel Protocol Command/Indication Channel Mode) ARCOFI® Voice/Data Manipulation (VDM) Detailed Register Description Command Register (CMDR) General Configuration Register (GCR) Data Format Interface Configuration Register (DFICR) Programmable Filter Configuration Register (PFCR) Tone Generator Configuration Register (TGCR) Tone Generator Switch Register (TGSR) Transmit Configuration Register (ATCR) Receive Configuration Register (ARCR) Test Function Configuration Register (TFCR) Configuration Register (SDICR); mode only Time Slot Configuration Register (TSCR); mode only Extended Configuration Register (XCR) Test Mode Register (TMR) Electrical Characteristics Package Outlines .102 Application Note Layout Wiring Recommendations .106 Introduction .106 Layout Considerations .107 Connecting Analog Front .108 Outputs Earpiece Loudspeaker .108 Differential Microphone Inputs .109 Single Ended Input .113 ARCOFI® Telephone Board SIPB 5132-SP Board Description .117 Introduction .117 Hardware Configuration .118 Floor Plan Switches .118
Semiconductor Group
1997-11-01
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Table Contents 8.2.2 8.4.1 8.4.2 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.2.1 9.2.2 9.2.2.1 9.2.2.2 9.2.2.3 9.2.2.4 9.2.2.5 9.2.2.6 9.2.3 9.2.4 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.5.1 9.4.1 9.4.2 9.4.3 9.5.1 9.5.2
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Connectors .120 Hardware Environment .122 Trackfiles .124 Trackfile IOM®-2 Mode .124 Trackfiles IOM®-2 NON-TE Mode .127 Circuit Diagram .135 ARCOFI® Coefficients Software SIPO 2163 User's Manual .139 Introduction .139 ARCOFI®-SP 2163 .139 ARCOFI®-BA 2161 .139 ARCOS-SP PLUS Software .140 System Requirements .141 Installation Activation ARCOS-SP PLUS .141 Using ARCOS-SP PLUS .143 Introduction .143 Menu Line .144 Using Menu Line .144 Pull-Down Menu "File" .144 Pull-Down Menu "ARCOFI" .146 Pull-Down Menu "Show" .146 Pull-Down Menu "Board" .146 Pull-down Menu "Options" .147 User Area .147 Command Line .150 Generating Correction Filter Coefficients .154 Filter Implementation Theory Calculation .154 Calculation Coefficients .155 Reading Filters .160 Examples Usage FX/FR Filters .160 Adapting Filters Target Frequency Response .160 Using "Execute" Feature Calculate Coefficients .162 Hardware Setup with ARCOS-SP PLUS .164 Introduction .164 Using SIPB 5000 System .164 Other Hardware Tools .167 Error Messages Troubleshooting .171 Hardware related Problems .171 Other Problems .173
Semiconductor Group
1997-11-01
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Table Contents 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.3 10.3.1 10.3.2 10.3.3 10.4 10.5 10.6 11.1 11.2 11.3 11.4 11.5
Page
Application Note Analog Line Interface with ARCOFI®-BA .177 Introduction .177 Realization .178 General Architecture .178 Characteristic .180 Impedance Matching .181 2-wire 4-wire Conversion .182 Transhybrid Balance .184 Hook-Switch Pulse Dialling .185 Ring Detection .186 Circuit Diagram .187 Component Values .187 Circuit Diagram .190 Circuit Diagram .191 Measurement Results .192 Line Interface Linecard .193 Appendix .195 Application Note Using ARCOFI®-BA with SLIC .199 Introduction .199 Harris SLIC HC5502B .200 Resistive Impedance Matching .203 Complex Impedance Matching .204 Measurement Results .207
IOM®, IOM®-1, IOM®-2, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, ARCOFI® ARCOFI®-BA, ARCOFI®-SP, EPIC®-1, EPIC®-S, ELIC®, ITAC®, ISAC®-S, ISAC®-S ISAC®-P ISAC®-P registered trademarks Siemens
Semiconductor Group
1997-11-01
2161
Overview Overview
2161 ARCOFI-BA provides design engineer with cost-optimized Audio, Ringing, Codec, Filter processor solution simple digital terminals. offers minimum functions necessary develop low-cost telephone with high flexibility technics. Remark: more sophisticated digital terminals (e.g. comfort telephones offering speakerphone, voice/data terminals) recommend Siemens ARCOFI-SP 2163. typical applications ARCOFI-BA are: low-cost digital telephone low-cost facsimile terminal low-cost answering machine
Note: Throughout this whole document "ARCOFI" refers ARCOFI-BA 2161.
ARCOFI performs encoding, decoding filtering functions according ITU-T ETSI (NET33) norms. Full featured applications possible without external elements. necessary hardware software implemented. transducer correction filters (one each direction) programmed optimum adaptation different transducer frequency characteristics. ARCOFI provides universal tone generator automatic generation multitone sequences which used tone alerting, call progress tones other audible feedback tones. DTMF generator transmit direction also available. This flexible tone generator concept fulfills wide range applications. interfacing handset mouth earpiece facilitated flexible analog front end. loudspeaker output also been integrated chip well secondary input handsfree microphone. analog inputs outputs gain programmable through software. digital side ISDN-Oriented Modular (IOM-2) interface terminal (TE) nonterminal (NON-TE) applications Serial Control/Data Interface (SCI SDI) realized connect layer-1/2 devices ARCOFI. ARCOFI BlCMOS-device, available P-DSO-28-1 package. operates from single supply features power-down state with very power consumption.
Semiconductor Group
1997-11-01
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Overview Comparison between 2161 2160 2160 CMOS technology P-DIP-24 P-LCC-28 supply Comment
Table main differences: 2161 BICMOS technology P-DSO-28-1 Single supply Reduced power consumption power down operating modes
Interface IOM-2 NON-TE Interface; Serial Control/Data Interface Flexible configuration concept Buffered Dual Port Coefficient-RAM (reprogramming Coefficient-RAM operating modes without acoustical effects) Separate digital output piezo ringer Multiplexed digital output piezo ringer Fully programmable, high performance BICMOS technology Ringing directly loudspeaker (simultaneously signalling over loudspeaker voice over earpiece possible) Sidetone gain stage with higher resolution (two byte coefficient) Extended tone generation unit receive transmit direction Partial programmable Analog Front (AFE) Ringing loudspeaker only over common receiver path (simultaneously signaling over loudspeaker voice over earpiece possible) Sidetone gain stage with resolution (one byte coefficient) Simple tone generation unit receive direction DTMF generator transmit direction
Digital high pass receive direction Monitoring mode digital analog voice recording Additional test loops ETSI (NET33) ITU-T G.712 ITU-T G.712
Note: Many slightly improvements realized 2161 documented this table.
Semiconductor Group
1997-11-01
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Overview AIMX ALTF ARCOFI CCITT CMDR CRAM DCLK DHON DHOP DHPR DHPX Table Symbols Address ARCOFI (IOM-2 mode) Analog Digital converter ARCOFI Digital Interface Analog Front Handset Output Amplifier Analog Input Multiplexer control bits (ATCR) Analog Loop Converter (TFCR) Analog Loop Front (TFCR) Analog Loop Interface (TFCR) Analog Loop Noise Shaper (TFCR) Loudspeaker Amplifier Analog Loop Test Function bits (TFCR) Analog Loop Z-side tone gain stage Microphone Amplifier Audio Ringing Codec Filter ARCOFI Signal Processor Auxiliary Input Beat Mode (TGCR) Beat Tone (TGCR) Chip Address Mode (IOM-2 chip mode; GCR) International Telegraph Telephone Consultative Committee Control Generator (TGCR) Command Register Coefficient Operation (CMDR) Configuration Register Coefficient Chip Select active (serial control interface) Digital Analog converter Double Clock Enable DCLK (SDICR) IOM-2 interface clock Data Clock (serial data interface) IOM-2 Data Downstream Decimation filter Disable (XCR) Disable (XCR) Disable High Pass Receive (PFCR) Disable High Pass Transmit (PFCR) Digital Loop Noise Shaper (TFCR) Digital Loop PCM-register (TFCR)
Semiconductor Group
1997-11-01
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Overview Table Symbols (cont'd) DLSN DLSP DLTF DRAM DTMF EPP0 EPP1 ETSI EVREF EWDF IDENT ISDN ITU-T Digital Loop Signal processor (TFCR) Disable (XCR) Disable (XCR) Digital Loop Test Function bits (TFCR) Data Receive (serial data interface) Data Digital Signal Processor Dual Tone (TGCR) Dual Tone Multi Frequency (TGSR) IOM-2 Data Upstream Data Transmit (serial data interface) Earpiece Enable Push-Pull DU/DX (SDICR) Enable Push-Pull SA/SDX (SDICR) Enable Tone Filter (TGCR) European Telecommunications Standards Institute Enable Voice Transmit (GCR) Enable VREF buffer (ATCR) Electrical Wave Digital Filter Frequency correction Receive (PFCR) IOM-2 SDI-Frame Synchronization kHz) Frequency correction Transmit (PFCR) Receive Gain (PFCR); Receive gain stage Transmit Gain (PFCR); Transmit gain stage Z-side tone Gain (PFCR); Z-side tone Gain stage Handset Output Handset Output Control bits (ARCR) Handset earpiece Output Handset earpiece Output High-pass filter receive High-pass filter transmit Identification Code Initialize Data (TFCR) Interpolation filter ISDN-Oriented Modular Integrated Services Digital Network International Telecommunication Union -Telephone
Semiconductor Group
1997-11-01
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Overview Table Symbols (cont'd) MCLK MCLKR MIN1/2 MIP1/2 PABX SA-SD SCLK SLOT SQTR A-Law/µ-Law (GCR) Linear data mode (VDM; DFICR) Loudspeaker Loudspeaker Control bits (ARCR) Loudspeaker output Loudspeaker output Master Clock (synchronized system clock) Master Clock Rate (SDICR) Microphone Control bits (ATCR) Microphone inputs pins Microphone inputs pins Operation (CMDR) Test mode (TFCR) Private Automatic Branch Exchange Peripheral Control Interface Pulse Code Modulation Piezo Mode; output digital pins PZ1/PZ2 (TGSR) Power-On Reset Power-Up (GCR) Reverse Channel Mode (CMDR) Reset Read/Write operation (CMDR) Receive path pins; control bits (SDICR) Serial Control Interface Serial Clock (serial control interface) Serial Data Interface Serial Data Receive (serial control interface) Serial Data Transmit (serial control interface) IOM-2 Slot select mode (GCR) Stop Mode (TGCR) Status Operation (CMDR) Square/Trapezoid mode (TGCR) Square/Trapezoid Generator
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Overview Table Symbols (cont'd) Terminal Equipment Tone Generator (TGCR) Three party conferencing (VDM; DFICR) Tone Ringing Loudspeaker (TGSR) Tone Ringing Receive (TGSR) Tone Ringing Transmit (TGSR) Time-Slot Selection SDI-mode (TSCR) Transmit path Voltage supply Analog Voltage supply Power amplifiers Voice Data Manipulation bits (DFICR) Reference Voltage output Analog ground Digital ground Analog ground Power amplifiers Wave Digital Filter Extended Operation (CMDR)
VDDP
VREF VSSA VSSD VSSP
Semiconductor Group
1997-11-01
Audio Ringing Codec Filter Basic Function ARCOFI-BA
2161
Version Features
BICMOS
Applications digital terminal equipment featuring voice functions Digital signal processing performs CODEC functions Fully compatible ITU-T ETSI (NET33) specification A-Law/µ-Law ITU-T) 16-bit linear P-DSO-28-1 data Flexible configuration internal functions IOM-2 interface NON-TE mode), Serial Control Interface (SCI) Serial Data Interface (SDI) Three analog inputs: differential, high performance inputs microphones single-ended auxiliary input differential outputs handset earpiece (200 loudspeaker sine wave square wave loudspeaker driver capability Separate digital output piezo ringer Flexible Peripheral Control Interface (PCI) IOM-2 mode Flexible test maintenance loopbacks analog front digital signal processor Independent gain programmable amplifiers analog inputs outputs Buffered Dual Port Coefficient-RAM (reprogramming Coefficient-RAM operating modes without acoustical effects) transducer correction filters Side tone gain adjustment Flexible DTMF, tone ringing generator Single power supply power consumption: standby operating consumption dependent selected operating mode Advanced BICMOS technology
Type 2161
Semiconductor Group
Ordering Code Q67101-H6763
Package P-DSO-28-1
1997-11-01
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Overview Configurations
P-DSO-28-1
VSSD SD/CS SC/SCLK SB/SDR SA/SDX DD/DR DU/DX MIP1 MIN1 MIN2 MIP2 VDDP
2161
ITP06366
AD/MCLK MODE DCL/DCLK VSSA VREF VSSP
Figure
Semiconductor Group
1997-11-01
2161
Overview Definitions Functions
Symbol Input Function Output Open Drain (OD)
VDDP VSSD VSSA VSSP
MODE MCLK
Power supply Power supply Digital Ground Analog Ground Analog Ground Mode Selection: IOM-2 serial control/data interface IOM® Address: Chip address IOM-2 chip mode Master Clock: Synchronous system clock when serial control/data interface selected Reset: high signal this forces ARCOFI into reset state Frame Sync: 8-kHz frame synchronization signal (IOM-2 mode) DCL-System Clock: 1.536 supplied application system clock when IOM-2 mode selected DCLK Data Clock: Data clock serial data interface (SDI) Data Downstream: Receive data from layer-1 IOM-2 controlling device Data Receive: Receive data serial data interface (SDI) Digital Piezo Ringer Output: When selected tone ringer routed this output (PZ1 opposite phases)
DCLK
I/(OD)
DD/DU-voice channel swapping (XOP_D)
Semiconductor Group
1997-11-01
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Overview Definitions Functions (cont'd) Symbol Input Function Output Open Drain (OD) OD/I Data Upstream: Transmit data layer-1 IOM-2 controlling device Data Transmit: Transmit data serial data interface (SDI) Programmable This port only available IOM-2 mode Chip Select: level indicates microprocessor access serial control interface (SCI) Programmable This port only available IOM-2 mode Serial Clock: Clock signal serial control interface (SCI) Programmable This port only available IOM-2 mode Serial Data Receive: Receive data line serial control interface (SCI) Programmable This port only available IOM-2 mode Serial Data Transmit: Transmit data line serial control interface (SCI) Output: Output biasing analog single-ended inputs Microphone Input This highly symmetrical differential input been designed commonly used telephone microphones
OD/O
SCLK
OD/O
VREF
MIP1 MIN1
DD/DU voice channel swapping (XOP_D) Programmable SDICR.EPP0 Programmable SDICR.EPP1
Semiconductor Group
1997-11-01
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Overview Definitions Functions (cont'd) Symbol Input Function Output Open Drain (OD) MIP2 MIN2 Microphone Input This highly symmetrical differential input been designed commonly used telephone microphones Auxiliary Input: Single-ended auxiliary input Loudspeaker Output: LSP, differential output pins which drive loudspeaker directly; piezo transducer also used ringing signal instead loudspeaker Handset Earpiece Output: HOP, differential output pins which drive handset earpiece transducers directly
Semiconductor Group
1997-11-01
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Overview Logic Symbol
Reset
/SDI Data /SDI Clock/Frame Mode Address/ System Clock
Microphone Input Microphone Input Auxiliary Input Loudspeaker Handset Earpiece MIP1 MIN1 MIP2 MIN2
VSSD VSSA VDDP VSSP VREF
DD/DR DU/DX
ARCOFI 2161
DCL/DCLK MODE AD/MCLK
SCLK
PCI/SCI Interface
Piezo Ringer
ITL09466
Figure Logic Symbol ARCOFI®
Semiconductor Group 1997-11-01
2161
Overview Functional Block Diagram
Configuration Coefficients
Peripheral Control Serial Control Interface Analog Front Data Digital Signal Processor Data Serial Data Interface
PCI/SCI
Audio
-2/SDI
Timing Unit Reset Logic
ITB05593
Figure Block Diagram ARCOFI®
Semiconductor Group 1997-11-01
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Overview System Integration
complete family digital terminals offered Siemens simplifies development these devices gives cost-effective solution design engineer. architecture these terminals based modular interface especially conceived ISDN named IOM-2. Figure shows example integrated multifunctional ISDN terminal using ISAC-S ISAC-S (ISAC-S: ISDN S-Access controller 2186) provides S-interface separates channels. voice processor connected programmable digital signal processing codec filter (ARCOFI-BA) data encryption module data device IC2. used voice communication data communication. Typical terminal applications described next sections.
ISAC 2186
Speech Processing
ARCOFI 2161
Data Encryption
ITAC 2110
e.g. V.24 Speech Modules Data Modules
ITS09467
80C5XX 80C16X
Figure Example ISDN Voice/Data Terminal
Semiconductor Group
1997-11-01
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Overview 1.8.1 ISDN-Voice Terminal
Figure shows typical solution voice terminal interface. ARCOFI offers functions CODEC filtering. also carries functions tone ringing, DTMF, conversions. ARCOFI permits direct connection handset loudspeaker. ARCOFI programmed read lOM-2 interface ISAC-S same supervises keyboard functions function hookON/OFF. S-interface functions such activation/deactivation, clock recovery, clock resynchronization well layer-2 functions like LAPD protocol handling executed ISDN Subscriber Access Controller. U-interface telephone easily derived from voice terminal shown figure replacing ISAC-S with ISDN Communication Controller 2070 ISDN-Echo Cancellation Unit IEC-Q (PSB 21910). Figure shows such typical solution voice terminal with U-interface. both cases whole terminal power supplied ISDN Converter Circuit IDCC 2023.
Semiconductor Group
1997-11-01
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Overview
S-Interface
Power Controller IDCC 2023
ISAC 2186
Keyboard
ARCOFI 2161
ISDN Basic Phone
Terminal
further modules
ITS09468
Figure Basic ISDN S-Voice Terminal
Semiconductor Group 1997-11-01
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Overview
Power Controller IDCC 2023
IEC-Q 21910
Keyboard
2070
ARCOFI 2161
ISDN -Voice Terminal
Terminal
further modules
ITS09469
Figure Basic ISDN U-Voice Terminal
Semiconductor Group 1997-11-01
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Overview 1.8.2 Digital PABX Voice Terminal
Serial Control Interface allows ARCOFI programmed directly from serial port microcontroller. voice data transmitted IOM-2 interface interface provided from other transceiver devices. Serial Data Interface (SDI) selected data rate vary from kbit/s 4096 kbit/s. Figure shows PABX voice terminal using ISAC-P 2196 together with microcontroller. Figure shows PABX-voice terminal using transceiver device without IOM-2 interface.
Keyboard
Power Controller IDCC 2023
ISAC 2196
ARCOFI 2161
ITS09470
Figure PABX Voice Terminal
Semiconductor Group 1997-11-01
2161
Overview
Power Controller GPPC 2121 Serial Control Interface (SCI)
SmartLink 2197
Keyboard
ARCOFI 2161
ITS09471
Figure PABX Voice Terminal NON-IOM®-2 Architecture
Semiconductor Group 1997-11-01
2161
Overview 1.8.3 Terminal Adapter Analog Telephones
Figure shows implement terminal adapter (tip/ring) connecting analog telephones ISDN world. SLIC connected ARCOFI. ring information transmitted transparently through ARCOFI C/I-channel channel through ISAC-S
S-Interface
ISAC 2186
Tip/Ring Interface ARCOFI 2161
SLIC Terminal Adapter Analog Telephones
Terminal
further modules
ITS09472
Figure Terminal Adapter Tip/Ring Analog Telephones
Semiconductor Group 1997-11-01
2161
Overview 1.8.4 Voice/Data Terminal (PC-Card)
Figure shows voice/data terminal developed PC-card. HSCX-TE (PSB 21525) offers cost data interface (e.g. X.25) from host ISDN world IOM-2 interface. card powered thus power controller necessary.
Voice
Terminal
ARCOFI 2161
HSCX-TE 21525
ISAC 2186
S-Interface
Interface
ITS09473
Figure PC-Card ISDN Voice/Data Terminal 1.8.5 Multifunctional ISDN Terminal
Figure gives example multifunctional terminal. HSCX-TE 21525 (High-Level Serial Communications Controller Extended Terminal Applications) simplifies realization intelligent X.25 terminal adapter module whereas ITAC 2110 offers X.21, V.24, V.110 V.120 interfaces ISDN terminals. connected ISAC-S 2186 system master. other slaves. When slave wants access bus, informs master C/l-channel IOM-2 channel
Semiconductor Group
1997-11-01
2161
Overview
S-Interface
Power Controller IDCC 2023
ISAC 2186
Keyboard
ARCOFI 2161
ISDN Basic Phone
Terminal
V.24/X.21
Drivers
Intelligent V.24 (X.21) Module
ITAC 2110
X.25
Drivers
Intelligent X.25 Module
HSCX-TE 21525
ITS09474
Figure Multifunctional ISDN Terminal
Semiconductor Group 1997-11-01
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Overview 1.8.6 IOM®-2 Line Card Application
Some applications require ARCOFI connect directly IOM-2 interface line card. channel selected pin-strapping. ARCOFI programmed MONITOR channel selected channel. ARCOFls distinguished input same channel. This configuration allows control ARCOFls IOM-2 interface line card controller.
ARCOFI 2161
(NON-TE)
ARCOFI 2161
EPIC 2054/6 ELIC 20550
ARCOFI 2161
ITS09475
Figure ARCOFI® Line Card Application
Semiconductor Group 1997-11-01
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Overview 1.8.7 Group Fax/Modem Adapter
ARCOFI connected standard modem chip designed analog networks. ARCOFI converts analog signal data which transmitted over digital network.
S-Interface
ISAC 2186
V.24
Fax/Modem
ARCOFI 2161
ITS09476
Figure Group Fax/Modem Adapter
Semiconductor Group
1997-11-01
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Functional Description Functional Description
ARCOFI bridges between audio world microphones, earphones, loudspeakers digital world providing full Codec with necessary transmit receive filters. block diagram ARCOFI shown figure ARCOFI subdivided three main blocks: ARCOFI Analog Front (AFE) ARCOFI Signal Processor (ASP) ARCOFI Digital Interface (ADI) detailed description found following chapters.
VDDP
Control
VREF
MIP2 MIN2 MIP1 MIN1
VREF
AINMUX Data Codec Filter
Peripheral Control Serial Control Interface Serial Data Interface
SA/SDX SB/SDR SC/SCLK SD/CS
DU/DX DD/DR
Reset Timing Unit
DCL/DCLK AD/MCLK MODE
VSSP
VSSA
VSSD
ITB06379
Figure Architecture ARCOFI®
Semiconductor Group
1997-11-01
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Functional Description Analog Front (AFE) Description
Analog Front section ARCOFI interface between analog transducers digital signal processor. transmit direction, function amplify transducer input signals (microphones) convert them into digital signals. receive section, incoming digital signal converted analog signal which output earpiece and/or loudspeaker. block diagram shown figure
VREF
MIP2 MIN2 MIP1 MIN1 AINMUX
VREF
BYP, 0.36 (6-dB Steps) PREFI
BYP, 9.-24 (3-dB Steps) 0.-24 (6-dB Steps) POFI
Level Shift Square
ITS06380
Figure Signal Flow Graph
Semiconductor Group
1997-11-01
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Functional Description 2.1.1 Description Analog
differential inputs (MIP1/MIN1 MIP2/MIN2) single-ended input (AXI) connected amplifier analog input multiplexer. programmable amplifier provides coarse gain adjustment range. Fine gain adjustment performed digital domain programmable gain adjustment stage (see signal processor section). This allows perfect level adaptation various types microphone transducers without loss signal noise performance. Fully differential output HOP/HON connects amplifier handset earpiece. Differential output LSP/LSN provided with loudspeaker. (sine wave) power delivered loudspeaker amplifier ALS. programmable amplifiers provide coarse gain adjustment range. Fine gain adjustment performed digital domain programmable adjustment stage implemented configuration registers (ATCR, ARCR) provide high flexibility accommodate extensive user procedures terminal attributes. 2.1.2 Attenuation Plan
Transmit Direction Parameter Transmit MIP1/MIN1 MIP2/MIN2 Microphone input level gain MIP1/MIN1 MIP2/MIN2 Microphone input level gain Input level gain Input level gain Limit Values 0dBm0 2.65E-02 1.87E-02 32.33 1.67E-00 1.18E-00 3.67 1.06E-01 7.46E-02 20.37 8.36E-01 5.91E-01 2.33 max. 3.81E-02 2.70E-02 32.86 29.19 2.40E-00 1.70E-00 3.14 6.81 1.51E-01 1.07E-01 20.86 17.19 1.20E-00 8.49E-01 2.86 0.81 Vrms dBm0 Vrms dBm0 Vrms dBm0 Vrms dBm0 1.18 0.775 1.18 0.775 1.18 0.775 1.18 0.775 Unit Reference
Semiconductor Group
1997-11-01
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Functional Description Receive Direction Parameter Receive LSP/LSN Output level symmetrical load LSP/LSN Output level symmetrical load 21.5 HOP/HON Output level symmetrical 200- load HOP/HON Output level symmetrical 200- load 21.5 Limit Values 0dBm0 2.23E-00 1.58E-00 6.17 1.41E-01 9.95E-02 21.5 17.83 2.23E-00 1.58E-00 6.17 1.41E-01 9.95E-02 21.5 17.83 max. 3.20E-00 2.26E-00 5.64 9.31 2.02E-01 1.43E-01 18.36 14.69 3.20E-00 2.26E-00 5.64 9.31 2.02E-01 1.43E-01 18.36 14.69 Vrms dBm0 Vrms dBm0 Vrms dBm0 Vrms dBm0 1.18 0.775 1.18 0.775 1.18 0.775 1.18 0.775 Unit Reference
Semiconductor Group
1997-11-01
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Functional Description 2.1.3 Interface Acoustic Transducers
Handset Earpiece
MIN1 MIP1 MIN2 MIP2
Handset Microphone (Electret)
ARCOFI 2161
Loudspeaker
Area
ITS09477
Note: requirements included.
Figure Example Connect Acoustic Transducers
Semiconductor Group 1997-11-01
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Functional Description ARCOFI® Signal Processor (ASP) Description
ARCOFI signal processor (ASP) been conceived perform ITU-T ETSI (NET33) recommended filtering transmit receive paths therefore fully compatible ITU-T G.712 ETSI (NET33) specifications. data processed provided transmit direction oversampling A/D-converter situated analog front (AFE). Once processed, speech signal converted into 8-bit A-law µ-law format remains 16-bit linear word complement) compander bypassed. bypassing companding depends setting configuration register DFICR (VDM-bits). receive direction, incoming stream expanded into linear format linear mode selected, expansion logic bypassed) subsequently processed until passed oversampling D/A-converter. Additionally these standard codec functions, ARCOFI provides universal tone generation unit.
Semiconductor Group
1997-11-01
Semiconductor Group 1997-11-01
Figure Processor Signal Flow Graph
Transmit DTMF DTMFLP DHPX DHPX COMP PCM/LIN kHz)
DTMF
DTMF Tone Generator DTMF Square Trapezoid Sine Interface
Ampl. Square
DHPR DHPR 0.-6 Receive
PCM/LIN kHz)
ITS06382
Functional Description
2161
Piezo-Port
User Programmable
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Functional Description 2.2.1 Transmit Signal Processing
transmit direction series decimation filters reduces sampling rate down 8-kHz PCM-rate. These filters attenuate out-of-band noise limiting transmit signal voice band. decimation stages with EWDF low-pass filter which band limits voice signal ITU-T G.712 ETSI (NET33) recommendations. ARCOFI meets exceeds ITU-T ETSI (NET33) recommendations attenuation distortion group delay distortion. tone generation unit connected transmit direction (TGSR.DTMF special 2-kHz DTMF low-pass filter placed transmit path. This filter guarantees attenuation unwanted frequency components, DTMF signals transmitted. Additionally, possible programmable tone signal transmit voice signal (TGSR.TRX GX-gain adjustment stage digitally programmable allowing gain programmed from steps 0.25 others also possible). bytes necessary desired value. reset, GX-gain stage bypassed. transmit path contains programmable high performance frequency response correction filter allowing optimum adaptation different types microphones (dynamic, piezoelectric electret). Twelve bytes necessary desired frequency correction function. reset, FX-frequency correction filter bypassed. Figure shows architecture FX/FR-filter. high-pass filter (HPX) also provided remove power line frequencies. voice signal, after being linearly processed, output 8-bit PCM-word according ITU-T G.711 A-law North-American µ-law format. desired companding stage bypassed, 16-bit linear word complement) then output IOM-2 interface. 2.2.2 Receive Signal Processing
receive path incoming PCM-signal expanded into linear code according selected A-law µ-law. linear mode chosen, PCM-expander circuit bypassed 16-bit linear word complement) provided processor. block offers several possibilities voice/data manipulation special applications. programmable sidetone gain stage adds sidetone signal incoming voice signal. sidetone gain programmed from within tolerance range others also possible). Respectively bytes coded CRAM desired value. reset, GZ-gain stage disabled dB).
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Functional Description high-pass filter (HPR) also provided remove disturbances from 50/60 telecommunication network. FR-frequency correction response filter similar FX-filter allowing optimum adaptation different types loudspeakers earpieces. Twelve bytes necessary desired frequency correction function. reset, FR-frequency correction filter bypassed. GR-gain adjustment stage digitally programmable from steps 0.25 others also possible). Respectively bytes coded CRAM desired value. reset, GR-gain stage bypassed. low-pass EWDF-filter limits signal bandwidth receive direction according ITU-T ETSI (NET33) recommendations. series low-pass interpolation filters increases sampling frequency desired value.The last interpolator feeds D/A-converter.
Equalizer
Equalizer
High- Low- Pass
ITD02288
Figure Architecture FR-Correction Filter
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Functional Description 2.2.3 Programmable Coefficients
This section gives short overview important programmable coefficients. more detailed information about special applications, special coefficient software package available (ARCOS-SP PLUS SIPO 2163). Description programmable level adjustment parameters: Parameter CRAM Range Bytes Comment
Transmit gain adjustment Transmission characteristics guaranteed Receive gain adjustment Transmission characteristics guaranteed Sidetone gain adjustment
Coefficients Gain [dB] 12.0 11.0 10.0 Gain [dB] 10.0 11.0 Gain [dB] 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0
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Functional Description 2.2.4 Tone Generation
2.2.4.1 Tone Generation Architecture contains universal tone generator which used tone alerting, call progress tones, DTMF signals other audible feedback tones. receive channel, universal switching each signal path (earpiece, loudspeaker piezo ringer) implemented. earpiece loudspeaker direction, addition programmed tone sequence (sine-wave, trapezoid, squarewave DTMF) with incoming voice signal possible. transmit direction, supplementary DTMF generator implemented. DTMF generator active (TGSR.DTMF only part tone generator (TG) available receive direction (one tone sequences). addition, universal switching transmit path also possible (TGSR.TRX). tone generation configurations programmable registers TGCR TGSR (see description chapter signal flow graph ARCOFI tone generation unit shown figure tone generation subdivided into five main blocks: Control Generator (CG) Tone Generator (TG) Tone Filter (TF) Tone Level Adjustment (TLA) DTMF Generator (DTG)
detailed description five main tone generation blocks follows next subsections.
Semiconductor Group
1997-11-01
Control Generator Ampl. Piezo-Pins Receive Path Gain G1,G2,(G3) DTMF Gain (FD) GD1,GD2,(GD3) Tone Level Adjustment TrapezoidGenerator Tone Filter Transmit Path Gain
Tone Generator
Semiconductor Group
SQTR Square-/ TrapezoidGenerator F1,F2,(F3) Equalizer Saturation
ControlGenerator
TON,TOFF
Gain
AutomaticStop
BeatGenerator
T1,T2,(T3)
Note: Adjustments brackets only available DTMF generator switched (TGCR.DTMF Figure Signal Flow Graph Tone Generation Unit
DTMF Gain TrapezoidGenerator
TrapezoidGenerator Gain DTMF Generator
Transmit Path (DTMF)
2161
Functional Description
ITS05609
1997-11-01
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Functional Description 2.2.4.2 Control Generator conjunction with control generator possible generate very complex signal sequences without reprogramming necessary parameters (e.g. pulsed three tone calls). Four typical applications control generator programming shown figure
TOFF TOFF
Fx:Frequency Gx:Gain Tx:Time span *):F2 don't care
TOFF
TOFF TOFF
TOFF
ITD02290
Indicates Intervention
Figure Typical Control Generator Application
Semiconductor Group 1997-11-01
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Functional Description Function table CG/TG-bit setting TGCR: TON/TOFF TOFF Generator Output tone Ringing sequence without break Break between ringing sequences Ringing sequence until next break
Description programmable parameters: Parameter TOFF CRAM Bytes Range Comment Period while tone generator turned Period while tone generator turned
2.2.4.3 Tone Generator tone generator contains beat generator, square/trapezoid generator, second trapezoid generator automatic stop three tone ringing signals. With automatic stop function (SM-bit setting TGCR) multitone generation stopped after sequence completed. This avoids unpleasant sounds when stopping tone generator. control generator activated (TGCR.CG setting insignificant. Otherwise (TGCR.CG TG-bit setting controls activities tone generator. functional diagram tone generator shown figure
Semiconductor Group
1997-11-01
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Functional Description
Beat Generator (T3)
Square/ Trapezoid Generator (F3, Trapezoid Generator
Frequency GDn: Gain Period time (.): available TGSR DTMF Piezo Ringer, DTMF
ITS09478
Tone Filter
Figure Functional Diagram Tone Generator Distinctive alerting signals, allowing example different multitone ringing patterns, programmable using beat tone generator conjunction with square/trapezoid generator. case three tone ringing signals, square/ trapezoid generator controls output frequency pitch whilst beat generator controls repetition rate. Either square trapezoid shaped tones generated depending TGCR.SQTR setting. piezo mode TGSR) chosen, only square-wave available (fixed amplitude VDD). this case SQTR-bit TGCR effect. secondary trapezoid generator also built into ARCOFI. Depending DT-bit setting TGCR, output signal this generator added output signal Square/Trapezoid (S/T) generator. conjunction with generator, wide variety different dual tone signals programmed. beat generator (TGCR.BT enabled, automatic stop function (SM-bit setting TGCR) activated. This prevents uncontrolled turn-off tone generator. Only when generation frequency (depending BM-bit setting TGCR) been completed, tone generator will switch off.
Semiconductor Group
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Functional Description Beat generator programming: Generator Output Continuous signal Continuous signal Continuous signal Continuous signal Alternating signal Alternating signal Alternating signal Alternating signal GD1, GD2, GD1, GD2, GD3,
Description programmable parameters: Parameter CRAM Range Bytes 2/2/2 1/1/1 2/2/2 1/1/1 kHz/m; Comment Trapezoid shaped tone Square-wave signal Gain adjustment square/trapezoid generator Period time three tone sequences Trapezoid shaped tone Gain adjustment trapezoid generator
either
Note: gain setting GD1, corresponds maximum level (A-Law: 3.14 dBm0)
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Functional Description 2.2.4.4 Tone Filter tone filter contains programmable equalizer saturation amplifier (see figure 19). filter function necessary, bypass mode used (TGCR.ETF brief description tone filter follows below. equalizer realized band-pass filter. filter parameters (center frequency, bandwidth, attenuation stopband) programmable. generated square-wave trapezoid signal converted equalizer into sine-wave signal. maximum attenuation first harmonic frequency possible. main purposes programmable saturation amplification are: Level balancing filtered signal (avoidance overload effects). Amplification followed saturation (3.14 dBm0) incoming signal. This saturation amplification converts sine-wave signal into square-wave trapezoid signal where their edges eliminated. This method produces pleasant ringing tones. Description programmable parameters: Parameter CRAM Bytes Range Comment Center frequency Determines with bandwidth. closer comes smaller bandwith. Attenuation stopband Saturation amplification
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1997-11-01
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Functional Description 2.2.4.5 Tone Level Adjustment level adjustment stages determines output levels tone generation (see figure 19). Description programmable parameters: Parameter CRAM Bytes Range Comment
(also (also
Level adjustment output which connected transmit channel Level adjustment output which connected receive channel
2.2.4.6 DTMF Generator (transmit) DTMF generator contains independent trapezoid generators which programmed wide frequency gain range. DTMF generator active (TGSR.DTMF output signal automatically switched transmit direction. this case attenuation unwanted frequency components executed special DTMF low-pass filter following limits: Frequency Band 3400 3400 4000 Min. Attenuation
pre-emphasis between high DTMF frequency groups with independent gain stages trapezoid generators GD3). generated DTMF frequencies guaranteed within deviation.
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Functional Description DTMF-frequency (F3, programming: ITU-T Q.23 Group High Group 1209 1336 1477 1633 ARCOFI® Nominal Relative Deviation Coefficients from ITU-T 697.1 770.3 852.2 941.4 1209.5 1336.9 1477.7 1632.8 high
Note: deviations inaccuracy incoming clock DCL/MCLK, when added nominal deviations tabulated above give total absolute deviation from ITU-T recommended frequencies.
Description programmable parameters: Parameter CRAM Range Bytes Comment Trapezoid shaped tone Gain adjustment trapezoid generator Trapezoid shaped tone Gain adjustment trapezoid generator
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Functional Description ARCOFI® Digital Interface (ADI)
ADI-function consists interface blocks: Peripheral Control Interface (PCI) Serial Control Interface (SCI) IOM-2 interface NON-TE timing mode) Serial Data Interface (SDI) Supplementary functions accessed strapping pins MODE according following table: MODE MCLK MCLK Mode IOM-2 IOM-2 Test IOM-2 IOM-2 Description IOM-2 timing mode IOM-2 timing mode IOM-2 NON-TE timing mode IOM-2 NON-TE timing mode Serial Data Interface
detailed description following chapter. 2.3.1 PCI-Interface
Peripheral Control Interface (PCI) provides programmable pins control peripheral devices (for more detailed information section DFICR). These four interface pins only available IOM-2 terminal mode mode). Otherwise three pins (SB, used slot select pins IOM-2 NON-TE mode used Serial Control Interface (SCI). SA-SD Slot Select 2.3.2 Mode IOM-2 IOM-2 Serial Mode
IOM®-2 Frame Structure Timing Modes
This interface consists data line direction (DD: Data Downstream; Data Upstream). additional signals define data clock (DCL) frame synchronization (FSC). terminal applications, IOM-2 constitutes powerful backplane offering intercommunication sophisticated control capabilities peripheral modules.
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Functional Description channel structure IOM-2 described figure
MONITOR
Figure Channel Structure IOM-2 64-kbit/s channels, conveyed first bytes. third byte (monitor channel) used programming controlling devices attached IOM-2 interface. fourth byte (control channel) contains bits 16-kbit/s D-channel, four command/indication bits controlling activation/deactivation additional control functions, bits supporting handling MONITOR channel. case IOM-2 interface frame structure depends whether NON-TE mode selected. NON-TE Timing Mode frame this mode multiplex eight IOM-2 channels (figure 23), each channel structure shown figure ARCOFI assigned eight channels strapping according following table: Selected IOM-2 Channel
used this mode should connected VSSD. Thus data rate channel kbit/s, whereas rate 2.048 kbit/s. IOM-2 interface signals are: 2048 kbit/s 4096 (double clock rate)
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Functional Description
-CH0
-CH0
MONITOR
ITD06383
Figure Multiplexed Frame Structure IOM®-2 Interface NON-TE Timing Mode
Semiconductor Group
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Functional Description Timing Mode IOM-2 frame provides three complete channels (figure 24): Channel contains kbit/s plus monitor command/indication channels layer-1 device. Channel contains 64-kbit/s intercommunication channels plus monitor command/indication channels other IOM-2 devices (e.g. ARCOFI). Channel used D-channel arbitration. IOM-2 signals are: kbit/s 1536 (double clock rate)
Channel MON0 C/I0
Channel MON1 C/I1
Channel C/I2
MON0 C/I0
MON1
C/I1
C/I2
Bearer voice data channel to/from layer-1 device MON1 Monitor channel C/I1 Command/Indicate channel IC1, Intercommunication channel
ITD09479
MON1 C/I1 IC1,
Bearer voice data channel to/from layer-1 device Monitor channel Command/Indicate channel Intercommunication channel
Figure IOM®-2 Interface Structure Mode
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Functional Description 2.3.3 Serial Control Interface
When MODE tied high AD/MCLK used system clock input (MCLK), internal configuration registers coefficient ARCOFI programmable serial control interface. consists lines: SCLK, SDR, (open drain push-pull) used start serial access ARCOFI registers coefficient RAM. Following falling edge first eight bits transmitted specify command. subsequent one, two, four eight bytes (depending command) read(s) write(s) contents selected registers RAM-locations until line becomes inactive. read command chosen, first byte after command identification code (<IDENT>) ARCOFI-SP 2161 (see also chapter 3.4.2.1). After command sequence completed least NOP-command required (see figure 25). transfer sequence broken setting high. bytes already sent when changes high valid, except last one. data transfer synchronized SCLK input. changes with falling edge SCLK while contents latched rising edge SCLK. Figure shows timing serial control interface transfer (one byte transfer).
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1997-11-01
2161
Functional Description
Write Access
SCLK Command Data
Read Access
SCLK Command Identification Data
ITD05618
Figure Serial Control Interface Timing
Semiconductor Group 1997-11-01
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Functional Description 2.3.4 Serial Data Interface
serial control interface selected, ARCOFI supports additional serial data interface B-channel transfer. This control interface consists five lines: FSC, DCLK, MCLK. 8-kHz frame synchronization signal. DCLK clock signal synchronize data transfer both data lines rising edge indicates start while falling edge used latch contents received data line double clock rate chosen (twice transmission rate) first rising edge indicates start while second falling edge used latch content data line. data rate interface vary from kbit/s 4.096 Mbit/s. frame consist time-slots bits each. last bits TSCR (Time Slot Configuration Register) indicate selected time slot from 16-bit mode (linear mode) chosen, lowest data rate kbit/s time-slot must even number. AD/MCLK system clock synchronized with (necessary synchronize internal PLL). Figure shows timing serial data interface (256 kbit/s with single clock rate).
MCLK
DCLK Data kbit/s
kbit/s
ITD09480
Figure Serial Data Interface Timing
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1997-11-01
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Functional Description Test Functions
ARCOFI provides several test diagnostic functions which grouped follows: programmable configuration registers coefficient RAM-locations readable Digital loop PCM-register (DLP) Digital loop signal processor (DLS) Digital loop noise shaper (DLN) Analog loop analog front (ALF) Analog loop converter (ALC) Analog loop noise shaper (ALN) Analog loop Z-sidetone (ALZ); sidetone gain stage must enabled (PFCR.GZ sidetone gain must programmed with depending VDM-bit setting (DFICR) addition incoming voice signal possible Analog loop digital interface (ALI).
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Operational Description Operational Description Reset
After RESET (hardware reset software reset XOP_E) pins programmed inputs. other output pins high-impedance state (HOP/ HON, LSP/LSN, VREF, PZ1, PZ2, DU/DX).
Note: After Reset (only NON-TE mode) coefficient RAM-locations have defined reset values.
defined reset values ARCOFI-registers listed below: Register CMDR Value after RESET [hex] Meaning operation (NOP) Disable voice transmit IOM-2 channel selected (IOM-2 TE-mode) Power-down mode IOM-2 chip mode (IOM-2 TE-mode) A-Law programmed inputs PCM-mode; receive voice blocked Programmable digital gain disabled Programmable sidetone gain disabled Correction filters disabled 50/60-Hz receive active 50/60-Hz transmit active Tone generator inactive Control generator inactive tone generator connection signal path Microphone amplifier power-down mode Reference voltage buffer power-down mode Pins MIP1/MIN1 directed microphone amplifier Earpiece amplifier power-down mode Loudspeaker amplifier power-down mode Analog test mode disabled Digital test mode disabled Single clock rate (DCLK) enabled configured open drain outputs Master clock rate Time-slot (SDI) selected differential mode locations NON-TE)
DFICR PFCR
TGCR TGSR ATCR
ARCR TFCR SDICR
TSCR CRAM
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Operational Description Initialization
During initialization subset configuration registers coefficient RAM-locations programmed configuration parameters according application desired features. Configuration Registers Register SLOT DFICR PFCR SA-SD DHPR DHPX TGCR SQTR TGSR DTMF
Semiconductor Group
Effect Enable voice transmit IOM-2 slot select Power-up/down mode IOM-2 address mode A-Law/µ-Law PCI-port configuration Voice data manipulation digital gain digital gain Sidetone gain TX-frequency correction filter RX-frequency correction filter Disable high-pass (50/60 receive Disable high-pass (50/60 transmit Tone generator Dual tone mode Enable tone filter Control generator Beat tone generator Beat mode Stop mode Square/trapezoid shaped signal Piezo mode Tone ringing loudspeaker Tone ringing receive direction DTMF-signal transmit direction Tone ringing transmit direction
Restricted IOM-2 IOM-2 IOM-2
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Operational Description Configuration Registers (cont'd) Register ATCR EVREF AIMX ARCR TFCR SDICR ALTF DLTF EPP0 EPP1 TSCR MCLKR DHOP DHON DLSP DLSN Effect Microphone amplifier control Enable reference voltage VREF Analog input multiplexer Handset amplifier control Loudspeaker amplifier control Analog Loops test functions Digital Loops test functions Enable push/pull (DX) Enable push/pull (SDX) Double clock enable Master clock rate Time slot select Disable (tristate) Disable (tristate) Disable (tristate) Disable (tristate) Restricted
Note: Before accessing ARCOFI (IOM-2 mode) interface, GCR-write command (SOP_0 SOP_F) sent.
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Operational Description Coefficient RAM-locations Mnemonic Bytes Effect
COP_0: Tone generator parameter Tone generator frequency Tone generator amplitude Trapezoid generator amplitude Beat tone time used
COP_1: Tone generator parameter tone generator level adjustment Tone generator frequency Tone generator amplitude Trapezoid generator amplitude Beat tone time span Level adjustment receive path Level adjustment transmit path
COP_2: Tone generator parameter Parameter DTMF-generator (TGSR.DTMF Tone generator frequency Tone generator amplitude Trapezoid generator amplitude Beat tone time span Dual tone frequency
COP_3: Tone filter Attenuation stop-band Center frequency Bandwidth Saturation amplification
COP_4: Control generator TOFF Turn-on period tone generator Turn-off period tone generator
COP_5: Receive transmit gain Transmit gain Receive gain used
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Operational Description Coefficient RAM-locations (cont'd) Mnemonic Bytes Effect
COP_6: Sidetone gain Sidetone gain used Transmit correction filter Transmit correction filter coefficients Receive correction filter Receive correction filter coefficients
COP_7/COP_8:
COP_8/COP_9:
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1997-11-01
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Operational Description ARCOFI® Operating Modes
most currently used ARCOFI operating modes documented following table. ARCOFI configuration registers have enough build-in flexibility accommodate extensive user calling procedures. following operating mode description table exhaustive should used example possible functions performed ARCOFI. State Description Power-on reset: when power supplied ARCOFI internal power-on reset generated. addition hardware reset RC-network connected input will force ARCOFI internal registers default values. ARCOFIregisters reset state described section system microprocessor initialize ARCOFI IOM-2 SCI-bus with different filter configuration values. Whilst remaining power-down (GCR.PU filter coefficients configuration bits loaded ARCOFI. system detects activity from hookswitch from keyboard. ARCOFI placed HANDSET state where handset enabled (AMI activated). system detects incoming call, ARCOFI placed RINGING state activating tone ringer TGCR/TGSR configuring ARCOFI such that either LSP/LSN-output piezo output (pins PZ1/PZ2) enabled. emergency ringing also implemented. this mode, only tone ringer loudspeaker amplifier active (AMI- AHO-amplifier disabled user). tone ringer signal directly switched loudspeaker amplifier ALS. audio inputs disabled forcing AMI-amplifier (ATCR) power-down. DTMF tones generated with tone generator output transmit path. Handset audio path enabled forcing HANDSET mode. single tone superimposed into audio receive path provide audible feedback when dialling. handset loudspeaker outputs LSP/LSN active (ATCR ARCR).
STAND
HANDSET
RINGING
DTMF
PULSE DIAL
LOUDHEARING (MONITORING)
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1997-11-01
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Operational Description Operating mode description table (cont'd) State MUTE Description ARCOFI placed MUTE state powering down AMI. handset mode outputs HOP/HON remain enabled while speakerphone mode outputs LSP/LSN enabled. other analog l/O's being disabled. single tone superimposed incoming PCM-voice signal. Applications requiring system function audible feedback therefore made possible.
FEATURE TONE
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1997-11-01
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Operational Description IOM®-2 Interface Protocol
following description IOM-2 interface comprises ARCOFI relevant functions terminal non-terminal mode (see IOM-2 interface specification general information).
Note: Channels only available IOM-2 mode. channel means MON1 channel IOM-2 mode pinstrapping selected channel IOM-2 mode.
3.4.1 IC-Channels (IOM®-2 Mode)
ARCOFI receive transmit voice data IOM-2 B2-channels well intercommunication channels located IOM-2 channels respectively. voice/data channel allocation programmable channel select SLOT GCR-register. respectively programmed RCM-bit CMDR-register. intercommunication channels used terminal local data communication (e.g. answering machine). This makes post-processing voice/data information possible (e.g. data encryption). 3.4.2 Monitor Channel
programming data required ARCOFI including coefficients transmitted exclusively time slot IOM-2 channel. channel allows point multipoint access where layer-2 component acts master program devices like ARCOFI. Each programmable device accessed sending specific address byte start each command stream. Before executing command, programmable device compares received address byte with address. latter consists bits whose MSB-bit must correspond AD-wire (AD/MCLK pin) strapped IOM-2 address. 3.4.2.1 Channel Data Structure data control program ARCOFI transferred channel IOM-2 interface procedure utilizing read/write registers ARCOFI. messages transmitted monitor channel have different kinds data structures. Therefore, first byte message used indicate data structure (first four bits).
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Operational Description Identification Command order able identify unambiguously different devices software, following identification command used: byte value byte value
ARCOFI responds this identification sequence sending identification sequence: byte value byte value logical logical <IDENT>
DESIGN (A-chip) (B-chip) 2160 2165 2163 2161
(active low): (passive high): ARCOFI ARCOFI-SP ARCOFI-SP ARCOFI-BA
DESIGN:six code, specific each device order identify differences operation e.g. 000000 000010 000100 001000
This identification sequence usually done once, when terminal connected first time.This function used that software distinguish between different possible hardware configurations. However this sequence compulsory. Programming Sequence ARCOFI programming sequence characterized being sent nibble first incoming identification code. byte value byte value
CMDx
programmed configurations coefficients read back when issuing appropriate CMDR read (CMDR.R/W ARCOFI responds sending IOM-2 specific address byte identifying chip followed requested data.
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1997-11-01
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Operational Description 3.4.2.2 Transfer Protocol transfer stream commands channel regulated handshake protocol mechanism implemented bits fourth slot IOM-2 channel. procedure follows (figure 27):
Receiver
Transmitter Byte
Byte)
Byte Byte
Byte Acknowledge Byte
Transmission
Byte Acknowledge Byte
Byte Byte
Byte Acknowledge Transmission (EOM)
Transmission
ITD09481
Figure Monitor Channel Handshake Procedure
Semiconductor Group 1997-11-01
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Operational Description Monitor transfer protocol rules: pair inactive state more consecutive frames indicates idle state transmission (EOM). command stream initiated transmitter slot accompanied activated downstream MX-bit. receiver acknowledges received byte toggling upstream MR-bit from inactive active subsequent IOM-2 frame least frame. transmitter indicates byte slot transition MX-bit from active inactive state. MX-bit returns active state after frame. frames with MX-bit inactive state indicate transmission. receiver acknowledges each byte similar frame transition MR-bit inactive state. frames with MR-bit inactive indicate receiver request abort. transmitter delay transmission sequence sending same byte continuously. that case MX-bit remains active IOM-2 frame following first byte occurrence. Delaying transmission sequence only possible while receiver MR-bit transmitter MX-bit active. Since receiver able receive slot data least twice consecutive frames), receiver waits reception successive identical bytes. control this handshake procedure collision detection mechanism implemented transmitter. This done making collision check transmitted data (MD).
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1997-11-01
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Operational Description 3.4.2.3 Implementation MON-Channel Protocol receiver following features: Transparent interface between IOM-2 interface device internal block (sink) with respect handshake procedure, i.e. acknowledge, EOM, abort request abort conveyed transparently through receiver. Figure shows state diagram receiver. following signals used: MR-bit sent receiver MX-bit received Last bytes were identical
Idle
Inital State
Byte
Abort
Byte Valid
Wait
Byte
Byte
Wait
ITD01907
Figure State Diagram Monitor Receiver
Semiconductor Group
1997-11-01
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Operational Description transmitter following features: Transparent interface between IOM-2 interface device internal block (source) with respect handshake procedure, i.e. acknowledge, abort, request abort conveyed transparently through transmitter. Figure shows state diagram transmitter. following signals used: RQT: EOM: MR-bit received MX-bit transmitted Last bytes were identical Request transmission transmission
MR+MX Idle Wait Abort Initial State
.RQT.MX
Byte
.RQT
MR.RQT
Byte
MR.RQT
Wait
MR.RQT
ITD01908
Figure State Diagram Monitor Transmitter
Semiconductor Group 1997-11-01
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Operational Description 3.4.3 Command/Indication Channel Mode)
C/l-channel bits represented that first transmitted/received appears left. data presented four peripheral control interface (PCI) pins transparently routed IOM-2 channel Pins configured individually input output information sent pins coming from them will appear respectively IOM-2 channel case reset been asserted, pins programmed input, however values switched C/I1-channel unless write command (except NOP) issued. mapping peripheral control interface (PCI) pins into C/I1-channel bits depends hardwired address (see section 2.3) follows.
(GCR.CAM chip mode)
(GCR.CAM chip mode)
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1997-11-01
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Operational Description C/I1-Channel (Signaling) Allocation Table DD-C/I1 DU-C/I1 PCI-Configuration after reset pins inputs pins outputs input output input output pins inputs pins outputs inputs outputs inputs outputs pins inputs pins outputs inputs outputs inputs outputs
don't care passive high
Semiconductor Group
1997-11-01
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Operational Description ARCOFI® Voice/Data Manipulation (VDM)
ARCOFI offers several possibilities voice/data manipulation special applications. According manipulation mode chosen, byte IOM-2 mode) output handset channel and/or loudspeaker channel. following tables give overview different voice/data manipulation modes. PCM-Mode Normal Mode (DFICR.VDM 000X): DFICR.VDM 0000 (IOM®-2)
0001
CMDR.RCM (IOM®-2)
GCR.SLOT (IOM®-2)
Receive Channel
Transmit Channel
This table given IOM-2 chip mode (GCR.CAM
Linear Mode (DFICR.VDM 010X): This mode exists only mode programmed following channel) IOM-2 chip mode (GCR.CAM voice/data channels IOM-2 mode) connected 16-bit linear channel complement). DFICR.VDM 0100 0101 (IOM®-2) CMDR.RCM (IOM®-2) GCR.SLOT (IOM®-2) Receive Channel Transmit Channel
B1&B2 (IC1&IC2) means (IC1) byte followed (IC2) byte (totally bits).
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Operational Description Three Party Conferencing Mode (DFICR.VDM 1000): This mode available only mode programmed following channel) IOM-2 chip mode (GCR.CAM DFICR.VDM 1000 (IOM®-2) CMDR.RCM (IOM®-2) GCR.SLOT (IOM®-2) Receive Channel Transmit Channel IC1,
(IC1 IC2) means (IC1) (IC2) byte added together bits). (IC1, IC2) means (IC1) (IC2) byte have same information. Voice Monitoring Mode (DFICR.VDM 1100): This mode available only mode IOM-2 chip mode (GCR.CAM monitoring chip transmission chip must strapped different hardware address (IOM-2: AD/MCLK pin). active DU-voice channel monitoring chip must Hi-Z mode (GCR.EVX PCI-port both chips must compatible configurations avoid collision problems DU-C/I1 channel. DFICR.VDM (IOM®-2) CMDR.RCM (IOM®-2) B1/B2 IC1/IC2 B1D/B2D B1U/B2U IC1D/IC2D IC1U/IC2U GCR.SLOT (IOM®-2) Receive Channel IC1D IC1U IC2D IC2U Transmit Channel (PZ1)
1100
Explanations:
signal voice channels IOM-2 intercommunication channels IOM-2 voice channels (downstream) IOM-2 voice channels (upstream) IOM-2 intercommunication channels (downstream) IOM-2 intercommunication channels (upstream)
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1997-11-01
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Operational Description
VSSD
MODE
VSSD
ARCOFI 2161
VSSD
MODE
ARCOFI 2161
(Strobe)
PZ1(DU +DD)
ITS09482
DCL/DCLK
+DD) Position depending selected voice channel
(Strobe) Note: Digital monitoring requires digital loop TFCR.DLTF DLN) piezo mode must (TGSR
ITD09483
Figure Configuration IOM®-2 Monitoring Mode
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Detailed Register Description Detailed Register Description
following section describes various ARCOFI registers coefficient locations accessible from terminal equipment microcontroller IOM-2 serial controller interface (SCI). summary registers located ADI-block presented below followed detailed description register content. Command Register (CMDR) CMDR CMD5 CMD4 CMD3 CMD2 CMD1 CMD0
General Configuration Register (GCR) SLOT
Data Format Interface Configuration Register (DFICR) DFICR
Programmable Filter Configuration Register (PFCR) PFCR DHPR
DHPX
Tone Generator Configuration Register (TGCR) TGCR
SQTR
Tone Generator Switch Register (TGSR) TGSR DTMF
Transmit Configuration Register (ATCR) ATCR EVREF
AIMX
Semiconductor Group
1997-11-01
2161
Detailed Register Description Receive Configuration Register (ARCR) ARCR
Test Function Configuration Register (TFCR) TFCR ALTF DLTF
Configuration Register (SDICR); only available mode SDICR EPP1 EPP0 MCLKR
Time Slot Configuration Register (TSCR); only available mode TSCR
Extended Configuration Register (XCR) DHOP DHON DLSP
DLSN
Test Mode Register (TMR)
Semiconductor Group
1997-11-01
2161
Detailed Register Description Command Register (CMDR) CMD5 CMD4 CMD3 CMD2 CMD1 CMD0
Value after reset: CMDR
writing configuration registers coefficient reading from configuration registers from coefficient
Reverse Channel Mode receive transmit mode) receive transmit mode) IOM-2 chip mode (GCR.CAM when strapped above applies. When strapped VDD, operates reverse order. Address internal programmable locations code reserved status operation (SOP) coefficient operation (COP) extended operation (XOP)
CMDx
Coding Status Operations (SOP):
Name SOP_0 SOP_1 SOP_2 SOP_3 SOP_4 SOP_5 SOP_6 SOP_7 SOP_8 SOP_9 SOP_A SOP_D SOP_E SOP_F
Status
Seq. Len.
Sequence Description <GCR> <DFICR <PFCR> <TGCR> <TGSR> <ATCR> <ARCR> <TFCR> <SDICR> <TSCR> <XCR> <IDENT>1) <TMR> <TFCR>.<GCR>
3.4.2.1
Semiconductor Group
1997-11-01
2161
Detailed Register Description Coding Coefficient Operations (COP)
Name COP_0 COP_1 Status Seq. Len. Sequence Description <F1> <F1> <G1> <GD1> <T1> <T1> <F2> <F2> <G2> <GD2> <T2> <T2> <GTR> <GTX> <F3> <F3> <G3> <GD3> <T3> <T3> <FD> <FD> <A1> <A2> <GE> <TON> <TON> <TOFF> <TOFF> <GX> <GX> <GR> <GR> <GZ> <GZ> <FX1>.<FX8> <FX9>.<FX12> <FR9>.<FR12> <FR1>.<FR8> Comments
Tone generator Tone generator Additional gain Tone generator Dual tone frequency Tone filter Control generator Transmit gain Receive gain Sidetone gain Correction filter Correction filter
COP_2
COP_3 COP_4 COP_5
COP_6 COP_7 COP_8 COP_9
Coding Extended Operations (XOP)
Name XOP_0 XOP_1 XOP_D XOP_E XOP_F Status Seq. Len. Comments
Power-down mode Power-up mode DD/DU voice channel swap (toggle function) Software reset Normal operation (NOP)
Semiconductor Group
1997-11-01
2161
Detailed Register Description General Configuration Register (GCR) SLOT
Value after reset:
Enable Voice Transmit disable transmit voice data enable transmit voice data GCR.PU idle code transmitted) IOM-2 Slot Select (IOM-2 mode only) bearer channels IOM-channel bearer channels IOM-channel Power-Up ARCOFI placed standby mode (power-down); registers coefficient contents saved interface functions available ARCOFI normal operating mode (power-up) This directly accessed XOP_0/XOP_1 operations. Chip Address Mode (IOM-2 mode only) ARCOFIs connected IOM-2 only ARCOFI connected IOM-2 Coding A-Law enabled µ-Law enabled
SLOT
Semiconductor Group
1997-11-01
2161
Detailed Register Description Data Format Interface Configuration Register (DFICR)
Value after reset: DFICR SD-SA
Signaling (PCI interface; only available IOM-2 mode) programmed output programmed input Voice Data Manipulation Receive Voice Channel Transmit Voice Channel Description
Transmit only Transfer mode 16-bit transmit only 16-bit transfer mode Conferencing mode Monitoring mode
signal Note: this table above voice channels indicated only examples. Other combinations (IC1 IOM-2 mode) possible complete description given section 3.5.
Semiconductor Group
1997-11-01
2161
Detailed Register Description Programmable Filter Configuration Register (PFCR) DHPR DHPX
Value after reset: PFCR
Transmit Gain gain gain coefficients loaded from coefficient (CRAM) Receive Gain gain gain coefficients loaded from CRAM Sidetone Gain gain gain coefficients loaded from CRAM Transmit Frequency Correction Filter filter bypassed filter coefficients loaded from CRAM Receive Frequency Correction Filter filter bypassed filter coefficients loaded from CRAM Disable High-Pass Receive (50/60 filter) filter enabled filter disabled Disable High-Pass Transmit (50/60 filter) filter enabled filter disabled
DHPR
DHPX
Semiconductor Group
1997-11-01
2161
Detailed Register Description Tone Generator Configuration Register (TGCR) SQTR
Value after reset: TGCR
Tone Generator tone generator disabled tone generator enabled; frequency gain coefficients loaded from CRAM; priority over Dual Tone Mode (DTMF) second trapezoid generator disabled second trapezoid generator enabled; output signal added signal generator (only TGSR.DTMF Enable Tone Filter tone filter by-passed tone filter enabled; filter coefficients loaded from CRAM Control Generator control generator disabled control generator enabled; time coefficients loaded from CRAM (tone generator activated independently TG-bit setting) Beat Tone Generator beat tone generator disabled beat tone generator enabled; time coefficients loaded from CRAM Beat Mode beat mode disabled; tone ring activated when BT-generator enabled beat mode enabled; three tone ring activated when BT-generator enabled (only TGSR.DTMF Stop Mode automatic stop mode disabled automatic stop mode enabled; three tone ring gets turned after sequence completed Square/Trapezoid Waveform trapezoid shaped signal enabled (only tone ringing loudspeaker piezo mode disabled: TGSR.TRL TGSR.PM square-wave signal enabled
SQTR
Semiconductor Group
1997-11-01
2161
Detailed Register Description Tone Generator Switch Register (TGSR) DTMF
Value after reset: TGSR
Piezo Mode ringing signal output piezo ring pins ringing signal (square) output piezo ring pins PZ1/PZ2 Tone Ringing Loudspeaker ringing signal output directly loudspeaker pins ringing signal (square) output directly loudspeaker pins LSP/LSN Tone Ringing Receive tone generator receive direction disabled tone generator receive direction enabled DTMF-Generator (transmit) DTMF-generator transmit direction disabled DTMF-generator transmit direction enabled Tone Ringing Transmit tone generator transmit direction disabled tone generator transmit direction enabled Enhanced Reverse Attenuation standard reverse attenuation receive direction enhanced reverse attenuation receive direction
DTMF
Semiconductor Group
1997-11-01
2161
Detailed Register Description Transmit Configuration Register (ATCR) Microphone Control EVREF Selected Mode PREFI power-down mode amplification amplification amplification amplification amplification amplification amplification bypass mode, reserved internal tests EVREF AIMX
Value after reset: ATCR
Enable VREF (2.4-V reference voltage) VREF-buffer enabled function GCR.PU (global power-up) ATCR/ARCR-programming VREF-buffer internal reference voltage generation enabled independently ARCOFI configuration Analog Input Multiplexer Selected Input connected pins MIP1/MIN1 (differential input) connected pins MIP2/MIN2 (differential input) connected (single-ended input) used
AIMX
Semiconductor Group
1997-11-01
2161
Detailed Register Description Receive Configuration Register (ARCR) Handset Output Control Selected Mode power-down mode amplification amplification amplification 15.5 amplification 21.5 amplification bypass mode, reserved internal tests
Value after reset: ARCR
Loudspeaker Output Control Selected Mode power-down mode 11.5 amplification amplification amplification amplification amplification amplification amplification amplification 12.5 amplification 15.5 amplification 18.5 amplification 21.5 amplification bypass mode, reserved internal tests
Semiconductor Group
1997-11-01
2161
Detailed Register Description Test Function Configuration Register (TFCR) ALTF DLTF
Value after reset: TFCR ALTF
Analog Loop Test Functions Test Function NOT: ALF: ALC: ALN: ALI: Test Mode Analog Loop Front Analog Loop Converter Analog Loop Noise Shaper Analog Loop Interface
DLTF
Digital Loop Test Functions Test Function NOT: IDR: DLP: DLS: DLN: Test Mode Initialize DRAM Digital Loop PCM-Register Digital Loop Signal Processor Digital Loop Noise Shaper
Semiconductor Group
1997-11-01
2161
Detailed Register Description 4.10 Configuration Register (SDICR); mode only EPP1 EPP0 MCLKR
Value after reset: SDICR EPP0
Enable Push-Pull DU/DX (SDI mode only) open drain enabled push-pull enabled Enable Push-Pull SDR/SDX (SDI mode only) open drain enabled push-pull enabled Double Clock Enable DCLK (SDI mode only) single clock rate double clock rate Master Clock Rate (synchronized system clock) MCLK Clock Rate 1.536 2.048 4.096 16.384 (test mode)
EPP1
MCLKR
Semiconductor Group
1997-11-01
2161
Detailed Register Description 4.11 Time Slot Configuration Register (TSCR); mode only
Value after reset: TSCR
Time Slot Selection Time Slot
Semiconductor Group
1997-11-01
2161
Detailed Register Description 4.12 Extended Configuration Register (XCR) DHOP DHON DLSP DLSN
Value after reset: DHOP
Disable Amplifier amplifier normal mode Disable amplifier (power-down, output high impedance) Disable Amplifier amplifier normal mode Disable amplifier (power-down, output high impedance) Disable Amplifier amplifier normal mode Disable amplifier (power-down, output high impedance) Disable Amplifier amplifier normal mode Disable amplifier (power-down, output high impedance)
DHON
DLSP
DLSN
Semiconductor Group
1997-11-01
2161
Detailed Register Description 4.13 Test Mode Register (TMR)
Value after reset:
Test Mode (only internal tests) 000: normal mode
Semiconductor Group
1997-11-01
2161
Electrical Characteristics Electrical Characteristics
Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Input/output voltage with respect ground Maximum voltage with respect ground Symbol min. Limit Values max. Unit
TSTG Vmax
ESD-integrity (according MIL-Std 883D, method 3015.7): 1000 exception: pins #14, #16, protected against voltage stress (versus VSSx, output performance prohibits adequate protective structures.
Note: Maximum ratings absolute ratings; exceeding only these values cause irreversible damage integrated circuit.
DC-Characteristics
VDD/VDDP VSSD/VSSA/VSSP
Parameter Input leakage current H-input level (except pins SCLK, MCLK, DCLK) L-input level (except pins SCLK, MCLK,DCLK) H-input level (pins SCLK, MCLK, DCLK) Symbol Limit Values min. typ. max. Unit Test Condition
VIH1
VIL1
VIH2
L-input level (pins SCLK, VIL2 MCLK, DCLK) H-output level (except pins PZ1/PZ2)
0.3VDD
VOH1
Semiconductor Group
1997-11-01
2161
Electrical Characteristics DC-Characteristics (cont'd)
VDD/VDDP VSSD/VSSA/VSSP
Parameter H-output level (pins PZ1/PZ2) L-output level (except L-output level (pin DD1)) Symbol Limit Values min. typ. max. 0.45 0.45 Unit Test Condition
VOH2 VOL1 VOL2
0.45
OFF; reset state
supply current
standby (IOM-2
IDDS1 IDDS2
supply current
operating (IOM-2
IDDO1 IDDO2
emergency ringing (TGSR.TRL handset mode (ARCR.HOC 010B)
Input capacitance Output capacitance
voice channel swap (XOP_D) enabled Operating power dissipation measured with analog outputs open. analog inputs VREF. digital input signal (pin idle code. emergency ringing mode, tone generator 400-Hz single tone (square). this mode loudspeaker amplifier (3.2 Vpp)
Note: listed characteristics ensured over operating range integrated circuit. Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply given supply voltage.
Semiconductor Group
1997-11-01
2161
Electrical Characteristics AC-Characteristics Inputs driven logical 0.45 logical "0". Timing measurements made logical logical "0". AC-testing input/output waveforms shown below.
0.45 Output
Load
ITS05624
Figure Input/Output Waveforms AC-Tests
Semiconductor Group
1997-11-01
2161
Electrical Characteristics Analog Front Input Characteristics Parameter AMI-input impedance AMI-input voltage swing AMI-gain Symbol Limit Values min. max. 38.1 3400 9.55 Unit Test Condition
ZAMI VAMI GAMI
Analog Front Output Characteristics AHO-output impedance AHO-output voltage swing AHO-output high voltage AHO-output voltage ALS-output impedance ALS-output voltage swing ALS-output high voltage ALS-output voltage
ZAHO VAHO VAHO VAHOL ZALS VALS VALSH VALSL ZVREF VVREF
2.35
3.08 3.08 2.45
3400 Load measured from input load HOP/HON input load HOP/HON 3400 Load measured from input load LSP/LSN input load LSP/LSN Load measured from VREF VSSA input load VREF
VREF output impedance VREF output voltage
maximum output voltage swing corresponds maximum incoming PCM-code 127)
Semiconductor Group
1997-11-01
2161
Electrical Characteristics Transmission Characteristics VDD/VDDP VSSD/VSSA/VSSP Parameter Attenuation Distortion dBm0 Limit Values min. 0.25 0.25 0.25 0.25 max. dBm0 dBm0 2400 2400 3000 3000 3400 3400 receive (TGSR.ERA=0): receive(TGSR.ERA=1): transmit: TGSR.ERA=0 1000 1000 2600 2600 2800 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 receive (A-Law; Psoph.) transmit (A-Law; Psoph.) Reference: dBm0 Unit Test Condition
0.25 0.45
Out-of-band signals Group delay distortion dBm0
Signal-to-total distortion (method sinewave 1kHz) Gain tracking (method dBm0 Idle-channel noise Cross-talk
Semiconductor Group
1997-11-01
2161
Electrical Characteristics Transmission Characteristics (cont'd) VDD/VDDP VSSD/VSSA/VSSP Parameter Programmable gain Overall programming range (With specified transmission characteristics) Limit Values min. 21.5 21.5
Unit
Test Condition step accuracy overall accuracy Receive: loudspeaker earpiece Transmit: differential inputs single ended input
max. 11.5
Delay measurements include delays through with features filters disabled.
Semiconductor Group
1997-11-01
2161
Electrical Characteristics IOM®-2 Switching Characteristics
FSCs
FSCh
(Data OUT) Frame
(Data
ITD05625
Figure IOM®-2 Timing Diagram
Parameter DCL-clock period DCL-clock period DCL-duty cycle FSC-period FSC-setup time FSC-hold time DD-data-in setup time DD-data-in hold time DU-data-out delay
Symbol min.
Limit Values typ. max.
Unit
tDCL tDCL tFSC tFSCs tFSCh tIDs tIDh tODd
kbit/s (IOM-2 Mode); max. jitter once FSC-period. 2048 kbit/s (IOM-2 Non-TE Mode).
Semiconductor Group
1997-11-01
2161
Electrical Characteristics PCI-Switching Characteristics (IOM®-2 TE-Mode)
(Data
Last C/I1
PCId
(Data OUT)
Last MON1
PCIs
PCIh
ITD05626
Figure IOM®-2 Timing Diagram (TE-Mode)
Parameter PCI-data-out delay PCI-data-in setup time PCI-data-in hold time
Symbol
Limit Values min. max.
Unit
tPCld tPCls tPClh
Semiconductor Group
1997-11-01
2161
Electrical Characteristics SCI-Switching Characteristics
SDRh
SCLK
SDRs
Tristate
SDXd
SDXt
ITD05627
Figure SCI-Switching Timing Diagram
Parameter SCLK-frequency Chip Select setup time Chip Select hold time SDR-setup time SDR-hold time SDX-data-out delay high tristate
Symbol
Limit Values min. max. 2048
Unit
fSCLK tCSs tCSh tSDRs tSDRh tSDXd tSDXt
Semiconductor Group
1997-11-01
2161
Electrical Characteristics SDI-Switching Characteristics
MCLK
FSCh
DCLK
FSCw
FSCd
DXd1
ITD05628
Figure SDI-Switching Timing Diagram
Parameter MCLK-frequency DCLK-frequency FSC-pulse width FSC-hold time from DCLK FSC-delay time DR-setup time DR-hold time DX-data-out delay (tFSCd DX-data-out delay (tFSCd DX-data-out delay
Symbol
Limit Values min. max. 4096 4096
Unit
fMCLK fDCLK tFSCw tFSCh tFSCd tDRs tDRh tDXd1 tDXd1 tDXd
tFSCd
Semiconductor Group
1997-11-01
2161
Package Outlines Package Outlines
P-DSO-28-1 (Plastic Dual Small Outline Package)
2.65
0.35
+0.09
2.45 -0.2
-0.1
1.27 0.35 +0.15
+0.8 10.3 ±0.3
Index Marking
18.1 -0.4
Does include plastic metal protrusions 0.15 side Does include dambar protrusion 0.05 side
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information" Surface Mounted Device Semiconductor Group
0.23
GPS05123
Dimensions 1997-11-01
-0.2
Audio Ringing Codec Filter ARCOFI®-BA 2161 Layout Wiring Recommendations
Application Note 06.96
2161 Revision History: Previous Version: Page Page previous current Version) Version)
Current Version: 1996-06-01
Subjects (major changes since last revision)
Edition 1996-06-01 This edition realized using software system FrameMaker®. Published Siemens Bereich Halbleiter, MarketingKommunikation, 81541 Siemens 1996. Rights Reserved. Attention please! patents other rights third parties concerned, liability only assumed components, applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. questions technology, delivery prices please contact Semiconductor Group Offices Germany Siemens Companies Representatives worldwide (see address list). technical requirements components contain dangerous substances. information types question please contact your nearest Siemens Office, Semiconductor Group. Siemens approved CECC manufacturer. Packing Please recycling operators known you. also help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred. Components used life-support devices systems must expressly authorized such purpose! Critical components1 Semiconductor Group Siemens only used life-support devices systems2 with express written approval Semiconductor Group Siemens critical component component used life-support device system whose failure reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain human life. they fail, reasonable assume that health user endangered.
2161
Table Contents 7.3.1 7.3.2 7.3.3
Page
Application Note Layout Wiring Recommendations .106 Introduction .106 Layout Considerations .107 Connecting Analog Front .108 Outputs Earpiece Loudspeaker .108 Differential Microphone Inputs .109 Single Ended Input .113
Semiconductor Group
1996-06-01
Audio Ringing Codec Filter ARCOFI®-BA
2161
Application Note Layout Wiring Recommendations Introduction
ARCOFI-BA 2161 high performance codec filter device with high gain analog amplifiers. obtain full performance device, some care designing analog circuitry printed circuit board taken. This application note gives some hints wants provide understanding parameters that influence performance. With "performance", especially following effects meant: Signal noise ratio, especially transmit direction (analog digital) Idle channel noise (the noise that present when there signal applied) Spurious oscillations Sensitivity kind interfering signals (noise power supply, interference, induced voltages etc.)
ARCOFI-BA contains high performance converters with more than resolution order allow different signal processing steps without degradation signals themselves. silicon 2161 integrates high gain, analog preamplifier, oversampling converters well digital signal processor. Besides ARCOFI-BA used digital environment that typically causes noise power supply produces many kinds interfering signals. these reasons, careful grounding, decoupling, shielding best system performance.
Note: circuits given this application note general guidance claim satisfy user specific requirements. Especially reasons additional components required.
Semiconductor Group
1996-06-01
2161
Application Note Layout Wiring Recommendations Layout Considerations
Decoupling Power Supply Pins 2161 three ground pins pins connecting positive supply voltage. Internally ground pins power supply pins connected. From table seen, what parts ARCOFI-BA supplied from what pins. important, that each pair pins given table decoupled with pair capacitors parallel. capacitor ceramic one, second tantalum type with recommended. Table Power Supply Pins 2161 (VSSD) (VSSP) (VSSA) (VDD) (VDDP) (VDD) Supply Digital signal processor digital interface Analog output amplifier AHO, Analog preamplifiers switches
Note, that (VDD) used both, supply supply analog part ARCOFI-BA except power amplifiers ALS. Blocking Reference Voltage reference voltage VREF 2161 blocked with capacitor least 100nF analog ground. Therefore this capacitor required between (VREF) (VSSA). placed close these pins. Grounding second aspect designing good layout well defined ground connection. This concerns three ground pins ARCOFI-BA (pin 20). These three ground pins have connected each other either directly ground plane underneath 2161 separate wires that lead central ground point system. latter case care must taken that three single ground wires carry only current ARCOFI-BA itself. ground connection e.g. low-level microphone signals should made directly VSSA which serves ground microphone preamplifier. general, kind ground loop must avoided since this would antenna noise. Note also position decoupling capacitor reference voltage between figure 38b. should placed close
Semiconductor Group
1996-06-01
2161
Application Note Layout Wiring Recommendations 7.3.1 Connecting Analog Front Outputs Earpiece Loudspeaker
analog handset output amplifier delivers symmetrical signal pins HON. load with impedance higher than connected directly (see figure 36a). However, load shows strong capacitive behavior like piezoceramic earpiece, better series resistors shown figure avoid spurious oscillations. This also typical example circuitry used real application. resistors have placed close output pins.
Handset Earpiece Handset Earpiece
ITS09484
Figure Analog Handset Output possible outputs single ended outputs with reference ground; load must greater than only half amplitude swing available.
Loudspeaker
ITS09485
Figure Analog Loudspeaker Output main difference between earpiece output loudspeaker output driver capability. load between pins order drive speaker. dynamic speaker connected directly these pins (see figure 37a). arrangement unsymmetrical connection with speakers shows figure 37b. load should decoupled avoid currents through speakers. With register bits XCR.DLSP XCR.DLSN each output switched into high impedance state therefore speakers switched independently. same applies earpiece output with HON. This feature offers variety applications. example, speaker figure left out, output becomes switchable line level output. example, this output could control external speaker box.
Semiconductor Group 1996-06-01
2161
Application Note Layout Wiring Recommendations 7.3.2 Differential Microphone Inputs
ARCOFI-BA offers five pins microphone inputs. differential inputs MIN1/MIP1 MIN2/MIP2 equivalent terms performance circuitry. single ended input offers slightly reduced performance unsymmetrical structure. inputs used interface directly with kinds microphones serve high level input. Unused microphone inputs left open tied VREF.
(MIP
(MIP
MIN1 (MIN
MIN1 (MIN
VREF
ITS09486
Figure Interfacing Symmetrical Microphones symmetric signal source that reference ground simply connected differential inputs. Basically, additional components required (figure 38a). microphone dynamic, magnetic, piezoelectric one. Usually arrangement similar shown figure will used order well defined impedances EMC/ESD protection. component values depend type microphone used. microphone inputs biased internally with VREF require external biasing. However, path helpful order avoid static charging input pins while they unused (not active). Therefore resistors figure introduced. input impedance single pins MIN, MIP, higher than Electret Microphones Today, electret microphones widely used telecommunications devices. These microphones usually contain active amplifier achieve output impedance therefore require some biasing. current bias electret microphone taken from positive supply voltage ARCOFI-BA reference voltage VREF used this purpose (2.4 schematic figure depicts first possibility.
Semiconductor Group 1996-06-01
2161
Application Note Layout Wiring Recommendations
VREF
MIN1
MIP1
ITS09487
Figure Interfacing Electret Microphones with Bias from input (MIN1) differential input tied VREF. This creates single ended configuration which must coupled with signal source, consisting electret microphone. used bias microphone. combination R2/C2 filters power supply ripple. value recommended microphone manufacturer usually range dashed line figure illustrates connect second microphone other differential input ARCOFI-BA without spending complete bias network again. second possibility bias electret microphones shown figure current taken directly from VREF ARCOFI-BA. network filter power noise necessary because reference voltage clean stable. Only case high gains analog microphone amplifier (AMI more than overall performance improved, reference voltage filtered. this purpose, combination k/10 between VREF resistors figure inserted. application incorporating this element shows figure
Semiconductor Group
1996-06-01
2161
Application Note Layout Wiring Recommendations
MIN1
MIP1
ITS09488
Figure Interfacing Electret Microphones with Bias from VREF solutions connecting microphones shown figure contain minimum components explain principle. solution that comes closer real application seen figure microphone biased from VREF pin.
VREF
MIN1
MIP1
ITS09489
Figure Example Typical Application With help R3/C3 well defined input impedance achieved. inserted, high frequency cut-off realized. k/10 combination used filter reference voltage (improved idle channel noise with dB).
Semiconductor Group 1996-06-01
2161
Application Note Layout Wiring Recommendations Especially electret microphone connected longer cable high noise immunity desired, circuity from figure suitable. microphone directly connected ground with feeding resistors
VREF
MIN1 (MIN
(MIP
ITS09490
Figure Symmetrical Biasing Electret Microphone
Semiconductor Group
1996-06-01
2161
Application Note Layout Wiring Recommendations 7.3.3 Single Ended Input
single ended input behaves like differential input pins, case input differential inputs tied VREF. Therefore application examples figure introduces ideas. electret microphone biased from (figure 43a) from VREF (figure 43b). symmetric signal source with reference ground should connected between VREF (figure 43c). Often used additional input e.g. separate microphones with their preamplifiers. Such high-level signal sources could connected shown figure 43d. general, only inputs required, advisable MIN1/MIP1 MIN2/MIP2 this purpose. They exhibit slightly better performance because their differential nature. When input source referred ground, gain input should exceed
VREF
VREF
External Input
ITS09491
Figure Using Single Ended Input
Semiconductor Group
1996-06-01
ARCOFI® Telephone Board SIPB 5132-SP Version
Board Description 05.96
SIPB 5132-SP Revision History: Previous Version: Page Page previous current Version) Version)
Current Version: 1996-05-01
Subjects (major changes since last revision)
Edition 1996-05-01 This edition realized using software system FrameMaker®. Published Siemens Bereich Halbleiter, MarketingKommunikation, 81541 Siemens 1996. Rights Reserved. Attention please! patents other rights third parties concerned, liability only assumed components, applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. questions technology, delivery prices please contact Semiconductor Group Offices Germany Siemens Companies Representatives worldwide (see address list). technical requirements components contain dangerous substances. information types question please contact your nearest Siemens Office, Semiconductor Group. Siemens approved CECC manufacturer. Packing Please recycling operators known you. also help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred. Components used life-support devices systems must expressly authorized such purpose! Critical components1 Semiconductor Group Siemens only used life-support devices systems2 with express written approval Semiconductor Group Siemens critical component component used life-support device system whose failure reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain human life. they fail, reasonable assume that health user endangered.
SIPB 5132-SP
Table Contents 8.2.1 8.2.2 8.4.1 8.4.2
Page
ARCOFI® Telephone Board SIPB 5132-SP Board Description .117 Introduction .117 Hardware Configuration .118 Floor Plan Switches .118 Connectors .120 Hardware Environment .122 Trackfiles .124 Trackfile IOM®-2 Mode .124 Trackfiles IOM®-2 NON-TE Mode .127 Circuit Diagram .135
Semiconductor Group
1996-05-01
ARCOFI® Telephone Board
SIPB 5132-SP
Version ARCOFI® Telephone Board SIPB 5132-SP Board Description Introduction
ARCOFI Telephone Board SIPB 5132-SP evaluation board ARCOFI-SP 2163 ARCOFI-BA 2161. conjunction with acoustic (optional) handset used simple IOM-2 telephone. Handset handsfree operation fully supported keypad entering dialling information available. evaluation measurement purposes analog outputs pins 2161/PSB 2163 directly accessible. Customer specific analog circuitry easily connected. SIPB 5132-SP board configured IOM-2 NON-TE mode (1.536 4.096 data clock). Upon delivery board equipped with 2163 DIP-28 package. Since 2163 compatible with 2161 applications 2161 evaluated with 2163 well. only difference between chips lack speakerphone support with 2161. desired, 2161 soldered DSO-28 footprint inside DIP-28 socket.
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description 8.2.1 Hardware Configuration Floor Plan Switches
Figure shows floor plan with connectors different jumpers. Please refer also schematic board SICOFI-2. ARCOFI-SP offers test mode which indicates internal speakerphone states ("transmit", "receive", "idle") with help LEDs connected piezo ringer output pins. SIPB 5132-SP board these pins switched piezo ringer pair LEDs with Power supply taken directly from IOM-2 connector from separate connector ST2. This selected complete circuitry analog front connected through jumpers ST5. Therefore each analog in-/output ARCOFI accessible corresponding jumper removed; please refer schematic details. reset ARCOFI active high. board pull-up resistor connected reset pin. reset switch normally closed requires reset line IOM-2 connector held connected hardware. customer specific hardware used together with SIPB 5132-SP board must ensured that during normal operation this reset line level.
Piezo Ringer Piezo 2161/63 "Transmit" Power Supply
Handset Acoustic
LED's "Idle"
Active Speaker
Power from
Power from
Mode
Reset
ITS09492
Figure Floor Plan with Connectors
Semiconductor Group 1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description switches DIP-switch used select address interface mode ARCOFI. other four switches applying high low-level signals pins ARCOFI. They therefore used test interface (general interface) ARCOFI IOM-2-TE mode select active channel IOM-2-NON-TE mode used (refer ARCOFI User's Manual, e.g. 2163, User's Manual 06.96, page 65). Table Mode Address setting with Switch Switch Switch Switch IOM-2 (1.536 MHz) A-Chip IOM-2 NON-TE (4.096 MHz) B-Chip
Table Purpose Switch Switch Switch Switch Switch Switch Low-level Low-level Low-level Low-level High-level High-level High-level High-level
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description 8.2.2 Connectors
Connector
ITS09493
Figure IOM® Connector Connector Signal
Reset
ITS09494
Figure External Power Supply
Semiconductor Group
Signal
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description Connector
1234
ITS09495
Figure Handset Connector
Connector
Signal MIP2
123456
ITS09496
Figure Speakerphone Connector
Signal MIP1
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description Hardware Environment
Figure shows typical example hardware setup based SIPB 5000 mainboard with ISAC-S (TE) ISAC-P (TE) transceiver chip. ARCOFI telephone board SIPB 5132-SP connected flat-band cable IOM-2 connector that leads Audio Interface Module SIPB 5130. interface mode used IOM-2-TE mode. Programming performed with ARCOS software package SIPB menu-software which comes with SIPB 5000 board. terminals figure linked Mini-Switch SIPB 8100 complete ISDN voice connection simulated (without D-channel protocol).
Mainboard SIPB 5000 Q67100 H8647 SIPB 5130 67100 H8657
SIPB 5100 Q67100 H8657
Mode
SIPB 5130 Q67100 H8657
SIPB 5103 67100 H6024
Mode
SIPB 5132 V2.0 67100 H6299
Acoustic 67100 H6446
123456
ITS09497
Figure Terminal Configuration with SIPB 5000 Mainboard
Semiconductor Group 1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description IOM-2 NON-TE mode configuration figure used. Again programming done either with ARCOS software menu software. PCM4 adapter optional. more flexible setup PCM4 measurements made with PERCOFI-Board STUT 2000.
SIPB 5132 V2.0 ARCOFI Telephone Q67100 H6299 SIPB 5121 Q67100 H8656 SIPB 5130 67100 H8657
654321
Mode
SIPB 5311 PCM4 Adapter
Mainboard SIPB 5000 67100 H8647
ITS09498
Figure Setup NON-TE Mode
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description 8.4.1 Trackfiles Trackfile IOM®-2 Mode
following trackfile used with setup shown figure written 2163 used with 2161 well.
Trackfile HS_S0.TE PROGRAMMING ARCOFI-SP 2163 IOM2 HANDSET MODE additionally ACTIVATING INTERFACE COSY MUST BEFORE -ISAC-S IOM2 mode -/S02TE/ISAC_S/SERIAL/ADF2 /S02TE/ISAC_S/SERIAL/SPCR /S02TE/ISAC_S/HDLC/STAR /S02TE/ISAC_S/HDLC/STAR /S02TE/ISAC_S/HDLC/STAR -Activation interface -/S02TE/ISAC_S/SERIAL/CIX0 /S02TE/ISAC_S/SERIAL/CIR0 /S02TE/ISAC_S/SERIAL/CIR0 /S02TE/ISAC_S/SERIAL/SPCR /S02TE/ISAC_S/SERIAL/SPCR -IOM2 Identification ARCOFI-SP -/S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR -Programming ARCOFI-SP
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description
HANDSET mode -/S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR -COP_6: GZ=-15dB -/S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR -Powering ARCOFI-SP -/S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR -Read SOP_F -/S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOX1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOCR
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description
/S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOR1 /S02TE/ISAC_S/SERIAL/MOSR /S02TE/ISAC_S/SERIAL/MOCR /S02TE/ISAC_S/SERIAL/MOSR
Trackfile
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description 8.4.2 Trackfiles IOM®-2 NON-TE Mode
trackfiles this chapter used with hardware shown figure Before ARCOFI accessed EPIC Linecard Module initialized first. This task first trackfile LC_1.IOM. This trackfile originally written SICOFI chip used with ARCOFIs well.
LC_1.IOM application: initialization line card module SICOFI2 measurement tool setup: line card module sipb 5121 iom2 channel assignement: ch0: analog subscriber (sicofi2) ch1: analog subscriber (sicofi2) ch2: analog subscriber (sicofi2) ch3: analog subscriber (sicofi2) ch4: analog subscriber (sicofi2) ch5: analog subscriber (sicofi2) ch6: analog subscriber (sicofi2) ch7: analog subscriber (sicofi2) interface characteristics: interface: with each interface: with each iom2 interfaces) configuration module: config register bits: clock mode (xtal 4096khz) reset board devices /LINECA/CONFIG/CONFIG/CONFIG /LINECA/CONFIG/CONFIG/CONFIG configuration mode /LINECA/EPIC/PCMCFI/PMOD /LINECA/EPIC/PCMCFI/PCSR /LINECA/EPIC/PCMCFI/POFD /LINECA/EPIC/PCMCFI/POFU interface:
configuration interface: mode clock source: pcl/pfs evaluated with falling edge prescaler /LINECA/EPIC/PCMCFI/CMD1 output: mode output: double rate xmit rising, falling edge /LINECA/EPIC/PCMCFI/CMD2 number /LINECA/EPIC/PCMCFI/CBNR
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description
marks ts31,bit1 /LINECA/EPIC/PCMCFI/CTAR shift between xmit /LINECA/EPIC/PCMCFI/CBSR subchannel position:64kbps=bits7.0 32kbps=bits7.4 16kbps=bits7.6 /LINECA/EPIC/PCMCFI/CSCR initialization ctrl field: reset mode /LINECA/EPIC/MARSCR/OMDR copied positions ctrl field /LINECA/EPIC/MARSCR/MADR /LINECA/EPIC/MARSCR/MACR configuration iom2: init mode /LINECA/EPIC/MARSCR/OMDR timeslots port programmed monitor signaling channels (analog iom) downstream: /LINECA/EPIC/MARSCR/MADR /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR downstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR timeslots port programmed monitor signaling channels (analog iom) downstream: /LINECA/EPIC/MARSCR/MADR /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR downstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR timeslots port programmed monitor signaling channels (analog iom) downstream:
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description
/LINECA/EPIC/MARSCR/MADR /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR downstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR timeslots port programmed monitor signaling channels (analog iom) downstream: /LINECA/EPIC/MARSCR/MADR /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR downstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR timeslots port programmed monitor signaling channels (analog iom) downstream: /LINECA/EPIC/MARSCR/MADR /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR downstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR timeslots port programmed monitor signaling channels (analog iom) downstream: /LINECA/EPIC/MARSCR/MADR /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR downstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description
/LINECA/EPIC/MARSCR/MACR timeslots port programmed monitor signaling channels (analog iom) downstream: /LINECA/EPIC/MARSCR/MADR /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR downstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR timeslots port programmed monitor signaling channels (analog iom) downstream: /LINECA/EPIC/MARSCR/MADR /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR downstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR upstream: /LINECA/EPIC/MARSCR/MAAR /LINECA/EPIC/MARSCR/MACR status /LINECA/EPIC/MARSCR/STAR synchronized (pss=0) setting epic normal mode /LINECA/EPIC/MARSCR/OMDR /LINECA/EPIC/MARSCR/ISTA /LINECA/EPIC/MARSCR/STAR status: synchronized (pss=1) initialization tristate field, high impedance /LINECA/EPIC/MARSCR/MADR /LINECA/EPIC/MARSCR/MACR activation epic: normal mode, active output drivers push-pull handshake protocol enabled /LINECA/EPIC/MARSCR/OMDR reset cififo: /LINECA/EPIC/MARSCR/CMDR
line card ready
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description
SICOFI2 measurements with PCM4 from Wandel Goltermann your trackfile with filter coefficients trackfile
After initializing EPIC LineCard module file HS_LC.TE used ARCOFI handset mode.
Track File HS_LC.TE Programming ARCOFI-SP 2163 IOM-2 NON-TE Handset Mode Trackfile LC_1.IOM before Configuration: LineCard SIPB 5121 Audio Module SIPB 5130 DIP-Switch Connecting LineCard Audio Interface Module /LINECA/CONFIG/CONFIG/CONFIG Selecting timeslot (depends pins SB,SC,SD) Here: slot (all pins VCC) MFSAR slot MFSAR slot MFSAR slot MFSAR slot MFSAR slot
Semiconductor Group
1996-05-01
SIPB 5132-SP
ARCOFI® Telephone Board SIPB 5132-SP Board Description
MFSAR slot MFSAR slot MFSAR slot /LINECA/EPIC/MCHSTR/MFSAR ARCOFI-SP Identification /LINECA/EPIC/MCHSTR/CMDR /LINECA/EPIC/MCHSTR/MFFIFO /LINECA/EPIC/MCHSTR/MFFIFO /LINECA/EPIC/MCHSTR/CMDR /LINECA/EPIC/MCHSTR/ISTA /LINECA/EPIC/MCHSTR/STAR /LINECA/EPIC/MCHSTR/MFFIFO /LINECA/EPIC/MCHSTR/STAR /LINECA/EPIC/MCHSTR/MFFIFO /LINECA/EPIC/MCHSTR/CMDR COP_6: GZ=-15dB /LINECA/EPIC/MCHST
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