PCnetTM- Home Single-Chip 1/10 Mbps Home Networking Controller DI
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Am79C978
PCnetTM- Home Single-Chip 1/10 Mbps Home Networking Controller
DISTINCTIVE CHARACTERISTICS
Fully integrated Mbps HomePNA Physical Layer (PHY) defined Home Phoneline Networking Alliance (HomePNA) specification Optimized home networking applications over ordinary telephone wire In-band control features: Adjustable power speed levels bits reserved in-band messaging piggybacked Ethernet packet Register programmable features: Power control Performance registers Speed control Major frame timing parameters programmable: ISBI, ISBI, pulse width, inter-symbol time Fully integrated Mbps interface Comprehensive Auto-Negotiation implementation Full-duplex capability Optimized 10BASE-T applications Integrated Fast Ethernet controller Peripheral Component Interconnect (PCI) 32-bit glueless host interface Supports clock frequency from independent network clock Supports network operation with clock from High performance mastering architecture with integrated Direct Memory Access (DMA) Buffer Management Unit utilization draft specification revision compliant Supports Subsystem/Subvendor Vendor programming through EEPROM interface Supports both 5.0-V 3.3-V signaling environments Plug Play compatible Supports unlimited burst length endian little endian byte alignments supported Implements optional power management event (PME) Dual-speed CSMA/CD Mbps Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 Ethernet standard Media Independent Interface (MII) connecting external 10/100 Mbps transceivers IEEE 802.3u compliant Intelligent Auto-Pollexternal status monitor interrupt Supports both auto-negotiable nonauto-negotiable external PHYs Supports 10BASE-T, 100BASETX/FX, 100BASET4, 100BASET2 IEEE 802.3 compliant PHYs full-duplex halfduplex Full-duplex operation supported port with independent Transmit (TX) Receive (RX) channels Supports PC98 specifications Implements full OnNow features including pattern matching link status wake-up events Implements Magic Packetmode Magic Packet mode physical address loaded from EEPROM power without requiring clock Supports Power Management Interface specification revision Supports Advanced Configuration Power Interface (ACPI) specification version Supports Network Device Class Power Management specification version 1.0a
Publication# 22206 Rev: Amendment/0 Issue Date: November 1999
AMD'
Independent internal FIFOs
Programmable FIFO watermarks both operations frame queuing high latency host operation Programmable allocation buffer space between queues
allowing protocol analysis begin before receive frame
Includes Programmable Inter Packet (IPG) address less network aggressive controllers Offers Modified Back-Off algorithm address Ethernet Capture Effect IEEE 1149.1-compliant JTAG Boundary Scan test access port interface NAND tree test mode board-level production connectivity test Software compatible with AMD's PCnetFamily LANCE/C-LANCE register descriptor architecture Very power consumption +3.3 power supply along with tolerant I/Os enable broad system compatibility Available 144-pin TQFP 160-pin PQFP packages
Extensive programmable internal/external loopback capabilities EEPROM interface supports jumperless design provides through-chip programming
Supports full programmability half-/fullduplex operation through EEPROM mapping Programmable reset output capable resetting external without need buffering
Extensive programmable status support Look-Ahead Packet Processing (LAPP) data handling technique reduces system overhead
GENERAL DESCRIPTION
Am79C978 controller first series home networking products from AMD. Am79C978 controller fabricated advanced power CMOS process provide operating current power sensitive applications. Am79C978 controller contains Ethernet Controller based Am79C971 Fast Ethernet controller, physical layer device supporting 802.3 standard 10BASE-T, physical layer device data networking speeds Mbps over ordinary residential telephone wiring. integrated Ethernet controller highly integrated 32-bit full-duplex, 10/100 Mbps Ethernet controller solution designed address high-performance system application requirements. flexible busmastering device that used application, including network ready PCs. master architecture provides high data throughput system utilization. integrated Ethernet transceiver physical layer device supporting IEEE 802.3 standards 10BASE-T. provides layer functions required support Mbps data transfer speeds. integrated HomePNA transceiver physical layer device that enables data networking speeds Mbps over common residential phone wiring regardless topology without disrupting telephone (POTS) service. 32-bit multiplexed interface unit provides direct interface local bus, simplifying design Ethernet home network node system. device built-in support both little endian byte alignment. integrated home networking controller's advanced CMOS design allows interface connected either +5.0 +3.3 signaling environment. compliant IEEE 1149.1 JTAG test interface board level testing also provided, well NAND tree test structure those systems that support JTAG interface. integrated Am79C978 home networking controller also compliant with PC98 specifications. includes full implementation Microsoft OnNow ACPI specifications, which backward compatible with Magic Packet technology. also compliant with Power Management Interface specification supporting four power management states (D0, D3), optional pin, necessary configuration data registers. integrated Am79C978 home networking controller complete Ethernet home network node integrated into single VLSI device. contains interface unit, Direct Memory Access (DMA) Buffer Management Unit, ISO/IEC 88023 (IEEE 802.3) compliant Media Access Controller (MAC), Transmit FIFO large Receive FIFO, IEEE 802.3u compliant MII. Both IEEE 802.3 compliant full-duplex half-duplex operations supported interface. 10/100 Mbps operation supported through interface. integrated Am79C978 home networking controller register compatible with LANCE (Am7990) C-LANCE (Am79C90) Ethernet controllers
Am79C978
Ethernet controllers PCnet Family (except ILACC(Am79C900)), including PCnet-ISA (Am79C960), PCnet-ISA+ (Am79C961), PCnet-ISA (Am79C961A), PCnet-32 (Am79C965A), PCnet-PCI (Am79C970), PCnet-PCI (Am79C970A), PCnetFAST (Am79C971), PCnet-FAST+ (Am79C972). Buffer Management Unit supports LANCE PCnet descriptor software models. While consuming minimal network resources, AMD's innovative any1HomeLink Detection Packet HomePNA networks provides means indicate thus upper layers system protocol that valid network defined Home Networking Alliance) been detected. Link Detection Packet also capable detecting network failure allows upper layer protocol take cor-
rective action. Thus, Link Detection Packet ensure strict compliance Microsoft PC97, PC98, Home requirements. integrated Am79C978 controller supports autoconfiguration configuration space. Additional integrated controller configuration parameters, including unique IEEE physical address, read from external non-volatile memory (EEPROM) immediately following system reset. addition, Am79C978 controller provides programmable on-chip drivers transmit, receive, collision, link integrity, Magic Packet status, speed, activity, power output, address match, full-duplex, Mbps status.
Am79C978
BLOCK DIAGRAM
XTAL1
XTAL2
RXD(3:0)/TXD(3:0)
Clock Reference
MDIO
1Mbps HomePNA
Interface
Transmit State Machine
Drive Control HRTXRXP/N
AD[31:0] C/BE[3:0] FRAME TRDY IRDY STOP IDSEL DEVSEL PERR SERR INTA
Management
Receive State Machine
Analog Front
Control
Link Monitor
FIFO Interface Unit
FIFO
802.3 Core Interface
Mbps
SRAM
Transmit State Machine BASE-T
FIFO
FIFO
MDIO Management
Receive State Machine
FIFO Control
Network Port Manager
Link Monitor
Auto Negotiation
Buffer Management Unit Control
Control
LED0 LED1 LED2 LED3 LED4 EECS EESK EEDI EEDO
JTAG Port Control
OnNow Power Management Unit
93C46 EEPROM Interface
22206B-1
Am79C978
TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION. BLOCK DIAGRAM. RELATED PRODUCTS. CONNECTION DIAGRAM (144 TQFP) CONNECTION DIAGRAM (160 PQFP) DESIGNATIONS (PQL144) Listed Number DESIGNATIONS (PQR160) Listed Number DESIGNATIONS (PQL144) Listed Group DESIGNATIONS (PQR160) Listed Group Listed Driver Type. ORDERING INFORMATION Standard Products DESCRIPTIONS Interface Magic Packet Interface Board Interface EEPROM Interface Interface IEEE 1149.1 (1990) Test Access Port Interface Ethernet Network Interfaces HomePNA Network Interface Clock Interface Power Supply. BASIC FUNCTIONS. System Interface. Software Interface Network Interfaces Media Independent Interface Transmit Interface Receive Interface Network Status Interface Management Interface Management Frames. Auto-Poll External Status Polling. Network Port Manager 10BASE-T JTAG Configuration Information. Slave Interface Unit Slave Configuration Transfers Slave Transfers Expansion Transfers. Slave Cycle Termination Disconnect When Busy Disconnect Burst Transfer. Parity Error Response Master Interface Unit Acquisition Master Transfers Basic Non-Burst Read Transfer Basic Burst Read Transfer Basic Non-Burst Write Transfer Basic Burst Write Transfer Target Initiated Termination Disconnect With Data Transfer
Am79C978
Disconnect Without Data Transfer Target Abort Master Initiated Termination Preemption During Non-Burst Transaction Preemption During Burst Transaction Master Abort Parity Error Response Advanced Parity Error Handling Initialization Block Transfers Descriptor Transfers FIFO Transfers Non-Burst FIFO Transfers Burst FIFO Transfers. Buffer Management Unit Initialization Re-Initialization Suspend. Buffer Management Descriptor Rings Polling Transmit Descriptor Table Entry Receive Descriptor Table Entry Receive Frame Queuing Software Interrupt Timer 10/100 Media Access Controller Transmit Receive Message Data Encapsulation Framing Destination Address Handling Error Detection Media Access Management. Medium Allocation Collision Handling. Transmit Operation Transmit Function Programming Automatic Generation. Transmit Generation Transmit Exception Conditions Loss Carrier Late Collision Test Error Receive Operation Receive Function Programming. Address Matching Automatic Stripping Receive Checking Receive Exception Conditions Loopback Operation. Miscellaneous Loopback Features Full-Duplex Operation Full-Duplex Link Status Support PHY/MAC Interface DETAILED FUNCTIONS Mbps HomePNA PHY. HomePNA Medium Interface. Framing HomePNA Symbol Waveform Time Interval Unit. ACCESS Intervals Symbol (SYNC interval) SYNC Transmit Timing.
Am79C978
SYNC Receive Timing. Symbols through Transmit Timing Receive Timing. Collisions. Signal ACCESS Values. Silence Interval (AID symbol Data Symbols Data Transmit Timing Data Receive Timing. Data Symbol RLL25 Encoding Management Interfaces Header Remote Control Word Commands Control Management Block (PCM Block) Register Administration 10BASE-T Device Description Methodology SRAM Configuration Latency Receive Configuration Direct SRAM Access. EEPROM Interface Automatic EEPROM Read Operation EEPROM Auto-Detection Direct Access Interface EEPROM-Programmable Registers EEPROM Support Power Savings Mode Power Management Support OnNow Wake-Up Sequence Link Change Detect OnNow Pattern Match Mode Pattern Match (PMR) Magic Packet Mode. IEEE 1149.1 (1990) Test Access Port Interface Boundary Scan Circuit Finite State Machine Supported Instructions Instruction Register Decoding Logic Boundary Scan Register Other Data Registers NAND Tree Testing Reset. H_RESET S_RESET STOP Power Reset. Software Access Configuration Registers Resources Registers Address PROM Space Reset Register. Word Mode Double Word Mode 10BASE-T Physical Layer. Twisted Pair Transmit Function. Twisted Pair Receive Function Twisted Pair Interface Status Collision Detect Function
Am79C978
Jabber Function Reverse Polarity Detect Auto-Negotiation Soft Reset Function .100 USER ACCESSIBLE REGISTERS .101 Configuration Registers .102 Vendor Register .102 Device Register .102 Command Register .103 Status Register .104 Revision Register .105 Programming Interface Register .105 Sub-Class Register .105 Base-Class Register .106 Latency Timer Register. .106 Header Type Register. .106 Base Address Register .106 Memory Mapped Base Address Register .107 Subsystem Vendor Register. .107 Subsystem Register .107 Expansion Base Address Register .108 Capabilities Pointer Register. .108 Interrupt Line Register .108 Interrupt Register .109 MIN_GNT Register .109 MAX_LAT Register .109 Capability Identifier Register .109 Next Item Pointer Register .109 Power Management Capabilities Register (PMC) .109 Power Management Control/Status Register (PMCSR) .110 PMCSR Bridge Support Extensions Register .111 Data Register .111 Register RAP: Register Address Port .112 Control Status Registers (CSRs) CSR0: Controller Status Control Register. .112 CSR1: Initialization Block Address .115 CSR2: Initialization Block Address .115 CSR3: Interrupt Masks Deferral Control .115 CSR4: Test Features Control .118 CSR5: Extended Control Interrupt .119 CSR6: RX/TX Descriptor Table Length .122 CSR7: Extended Control Interrupt .122 CSR8: Logical Address Filter .125 CSR9: Logical Address Filter .125 CSR10: Logical Address Filter .125 CSR11: Logical Address Filter .126 CSR12: Physical Address Register .126 CSR13: Physical Address Register .126 CSR14: Physical Address Register .126 CSR15: Mode .127 CSR16: Initialization Block Address Lower .128 CSR17: Initialization Block Address Upper .128 CSR18: Current Receive Buffer Address Lower .128 CSR19: Current Receive Buffer Address Upper .128 CSR20: Current Transmit Buffer Address Lower. .129 CSR21: Current Transmit Buffer Address Upper. .129 CSR22: Next Receive Buffer Address Lower .129 CSR23: Next Receive Buffer Address Upper .129 CSR24: Base Address Receive Ring Lower .129
Am79C978
CSR25: Base Address Receive Ring Upper .129 CSR26: Next Receive Descriptor Address Lower .129 CSR27: Next Receive Descriptor Address Upper .130 CSR28: Current Receive Descriptor Address Lower .130 CSR29: Current Receive Descriptor Address Upper .130 CSR30: Base Address Transmit Ring Lower. .130 CSR31: Base Address Transmit Ring Upper. .130 CSR32: Next Transmit Descriptor Address Lower. .130 CSR33: Next Transmit Descriptor Address Upper. .130 CSR34: Current Transmit Descriptor Address Lower .131 CSR35: Current Transmit Descriptor Address Upper .131 CSR36: Next Next Receive Descriptor Address Lower .131 CSR37: Next Next Receive Descriptor Address Upper .131 CSR38: Next Next Transmit Descriptor Address Lower .131 CSR39: Next Next Transmit Descriptor Address Upper .131 CSR40: Current Receive Byte Count. .131 CSR41: Current Receive Status .132 CSR42: Current Transmit Byte Count .132 CSR43: Current Transmit Status .132 CSR44: Next Receive Byte Count .132 CSR45: Next Receive Status. .132 CSR46: Transmit Poll Time Counter .132 CSR47: Transmit Polling Interval. .133 CSR48: Receive Poll Time Counter. .133 CSR49: Receive Polling Interval .133 CSR58: Software Style .134 CSR60: Previous Transmit Descriptor Address Lower .136 CSR61: Previous Transmit Descriptor Address Upper .136 CSR62: Previous Transmit Byte Count .136 CSR63: Previous Transmit Status .136 CSR64: Next Transmit Buffer Address Lower .136 CSR65: Next Transmit Buffer Address Upper .136 CSR66: Next Transmit Byte Count .136 CSR67: Next Transmit Status .137 CSR72: Receive Ring Counter .137 CSR74: Transmit Ring Counter .137 CSR76: Receive Ring Length .137 CSR78: Transmit Ring Length .137 CSR80: Transfer Counter FIFO Threshold Control .138 CSR82: Transmit Descriptor Address Pointer Lower. .140 CSR84: Address Register Lower .140 CSR85: Address Register Upper .140 CSR86: Buffer Byte Counter .140 CSR88: Chip Register Lower .141 CSR89: Chip Register Upper .141 CSR92: Ring Length Conversion. .141 CSR100: Timeout .141 CSR112: Missed Frame Count .142 CSR114: Receive Collision Count .142 CSR116: OnNow Power Mode Register .142 CSR122: Advanced Feature Control .143 CSR124: Test Register .143 CSR125: Enhanced Configuration Control .144 Configuration Registers (BCRs) .145 BCR0: Master Mode Read Active .145 BCR1: Master Mode Write Active .145 BCR2: Miscellaneous Configuration .145 BCR4: LED0 Status .147 BCR5: LED1 Status .149 BCR6: LED2 Status .151
Am79C978
BCR7: LED3 Status .153 BCR9: Full-Duplex Control. .155 BCR16: Base Address Lower .155 BCR17: Base Address Upper .155 BCR18: Burst Control Register .156 BCR19: EEPROM Control Status .158 BCR20: Software Style .161 BCR22: Latency Register .163 BCR23: Subsystem Vendor Register .163 BCR24: Subsystem Register .164 BCR25: SRAM Size Register. .164 BCR26: SRAM Boundary Register .164 BCR27: SRAM Interface Control Register .165 BCR28: Expansion Port Address Lower (Used Flash/EPROM SRAM Accesses) .166 BCR29: Expansion Port Address Upper (Used Flash/EPROM Accesses). .167 BCR30: Expansion Data Port Register. .167 BCR31: Software Timer Register. .168 BCR32: Control Status Register. .168 BCR33: Address Register .170 BCR34: Management Data Register .171 BCR35: Vendor Register .171 BCR36: Power Management Capabilities (PMC) Alias Register .172 BCR37: DATA Register (DATA0) Alias Register .172 BCR38: DATA Register (DATA1) Alias Register .172 BCR39: DATA Register (DATA2) Alias Register .172 BCR40: DATA Register (DATA3) Alias Register .173 BCR41: DATA Register (DATA4) Alias Register .173 BCR42: DATA Register (DATA5) Alias Register .174 BCR43: DATA Register (DATA6) Alias Register .174 BCR44: DATA Register (DATA7) Alias Register .174 BCR45: OnNow Pattern Matching Register .175 BCR46: OnNow Pattern Matching Register .175 BCR47: OnNow Pattern Matching Register .176 BCR48: LED4 Status .176 BCR49: Select .178 BCR50-BCR55: Reserved Locations. .178 Mbps HomePNA Internal Registers HPR0: HomePNA Control (Register .179 HPR1: HomePNA Status (Register HPR2 HPR3: HomePNA (Registers .181 HPR4-HPR7: HomePNA Auto-Negotiation (Registers .181 Reserved Registers: HPR8 HPR15 .181 HPR16: HomePNA Control (Register HPR17: HomePNA Status Control (Register 17). HPR18 HPR19: HomePNA TxCOMM (Registers .183 HPR20 HPR21: HomePNA RxCOMM (Registers HPR22: HomePNA (Register .184 HPR23: HomePNA Noise Control (Register .184 HPR24: HomePNA Noise Control (Register .185 HPR25: HomePNA Noise Statistics (Register 25). .185 HPR26: HomePNA Event Status (Register 26). HPR27: HomePNA Event Status (Register 27). .186 HPR28: HomePNA ISBI Control (Register .186 HPR29: HomePNA Control (Register .187 HPR30: Mbps HomePNA Drive Level Control Test Register (Register .187 HPR31: Mbps HomePNA Analog Control Register (Register .187 10BASE-T Management Registers (TBRs) TBR0: 10BASE-T Control Register (Register .189 TBR1: 10BASE-T Status Register (Register TBR2 TBR3: 10BASE-T Identifier (Registers
Am79C978
TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register .192 TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register .193 TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register .194 Reserved Registers (Registers 8-15, 20-23, 25-31) .194 TBR16: 10BASE-T INTERRUPT Status Enable Register (Register 16). TBR17: 10BASE-T Control/Status Register (Register TBR19: 10BASE-T Management Extension Register (Register Reserved Register: 10BASE-T Configuration Register (Register .197 Reserved Register: 10BASE-T Carrier Status Register (Register 23). .197 TBR24: 10BASE-T Summary Status Register (Register .197 Initialization Block RLEN TLEN .198 RDRA TDRA .199 LADRF .199 PADR .199 Mode .199 Receive Descriptors. .200 RMD0. .201 RMD1. .201 RMD2. .202 RMD3. .203 Transmit Descriptors .203 TMD0 .204 TMD1 .204 TMD2 .205 TMD3 .206 REGISTER SUMMARY .207 Configuration Registers .207 Control Status Registers .208 Configuration Registers .212 10BASE-T Management Registers .213 Mbps HomePNA Management Registers. .214 REGISTER PROGRAMMING SUMMARY. .215 Am79C978 Programmable Registers .215 ABSOLUTE MAXIMUM RATINGS .220 OPERATING RANGES .220 CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED .220 SWITCHING CHARACTERISTICS: INTERFACE .222 10BASE-T Mode .224 Power Supply Current .224 External Clock (XTAL) Timing Specifications. .225 External Clock (Oscillator) Timing Specification .225 Interface .225 PECL .225 10BASE-T .227 SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE .228 SWITCHING WAVEFORMS .229 Switching Waveforms .229 SWITCHING TEST CIRCUITS .229 SWITCHING WAVEFORMS: SYSTEM INTERFACE .230 SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE .234 PHYSICAL DIMENSIONS .236 PQL144 .236 PQR160 .237 APPENDIX ALTERNATIVE METHOD INITIALIZATION APPENDIX LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT INDEX INDEX-1
Am79C978
LIST FIGURES
Figure Media Independent Interface Figure Frame Format Interface Connection. Figure Slave Configuration Read. Figure Slave Configuration Write Figure Slave Read Using Command Figure Slave Write Using Memory Command Figure Expansion Read Figure Disconnect Slave Cycle When Busy. Figure Disconnect Slave Burst Transfer Host Wait States Figure Disconnect Slave Burst Transfer Host Inserts Wait States. Figure Address Parity Error Response Figure Slave Cycle Data Parity Error Response Figure Acquisition Figure Non-Burst Read Transfer Figure Burst Read Transfer (EXTREQ MEMCMD Figure Non-Burst Write Transfer Figure Burst Write Transfer (EXTREQ Figure Disconnect With Data Transfer Figure Disconnect Without Data Transfer Figure Target Abort Figure Preemption During Non-Burst Transaction Figure Preemption During Burst Transaction. Figure Master Abort Figure Master Cycle Data Parity Error Response Figure Initialization Block Read Non-Burst Mode Figure Initialization Block Read Burst Mode Figure Descriptor Ring Read Non-Burst Mode Figure Descriptor Ring Read Burst Mode Figure Descriptor Ring Write Non-Burst Mode Figure Descriptor Ring Write Burst Mode Figure FIFO Burst Write Start Unaligned Buffer. Figure FIFO Burst Write Unaligned Buffer Figure 16-Bit Software Model Figure 32-Bit Software Model Figure 8802-3 (IEEE/ANSI 802.3) Data Frame Figure IEEE 802.3 Frame Length Field Transmission Order Figure HomePNA Framing Figure Symbol Transmit Timing Figure Symbol Receive Timing Figure Transmit Data Symbol Timing. Figure Receive Symbol Timing Figure Coding Tree Figure Block Diagram SRAM Configuration Figure Block Diagram Latency Receive Configuration. Figure Control Logic. Figure OnNow Functional Diagram Figure Pattern Match Figure NAND Tree Circuitry (160 PQFP) Figure NAND Tree Waveform Figure 10BASE-T Transmit Receive Data Paths Figure Address Match Logic Figure Clock Timing Figure Interface Timing (PECL) .225 Figure Mbps Transmit (TX±) Timing Diagram. .226 Figure Mbps Receive (RX±) Timing Diagram .226 Figure Normal Tri-State Outputs Figure Waveform Signaling Figure Waveform Signaling
Am79C978
Figure Input Setup Hold Timing Figure Output Valid Delay Timing Figure Output Tri-State Delay Timing Figure EEPROM Read Functional Timing Figure Automatic PREAD EEPROM Timing Figure JTAG (IEEE 1149.1) Waveform Signaling. Figure JTAG (IEEE 1149.1) Test Signal Timing Figure Transmit Timing Figure Receive Timing Figure Waveform Figure Management Data Setup Hold Timing. Figure Management Data Output Valid Delay Timing Figure B-1. LAPP Timeline. Figure B-2. LAPP Buffer Grouping Figure B-3. LAPP Timeline Two-Interrupt Method Figure B-4. LAPP Buffer Grouping Two-interrupt Method B-10
LIST TABLES Table Interrupt Flags Table External Clock/Crystal Select Table Device Table Software Configuration Table Slave Commands Table Slave Configuration Transfers Table Master Commands Table Descriptor Read Sequence Table Descriptor Write Sequence Table Receive Address Match Table HomePNA Pulse Parameters. Table Access Symbol Pulse Positions Encoding Table Blanking Interval Speed Settings Table Master Station Control Word Functions Table Control Frame Format Table EEPROM Table Default Configuration Table IEEE 1149.1 Supported Instruction Summary Table Mode Operation Table Device Register Table NAND Tree Sequence (160 PQFP) Table NAND Tree Sequence (144 TQFP) Table Configuration Space Layout Table Word Mode (DWIO Table Legal Accesses Word Mode (DWIO Table DWord Mode (DWIO Table Legal Accesses Double Word Mode (DWIO =1). Table Auto-Negotiation Capabilities Table Loopback Configuration Table Software Styles Table Receive Watermark Programming Table Transmit Start Point Programming Table Transmit Watermark Programming Table Registers Table ROMTNG Programming Values Table Select Programming Table EEDET Setting Table Interface Assignment Table Software Styles Table SRAM_BND Programming. Table EBCS Values Table CLK_FAC Values
Am79C978
Table FMDC Values Table APDW Values Table HPR0: HomePNA Control (Register Table HPR1: HomePNA Status (Register Table HPR2 HPR3: HomePNA (Registers Table HPR4-HPR7: HomePNA Auto-Negotiation (Registers Table HPR16: HomePNA Control (Register Table HPR17: HomePNA Status Control (Register Table HPR18 HPR19: HomePNA TxCOMM (Registers 19). Table HPR20 HPR21: HomePNA RxCOMM (Registers Table HPR22: HomePNA (Register Table HPR23: HomePNA Noise Control (Register Table HPR24: HomePNA Noise Control (Register 24). Table HPR25: HomePNA Noise Statistics (Register Table HPR26: HomePNA Event Status (Register Table HPR27: HomePNA Event Status (Register Table HPR8: HomePNA ISBI Control (Register Table HPR29: HomePNA Control (Register Table HPR30: HomePNA Drive Level Control Test Register (Register Table HPR31: HomePNA Analog Control Register (Register Table Am79C978 10BASE-T Management Register Table TBR0: 10BASE-T Control Register (Register Table TBR1: 10BASE-T Status Register (Register Table TBR2: 10BASE-T Identifier (Register Table TBR3: 10BASE-T Identifier (Register Table TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register Table TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register Base Page Format Table TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register Next Page Format Table TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register Table TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register Table TBR16: 10BASE-T INTERRUPT Status Enable Register (Register Table TBR17: 10BASE-T Control/Status Register (Register 17). Table TBR19: 10BASE-T Management Extension Register (Register Table TBR24: 10BASE-T Summary Status Register (Register Table Initialization Block (SSIZE32 Table Initialization Block (SSIZE32 Table R/TLEN Decoding (SSIZE32 Table R/TLEN Decoding (SSIZE32 Table Receive Descriptor (SWSTYLE Table Receive Descriptor (SWSTYLE Table Receive Descriptor (SWSTYLE Table Transmit Descriptor (SWSTYLE Table Transmit Descriptor (SWSTYLE Table Transmit Descriptor (SWSTYLE Table Configuration Registers. Table Control Status Registers (CSRs). Table Configuration Registers (BCRs) Table 10BASE-T Management Registers (TBRs) Table Mbps HomePNA Management Registers (HPRs) Table Control Status Registers Table Configuration Registers. Table A-1. Registers Alternative Initialization Method (Note
Am79C978
RELATED PRODUCTS
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Integrated Controllers Am79C930 Am79C940B Am79C961A Am79C965A Am79C970A Am79C971 Am79C972 PCnetTM-Mobile Single Chip Wireless Media Access Controller Media Access Controller Ethernet (MACETM) PCnet-ISA Full Duplex Single-Chip Ethernet Controller PCnet-32 Single-Chip 32-Bit Ethernet Controller Buses PCnet-PCI Full Duplex Single-Chip Ethernet Controller Local PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller Local PCnet-FAST+ Enhanced 10/100 Mbps Ethernet Controller with OnNow Support
Manchester Encoder/Decoder Am7992B Serial Interface Adapter (SIA)
Physical Layer Devices (Single-Port) Am7996 Am79761 Am79C98 Am79C100 Am79C873 IEEE 802.3/Ethernet/Cheapernet Transceiver (TAP) Physical Layer 10-Bit Transceiver Gigabit Ethernet (GigaPHYTM-SD) Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) 10/100 Mbps Ethernet Physical Layer Transceiver (NetPHYTM-1)
Physical Layer Devices (Multi-Port) Am79C871 Am79C988B Am79C989 Quad Fast Ethernet Transceiver 100BASE-X Repeaters (QFEXrTM) Quad Integrated Ethernet Transceiver (QuIETTM) Quad Ethernet Switching Transceiver (QuESTTM)
Integrated Repeater/Hub Devices Am79C981 Am79C982 Am79C983A Am79C984A Am79C985 Am79C987 Integrated Multiport Repeater Plus (IMR+) Basic Integrated Multiport Repeater (bIMR) Integrated Multiport Repeater (IMR2TM) Enhanced Integrated Multiport Repeater (eIMRTM) Enhanced Integrated Multiport Repeater Plus (eIMR+TM) Hardware Implemented Management Information Base (HIMIBTM)
Am79C978
CONNECTION DIAGRAM (144 TQFP)
IDSEL AD23 VSSB AD22 VDD_PCI AD21 AD20 AD19 AD18 VSSB AD17 VDD_PCI AD16 C/BE2 FRAME IRDY VSSB TRDY VDD_PCI DEVSEL STOP PERR SERR VSSB VDD_PCI C/BE1 AD15 AD14 AD13 VSSB AD12
C/BE3 AD24 AD25 VSSB AD26 VDD_PCI AD27 AD28 AD29 AD30 VSSB AD31 VDD_PCI PCI_CLK INTA VSSB VDDB EECS VSSB EESK/LED1 LED2 VDDB EEDI/LED0 EEDO/LED3
Am79C978
RXDVDDRX DVSSX TXDVDDTX DVDDD IREF DVSSD DVSSA DVDDA PHY_RST DVDDA_HR VSSB VDDB HRTRXP VDDHR HRTRXN VSSHR VDDCO XTAL1 XTAL2 XCLK/XTAL LED4 MDIO VSSB RXD3 RXD2 VDDB RXD1 RXD0
AD11 VDD_PCI AD10 C/BE0 VSSB VDD_PCI VSSB VDD_PCI VSSB TXD3 TXD2 TXD1 VDDB TXD0 TX_EN TX_CLK VSSB RX_ER RX_CLK RX_DV
22206B-2
Am79C978
CONNECTION DIAGRAM (160 PQFP)
IDSEL AD23 VSSB AD22 VDD_PCI AD21 AD20 AD19 AD18 VSSB AD17 VDD_PCI AD16 C/BE2 FRAME IRDY VSSB TRDY VDD_PCI DEVSEL STOP PERR SERR VSSB VDD_PCI C/BE1 AD15 AD14 AD13 VSSB AD12
C/BE3 AD24 AD25 VSSB AD26 VDD_PCI AD27 AD28 AD29 AD30 VSSB AD31 VDD_PCI PCI_CLK INTA VSSB VDDB EECS VSSB EESK/LED1 LED2 VDDB EEDI/LED0 EEDO/LED3
Am79C978
RXDVDDRX DVSSX TXDVDDTX DVDDD IREF DVSSD DVSSA DVDDA PHY_RST DVDDA_HR VSSB VDDB HRTRXP VDDHR HRTRXN VSSHR VDDCO XTAL1 XTAL2 XCLK/XTAL LED4 MDIO VSSB RXD3 RXD2 VDDB RXD1 RXD0
AD11 VDD_PCI AD10 C/BE0 VSSB VDD_PCI VSSB VDD_PCI VSSB TXD3 TXD2 TXD1 VDDB TXD0 TX_EN TX_CLK VSSB RX_ER RX_CLK RX_DV
22206B-3
Am79C978
DESIGNATIONS (PQL144) Listed Number
Name IDSEL AD23 VSSB AD22 VDD_PCI AD21 AD20 AD19 AD18 VSSB AD17 VDD_PCI AD16 C/BE2 FRAME IRDY VSSB TRDY VDD_PCI DEVSEL STOP PERR SERR VSSB VDD_PCI C/BE1 AD15 AD14 AD13 VSSB AD12 Name AD11 VDD_PCI AD10 C/BE0 VSSB VDD_PCI VSSB VDD_PCI VSSB TXD3 TXD2 TXD1 VDDB TXD0 TX_EN TX_CLK VSSB RX_ER RX_CLK RX_DV Name RXD0 RXD1 VDDB RXD2 RXD3 VSSB MDIO LED4 XCLK/XTAL XTAL2 XTAL1 VDDCO VSSHR HRTRXN VDDHR HRTRXP VDDB VSSB DVDDA_HR PHY_RST DVDDA DVSSA DVSSD IREF DVDDD DVDDTX TXDVSSX DVDDRX RXPin Name EEDO/LED3 EEDI/LED0 VDDB LED2 EESK/LED1 VSSB EECS VDDB VSSB INTA PCI_CLK VDD_PCI AD31 VSSB AD30 AD29 AD28 AD27 VDD_PCI AD26 VSSB AD25 AD24 C/BE3
Am79C978
DESIGNATIONS (PQR160) Listed Number
Name IDSEL AD23 VSSB AD22 VDD_PCI AD21 AD20 AD19 AD18 VSSB AD17 VDD_PCI AD16 C/BE2 FRAME IRDY VSSB TRDY VDD_PCI DEVSEL STOP PERR SERR VSSB VDD_PCI C/BE1 AD15 AD14 AD13 VSSB AD12 Name AD11 VDD_PCI AD10 C/BE0 VSSB VDD_PCI VSSB VDD_PCI VSSB TXD3 TXD2 TXD1 VDDB TXD0 TX_EN TX_CLK VSSB RX_ER RX_CLK RX_DV Name RXD0 RXD1 VDDB RXD2 RXD3 VSSB MDIO LED4 XCLK/XTAL XTAL2 XTAL1 VDDCO VSSHR HRTRXN VDDHR HRTRXP VDDB VSSB DVDDA_HR PHY_RST DVDDA DVSSA DVSSD IREF DVDDD DVDDTX TXDVSSX DVDDRX RXPin Name EEDO/LED3 EEDI/LED0 VDDB LED2 EESK/LED1 VSSB EECS VDDB VSSB INTA PCI_CLK VDD_PCI AD31 VSSB AD30 AD29 AD28 AD27 VDD_PCI AD26 VSSB AD25 AD24 C/BE3
Am79C978
DESIGNATIONS (PQL144) Listed Group
Pins
Name HomePNA Network Ports HRTXRXP/N XTAL1 XTAL2 XCLK/XTAL IREF PHY_RST TX_CLK TXD[3:0] TX_EN RX_CLK RXD[3:0] RX_ER RX_DV MDIO Magic Packet Host Interface PCI_CLK C/BE[3:0] AD[31:0] DEVSEL FRAME IDSEL INTA IRDY PERR SERR Clock Transmit Clock Transmit Data Transmit Enable Receive Clock Receive Data Receive Error
Function Receive/Transmit Data Crystal Input XTAL/60 CLK) Crystal Output XTAL) Oscillator/Crystal Select Serial Transmit Data Serial Receive Data Tied resistor Buffered signal
Type
Voltage 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5
Driver XTAL OMII1 OMII1 OMII1 OMII2 TSMII STS6 STS6 STS6 STS6 STS6
10BASE-T Network Ports
Receive Data Valid Management Data Clock Management Data Carrier Sense Collision Power Management Event Power Good
Command Byte Enable Address/Data Device Select Cycle Frame Grant Initialization Device Select Interrupt Initiator Ready Parity Parity Error Request Reset System Error
Am79C978
Name STOP TRDY EECS EEDI/LED0 EESK/LED1 LED2 EEDO/LED3 LED4 TCLK Power/Ground DVDDTX DVDDRX VDD_PCI VDDB VDDHR DVDDA DVDDD VDDCO DVDDA_HR DVSSD DVSSA DVSSX VSSB VSSHR Stop Target Ready Chip Select Data In/LED0 Serial Clock/LED1 LED2 Data Out/LED3 LED4 Test Clock Test Mode Select Test Data Test Data
Function
Type
Voltage 3.3/5 3.3/5
Driver STS6 STS6
Pins
EEPROM/LED Interface
Test Access Port Interface (JTAG)
Transceiver Digital Power Transceiver Digital Power Digital power Digital power Digital power Digital power HomePNA Transceiver Analog Power Transceiver Digital Power Crystal Oscillator Power Transceiver Analog Power Transceiver Digital Ground Transceiver Analog Ground Transceiver Ground Digital Ground Digital Ground HomePNA Analog Ground
Am79C978
DESIGNATIONS (PQR160) Listed Group
Pins
Name HomePNA Network Ports HRTXRXP/N XTAL1 XTAL2 XCLK/XTAL IREF PHY_RST TX_CLK TXD[3:0] TX_EN RX_CLK RXD[3:0] RX_ER RX_DV MDIO Magic Packet Host Interface PCI_CLK C/BE[3:0] AD[31:0] DEVSEL FRAME IDSEL INTA IRDY PERR SERR Clock Transmit Clock Transmit Data Transmit Enable Receive Clock Receive Data Receive Error
Function Receive/Transmit Data Crystal Input XTAL/60 CLK) Crystal Output XTAL) Oscillator/Crystal Select Serial Transmit Data Serial Receive Data Tied resistor Buffered signal
Type
Voltage 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5
Driver XTAL OMII1 OMII1 OMII1 OMII2 TSMII STS6 STS6 STS6 STS6 STS6
10BASE-T Network Ports
Receive Data Valid Management Data Clock Management Data Carrier Sense Collision Power Management Event Power Good
Command Byte Enable Address/Data Device Select Cycle Frame Grant Initialization Device Select Interrupt Initiator Ready Parity Parity Error Request Reset System Error
Am79C978
Name STOP TRDY EECS EEDI/LED0 EESK/LED1 LED2 EEDO/LED3 LED4 TCLK Power/Ground DVDDTX DVDDRX VDD_PCI VDDB VDDHR DVDDA DVDDD VDDCO DVDDA_HR DVSSD DVSSA DVSSX VSSB VSSHR Stop Target Ready Chip Select Data In/LED0 Serial Clock/LED1 LED2 Data Out/LED3 LED4 Test Clock Test Mode Select Test Data Test Data
Function
Type
Voltage 3.3/5 3.3/5
Driver STS6 STS6
Pins
EEPROM/LED Interface
Test Access Port Interface (JTAG)
Transceiver Digital Power Transceiver Digital Power Digital power Digital power Digital power Digital power HomePNA Transceiver Analog Power Transceiver Digital Power Crystal Oscillator Power Transceiver Analog Power Transceiver Digital Ground Transceiver Analog Ground Transceiver Ground Digital Ground Digital Ground HomePNA Analog Ground
Am79C978
DESIGNATIONS Listed Driver Type
following table describes various types output drivers used Am79C978 controller. values shown table apply signaling.
sustained tri-state signal active signal that driven high clock period before left floating. differential output driver. characteristics those XTAL2 output described CHARACTERISTICS section.
Driver Name STS6 OMII1 OMII2 TSMII Totem Pole Open Drain Tri-State Tri-State
Type
(mA)
(mA)
Load (pF)
Sustained Tri-State Tri-State Tri-State Tri-State
typical characteristics, please refer Characteristics Over Commercial Operating Ranges section.
Am79C978
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination elements below.
Am79C978
ALTERNATE PACKAGING OPTION Trimmed formed tray TEMPERATURE RANGE Commercial +70° PACKAGE TYPE Plastic Quad Flat Pack (PQR160) Thin Quad Flat Pack (PQL144) SPEED OPTION applicable
DEVICE NUMBER/DESCRIPTION Am79C978 PCnet-Home Single-Chip 1/10 Mbps Home Networking Controller
Valid Combinations Am79C978 KC\W VC\W
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C978
DESCRIPTIONS Interface AD[31:0]
Address Data Input/Output Address data multiplexed same interface pins. During first clock transaction, AD[31:0] contain physical address bits). During subsequent clocks, AD[31:0] contain data. Byte ordering little endian default. AD[7:0] defined least significant byte (LSB) AD[31:24] defined most significant byte (MSB). FIFO data transfers, Am79C978 controller programmed endian byte ordering. CSR3, (BSWP) more details. During address phase transaction, when Am79C978 controller master, AD[31:2] will Am79C978 controller always drives AD[1:0] '00' during address phase indicating linear burst order. When Am79C978 controller master, AD[31:0] lines continuously monitored determine address match exists slave transfers. During data phase transaction, AD[31:0] driven Am79C978 controller when performing master write slave read operations. Data AD[31:0] latched Am79C978 controller when performing master read slave write operations. When active, AD[31:0] inputs NAND tree testing.
support clock frequency after certain precautions taken ensure data integrity. This clock derivation used drive network functions. When active, PCI_CLK input NAND tree testing.
DEVSEL
Device Select Input/Output Am79C978 controller drives DEVSEL when detects transaction that selects device target. device samples DEVSEL detect target claims transaction that Am79C978 controller initiated. When active, DEVSEL input NAND tree testing.
FRAME
Cycle Frame Input/Output FRAME driven Am79C978 controller when master indicate beginning duration transaction. FRAME asserted indicate transaction beginning. FRAME asserted while data transfers continue. FRAME deasserted before final data phase transaction. When Am79C978 controller slave mode, samples FRAME determine address phase transaction. When active, FRAME input NAND tree testing.
Grant Input This signal indicates that access been granted Am79C978 controller. Am79C978 controller supports parking. When idle system arbiter asserts without active from Am79C978 controller, device will drive AD[31:0], C/BE[3:0], lines. When active, input NAND tree testing.
C/BE[3:0]
Command Byte Enables Input/Output command byte enables multiplexed same interface pins. During address phase transaction, C/BE[3:0] define command. During data phase, C/BE[3:0] used byte enables. byte enables define which physical byte lanes carry meaningful data. C/BE0 applies byte (AD[7:0]) C/BE3 applies byte (AD[31:24]). function byte enables independent byte ordering mode (BSWP, CSR3, When active, C/BE[3:0] inputs NAND tree testing.
IDSEL
Initialization Device Select Input This signal used chip select Am79C978 controller during configuration read write transactions. When active, IDSEL input NAND tree testing.
PCI_CLK
Clock Input This clock used drive system interface internal buffer management unit. signals sampled rising edge PCI_CLK parameters defined with respect this edge. Am79C978 controller normally operates over frequency range networking demands. Am79C978 controller will
Am79C978
INTA
Interrupt Request Output attention signal which indicates that more following status flags set: EXDINT, IDON, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT, TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MREINT, STINT. Each status flag either mask enable which allows suppression INTA assertion. Table shows flag descriptions. default INTA open-drain output. applications that need high-active edge-sensitive interrupt signal, INTA configured this mode setting INTLEVEL (BCR2, Table When active, INTA output NAND tree testing. Table Interrupt Flags
Name EXDINT IDON MERR MISS MFCO MPINT RCVCCO RINT SINT TINT TXSTRT UINT Description Excessive Deferral Initialization Done Memory Error Mask CSR5, CSR3, CSR3, Interrupt CSR5, CSR0, CSR0, CSR0, CSR4, CSR5, CSR4, CSR0, CSR5, CSR0, CSR4, CSR4,
IRDY
Initiator Ready Input/Output IRDY indicates ability initiator transaction complete current data phase. IRDY used conjunction with TRDY. Wait states inserted until both IRDY TRDY asserted simultaneously. data phase completed clock when both IRDY TRDY asserted. When Am79C978 controller master, asserts IRDY during write data phases indicate that valid data present AD[31:0]. During read data phases, device asserts IRDY indicate that ready accept data. When Am79C978 controller target transaction, checks IRDY during write data phases determine valid data present AD[31:0]. During read data phases, device checks IRDY determine initiator ready accept data. When active, IRDY input NAND tree testing.
Parity Input/Output Parity even parity across AD[31:0] C/BE[3:0]. When Am79C978 controller master, generates parity during address write data phases. checks parity during read data phases. When Am79C978 controller operates slave mode, checks parity during every address phase. When target cycle, checks parity during write data phases generates parity during read data phases. When active, input NAND tree testing.
Missed Frame CSR3, Missed Frame Count OverCSR4, flow Magic Packet Interrupt CSR5,
Receive Collision Count CSR4, Overflow Receive Interrupt System Error Transmit Interrupt User Interrupt Management Command Complete Interrupt CSR3, CSR5, CSR3,
PERR
Parity Error Input/Output During slave write transaction master read transaction, Am79C978 controller asserts PERR when detects data parity error reporting error enabled setting PERREN (PCI Command register, During master write transaction, Am79C978 controller monitors PERR target reports data parity error. When active, PERR input NAND tree testing.
Transmit Start CSR4, CSR4,
MCCINT
CSR7,
CSR7,
MPDTINT MAPINT
Detect CSR7, Transition Interrupt Auto-Poll Interrupt CSR7,
CSR7, CSR7,
Request Input/Output Am79C978 controller asserts signal that wishes become master. driven high when Am79C978 controller does request bus. Power Management mode, will driven.
MREINT
Management CSR7, Frame Read Error Interrupt Software Timer CSR7, Interrupt
CSR7,
STINT
CSR7,
Am79C978
When active, input NAND tree testing.
Reset Input When asserted HIGH, then Am79C978 controller performs internal system reset type H_RESET (HARDWARE_RESET, section RESET). must held minimum clock periods. While H_RESET state, Am79C978 controller will disable deassert outputs. asynchronous clock when asserted deasserted. When LOW, disables pins except pin. When HIGH, NAND tree testing enabled.
When Am79C978 controller target transaction, asserts TRDY during read data phases indicate that valid data present AD[31:0]. During write data phases, device asserts TRDY indicate that ready accept data. When active, TRDY input NAND tree testing.
Magic Packet Interface
Power Management Event Output, Open Drain output that used indicate that power management event Magic Packet, OnNow pattern match, change link state) been detected. asserted when either PME_STATUS PME_EN both PME_EN_OVR MPMAT both PME_EN_OVR LCDET both
SERR
System Error Output During slave transaction, Am79C978 controller asserts SERR when detects address parity error, reporting error enabled setting PERREN (PCI Command register, SERREN (PCI Command register, default SERR open-drain output. component test, programmed active-high totem-pole output. When active, SERR input NAND tree testing.
signal asynchronous with respect clock. Power Saving Mode section detailed description.
Power Good Input functions: puts device into Magic Packet mode, blocks resets when power off. When either MPPEN MPMODE device enters Magic Packet mode. When LOW, assertion will only cause interface pins (except PME) high impedance state. internal logic will ignore assertion RST. When HIGH, assertion causes controller logic reset configuration information loaded from EEPROM.
STOP
Stop Input/Output slave mode, Am79C978 controller drives STOP signal inform master stop current transaction. master mode, Am79C978 controller checks STOP determine target wants disconnect current transaction. When active, STOP input NAND tree testing.
Note: input should kept high during NAND tree testing.
TRDY
Target Ready Input/Output TRDY indicates ability target transaction complete current data phase. Wait states inserted until both IRDY TRDY asserted simultaneously. data phase completed clock when both IRDY TRDY asserted. When Am79C978 controller master, checks TRDY during read data phases determine valid data present AD[31:0]. During write data phases, device checks TRDY determine target ready accept data.
Board Interface
Note: Before programming pins, description LEDPE BCR2,
LED0
LED0 Output This output designed directly drive LED. default, LED0 indicates active link connection. This also programmed indicate other network status (see BCR4). LED0 polarity programmable, default active LOW. When LED0 polarity programmed active LOW, output open drain driver. When LED0 polarity pro-
Am79C978
grammed active HIGH, output totem pole driver. Note: LED0 multiplexed with EEDI pin.
larity programmed active HIGH, output totem pole driver. Special attention must given external circuitry attached this pin. When this used drive while EEPROM used system, then buffering required between LED3 circuit. circuit were directly attached this pin, create requirement that could serial EEPROM attached this pin. EEPROM included system design current LEDs used, then LED3 signal directly connected without buffering. more details regarding connection, section Support. Note: LED3 multiplexed with EEDO pin.
LED1
LED1 Output This output designed directly drive LED. default, LED1 indicates receive activity network. This also programmed indicate other network status (see BCR5). LED1 polarity programmable, default, active LOW. When LED1 polarity programmed active LOW, output open drain driver. When LED1 polarity programmed active HIGH, output totem pole driver. Note: LED1 multiplexed with EESK pin. LED1 also used during EEPROM AutoDetection determine whether EEPROM present Am79C978 controller interface. last rising edge while active LOW, LED1 sampled determine value EEDET BCR19. important maintain adequate hold time around rising edge this time ensure correctly sampled value. sampled HIGH value means that EEPROM present, EEDET will sampled value means that EEPROM present, EEDET will EEPROM Auto-Detection section more details. circuit attached this pin, then pullup pull-down resistor must attached order select EEDET setting. WARNING: input signal level LED1 must insured correct EEPROM detection before deassertion RST.
LED4
LED4 Output This output designed directly drive LED. This programmed indicate various network status (see BCR48). LED4 polarity programmable, default active LOW. When LED4 polarity programmed active LOW, output open drain driver. When LED4 polarity programmed active HIGH, output totem pole driver.
EEPROM Interface EECS
EEPROM Chip Select Output This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EECS connected EEPROM's chip select pin. controlled either Am79C978 controller during command portions read entire EEPROM, indirectly host system writing BCR19,
LED2
LED2 Output This output designed directly drive LED. This programmed indicate various network status (see BCR6). LED2 polarity programmable, default active LOW. When LED2 polarity programmed active LOW, output open drain driver. When LED2 polarity programmed active HIGH, output totem pole driver.
EEDI
EEPROM Data Output This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EEDI connected EEPROM's data input pin. controlled either Am79C978 controller during command portions read entire EEPROM, indirectly host system writing BCR19, Note: EEDI multiplexed with LED0 pin.
LED3
LED3 Output This output designed directly drive LED. default, LED3 indicates transmit activity network. This also programmed indicate other network status (see BCR7). LED3 polarity programmable, default active LOW. When LED3 polarity programmed active LOW, output open drain driver. When LED3
EEDO
EEPROM Data Input This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EEDO connected EEPROM's data output pin. controlled either Am79C978
Am79C978
controller during command portions read entire EEPROM, indirectly host system reading from BCR19, Note: EEDO multiplexed with LED3 pin.
EESK
EEPROM Serial Clock Output This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EESK connected EEPROM's clock pin. controlled either Am79C978 controller directly during read entire EEPROM, indirectly host system writing BCR19, Note: EESK multiplexed with LED1 pin. EESK also used during EEPROM AutoDetection determine whether EEPROM present Am79C978 controller interface. rising edge last edge while asserted, EESK sampled determine value EEDET BCR19. sampled HIGH value means that EEPROM present, EEDET will sampled value means that EEPROM present, EEDET will EEPROM Auto-Detection section more details. circuit attached this pin, then pullup pull-down resistor must attached instead resolve EEDET setting. WARNING: input signal level EESK must valid correct EEPROM detection before deassertion RST.
RX_CLK synchronous receive data. order frame fully received Am79C978 device, RX_DV must asserted prior RX_CLK rising edge, when first nibble Start Frame Delimiter driven RXD[3:0], must remain asserted until after rising edge RX_CLK, when last nibble driven RXD[3:0]. RX_DV must then deasserted prior RX_CLK rising edge which follows this final nibble. RX_DV transitions synchronous RX_CLK rising edges.
Receive Carrier Sense Input input that indicates that non-idle medium, either transmit receive activity, been detected.
Collision Input input that indicates that collision been detected network medium.
RX_ER
Receive Error Input RX_ER input that indicates that transceiver device detected coding error receive data frame currently being transferred RXD[3:0] pins. RX_ER asserted while RX_DV asserted, error will indicated receive descriptor incoming receive frame. RX_ER ignored while RX_DV deasserted. Special code groups generated while RX_DV deasserted ignored (e.g., idle T4). RX_ER transitions synchronous RX_CLK.
Interface RX_CLK
Receive Clock Input RX_CLK clock input that provides timing reference transfer RX_DV, RXD[3:0], RX_ER signals into Am79C978 device. RX_CLK must provide nibble rate clock (25% network data rate). Hence, when Am79C978 device operating Mbps, provides RX_CLK frequency MHz, Mbps provides RX_CLK frequency MHz.
TX_CLK
Transmit Clock Input TX_CLK clock input that provides timing reference transfer TXD[3:0] TX_ER signals into Am79C978 device. TX_CLK must provide nibble rate clock (25% network data rate). Hence, when Am79C978 device operating Mbps, provides TX_CLK frequency MHz, Mbps provides RX_CLK frequency MHz.
RXD[3:0]
Receive Data Input RXD[3:0] nibble-wide MII-compatible receive data bus. Data RXD[3:0] sampled every rising edge RX_CLK while RX_DV asserted. RXD[3:0] ignored while RX_DV de-asserted.
TXD[3:0]
Transmit Data Output TXD[3:0] nibble-wide MII-compatible transmit data bus. Valid data generated TXD[3:0] every rising edge TX_CLK while TX_EN asserted. While TX_EN deasserted, TXD[3:0] values driven TXD[3:0] transitions synchronous rising edges TX_CLK.
RX_DV
Receive Data Valid Input RX_DV input used indicate that valid received data being presented RXD[3:0] pins
Am79C978
TX_EN
Transmit Enable Output TX_EN indicates when Am79C978 device presenting valid transmit nibbles TXD[3:0] bus. While TX_EN asserted, Am79C978 device generates TXD[3:0] TX_ER TX_CLK rising edges. TX_EN asserted with first nibble preamble remains asserted throughout duration packet until deasserted prior first TX_CLK following final nibble frame. TX_EN transitions synchronous TX_CLK.
Test Data Output test data output path from Am79C978 controller. tri-stated when JTAG port inactive.
Test Mode Select Input serial input stream used define specific boundary scan test executed. internal pull-up resistor.
Management Data Clock Output non-continuous clock output that provides timing reference bits MDIO pin. During management port operations, runs nominal frequency MHz. When management operations progress, driven LOW. port selected, left floating.
Ethernet Network Interfaces
Serial Transmit Data Output These pins carry transmit output data connected transmit side magnetics module.
Serial Receive Data Input These pins accept receive input data from magnetics module.
MDIO
Management Data Input/Output Output Input/
IREF
Internal Current Reference Input This serves current reference integrated 1/10 PHY. must connected through 12100- resistor (1%).
MDIO bidirectional management port data pin. MDIO output during header portion management frame transfers during data portion write operations. MDIO input during data portion read operations. attached port physical connector then MDIO should externally pulled down with resistor. directly attached pins then MDIO should externally pulled with resistor.
PHY_RST
Reset Output This output used reset external PHY. This output eliminates need fanout buffer reset (RST) signal, provided polarity control specific used, prevents resetting when input LOW. output polarity determined RST_POL (CRS116, bit0).
IEEE 1149.1 (1990) Test Access Port Interface
Test Clock Input clock input boundary scan test mode operation. operate frequency MHz. internal pull-up resistor.
HomePNA Network Interface HRTXRXP/HRTXRXN
Serial Receive Data Input/Output These pins accept receive input data from magnetics module carry transmit output data. 102- resistor should placed between these pins.
Test Data Input test data input path Am79C978 controller. internal pull-up resistor.
Clock Interface XCLK/XTAL
External Clock/Crystal Select Input When HIGH, external 60-MHz clock source selected bypassing crystal circuit clock trippler. When LOW, 20-MHz crystal used instead. following table illustrates this works.
Am79C978
Table External Clock/Crystal Select
Input XTAL1 XTAL1 Output XTAL2 Don't Care XCLK/XTAL Clock Source 20-MHz Crystal 60-MHz Oscillator/ External Source
DVDDD
10BASE-T Block Power +3.3 Power This supplies power Mbps Transceiver block. must connected +3.3 ±300 source. This requires careful decoupling ensure proper device performance.
DVDDRX, DVDDTX
10BASE-T Buffer Power +3.3 Power These pins supply power 10BASE-T input/output buffers. They must connected +3.3 ±300 source. These pins require careful decoupling ensure proper device performance.
XTAL1
Crystal Oscillator Input internal clock generator utilizes either 20-MHz crystal that attached pins XTAL1 XTAL2 60-MHz clock source connected XTAL1. This tolerant, clock source must from source.
DVDDA
Analog Power +3.3 Power This supplies power IREF current reference circuit 10BASE-T analog PLL. They must connected +3.3 ±300 source. These pins require careful decoupling ensure proper device performance.
XTAL2
Crystal Oscillator Output internal clock generator utilizesd 20-MHz crystal that attached pins XTAL1 XTAL2.
Power Supply VDDB
Buffer Power Pins) +3.3 Power These pins power supply pins that used input/output buffer drivers. VDDB pins must connected +3.3 supply.
DVSSX, DVSSA
10BASE-T Analog Ground Ground These pins ground connection analog section within Physical Data Transceiver (PDX) block.
DVSSD
10BASE-T Digital Ground Ground This ground connection digital logic within block.
VDD_PCI
Buffer Power Pins) +3.3 Power These pins power supply pins that used input/output buffer drivers (except driver). VDD_PCI pins must connected +3.3 supply.
VDDCO
Crystal +3.3 Power This supplies power crystal circuit.
VSSB
Buffer Ground Pins) Ground These pins ground pins that used input/output buffer drivers.
VDDHR
HomePNA Digital Power +3.3 Power These pins digital power supply pins that used internal digital circuitry HomePNA block. They must connected +3.3 source.
Digital Power Pins) +3.3 Power These pins power supply pins that used internal digital circuitry. pins must connected +3.3 supply.
VSSHR
HomePNA Analog Ground Ground This ground connection analog section within HomePNA block.
Digital Ground Pins) Ground There seven ground pins that used internal digital circuitry.
DVDDA_HR
HomePNA Analog Power +3.3 Power This supplies power analog section HomePNA block. must connected +3.3 ±300 source. This requires careful decoupling ensure proper device performance.
Am79C978
BASIC FUNCTIONS System Interface
Am79C978 controller designed operate master during normal operations. Some slave accesses Am79C978 controller required normal operations well. Initialization Am79C978 controller achieved through combination Configuration Space accesses, slave accesses, master accesses, optional read serial EEPROM that performed Am79C978 controller. EEPROM read operation performed through 93C46 EEPROM interface. 8802-3 (IEEE/ANSI 802.3) Ethernet Address reside within serial EEPROM. Some controller configuration registers also programmed EEPROM read operation. Address PROM, on-chip board-configuration registers, Ethernet controller registers occupy bytes address space. memory mapped accesses supported. Base Address registers configuration space allow locating address space wide variety starting addresses.
network operations. There descriptor area receive activity, there separate area transmit activity. descriptor space contains relocatable pointers network frame data, used transfer frame status from Am79C978 controller software. buffer areas locations that hold frame data transmission that accept frame data that been received.
Network Interfaces
Am79C978 controller provides layer functions Mbps (10BASE-T) Mbps. Am79C978 controller supports both half-duplex full-duplex operation network interface.
Media Independent Interface
Am79C978 controller fully supports according IEEE 802.3u standard. This Reconciliation Sublayer interface allows variety PHYs (100BASE-TX, 100BASE-FX, 100BASE-T4, 100BASE-T2, 10BASE-T, etc.) attached Am79C978 device without future upgrade problems. interface 4-bit (nibble) wide data path interface that runs 100-Mbps networks 10-Mbps networks. interface consists independent data paths, receive (RXD(3:0)) transmit (TXD(3:0)), control signals each data path (RX_ER, RX_DV, TX_EN), network status signals (COL, CRS), clocks (RX_CLK, TX_CLK) each data path, two-wire management interface (MDC MDIO). Figure Transmit Interface transmit clock generated external sent Am79C978 controller TX_CLK input pin. clock MHz, depending speed network which external attached. data nibble-wide bits) data path, TXD(3:0), from Am79C978 controller external synchronous rising edge TX_CLK. transmit process starts when Am79C978 controller asserts TX_EN, which indicates external that data TXD(3:0) valid. Normally, unrecoverable errors signaled through external with TX_ER output pin. external will respond this error generating coding error current transmitted frame. Am79C978 controller does this method signaling errors transmit side. Am79C978 controller will invert last byte generating invalid FCS. TX_ER should tied GND.
Software Interface
software interface Am79C978 controller divided into three parts. part configuration registers used identify Am79C978 controller setup configuration device. setup information includes memory mapped base address, mapping Expansion ROM, routing Am79C978 controller interrupt channel. This allows jumperless implementation. second portion software interface direct access resources Am79C978 controller. Am79C978 controller occupies bytes address space that must begin 32-byte block boundary. address space mapped into memory space (memory mapped I/O). Base Address Register Configuration Space controls start address address space mapped space. Memory Mapped Base Address Register controls start address address space mapped memory space. 32byte address space used software program Am79C978 controller operating mode, enable disable various features, monitor operating status, request particular functions executed Am79C978 controller. third portion software interface descriptor buffer areas that shared between software Am79C978 controller during normal network operations. descriptor area boundaries software change during nor-
Am79C978
RXD(3:0) RX_DV RX_ER RX_CLK Receive Signals
Interface
TXD(3:0) TX_EN TX_CLK Management Port Signals MDIO Transmit Signals Network Status Signals
Am79C978
22206B-4
Figure
Media Independent Interface
Receive Interface receive clock also generated external sent Am79C978 controller RX_CLK input pin. clock will same frequency TX_CLK will phase MHz, depending speed network which external attached. RX_CLK continuous clock during reception frame, stopped RX_CLK periods beginning frames, that external sync network data traffic necessary recover receive clock. During this time, external switch TX_CLK maintain stable clock receive interface. Am79C978 controller will handle this situation with loss data. data nibble-wide bits) data path, RXD(3:0), from external Am79C978 controller synchronous rising edge RX_CLK. receive process starts when RX_DV asserted. RX_DV will remain asserted until receive frame. Am79C978 controller requires (Carrier Sense) toggle between frames order receive them properly. Errors currently received frame signaled across RX_ER pin. RX_ER used signal special conditions band when RX_DV asserted. defined out-ofband conditions this 100BASE-TX signaling Start Frame Delimiter 100BASE-T4 indication illegal code group before receiver synched incoming data. Am79C978 controller will respond these conditions. band conditions currently treated NULL events.
Network Status Interface also provides signals that consistent necessary IEEE 802.3 IEEE 802.3u operation. These signals (Carrier Sense) (Collision Sense). Carrier Sense used detect non-idle activity network. Collision Sense used indicate that simultaneous transmission occurred half-duplex network. Management Interface provides two-wire management interface that Am79C978 controller control receive status from external devices. Network Port Manager copies PHYAD after Am79C978 controller reads EEPROM uses communicate with external PHY. (Refer also BCR49 description). address must programmed into EEPROM prior starting Am79C978 controller. This necessary that internal management controller work autonomously from software driver always know where access external PHY. Am79C978 controller unique offering direct hardware support external device without software support. address reserved should used. access internal external PHYs, software driver must have knowledge PHY's address before attempting address Management Interface uses Control, Address, Data registers (BCR32, control Am79C978 controller generates management frames external through MDIO synchronous rising edge Management Data Clock (MDC) based combination writes reads these registers.
Am79C978
Management Frames management frames automatically generated Am79C978 controller conform clause IEEE 802.3u standard. start frame preamble ones (unless register equals guarantees that external PHYs synchronized same interface. Figure Loss synchronization pos-
sible hot-plugging capability exposed MII. IEEE 802.3 specification allows drop preamble, after reading Status Register from external determine that external will support Preamble Suppression (BCR34, After having valid Status Register read, Am79C978 controller will then drop creation preamble stream until reset occurs, receives read error, external disconnected.
Preamble 1111.1111 Bits
Bits
Bits
Address
Register Address
Bits
Data
Idle
22206B-5
Bits
Bits
Bits
Figure
Frame Format Interface Connection sped setting FMDC bits BCR32. IEEE 802.3 specification requires 2.5-MHz clock rate, also available user. 5-MHz clock rate used exposed with external attached. 2.5MHz clock rate intended used when multiple external PHYs connected Management Port compliance IEEE 802.3u standard required. Auto-Poll External Status Polling defined IEEE 802.3 standard, external attached Am79C978 controller's communicating important timely status information back Am79C978 controller. Am79C978 controller knowing that external undergone change status without polling status register. prevent problems from occurring with nadequate host software polling, Am79C978 controller will Auto-Poll when APEP (BCR32, insure that most current information available. 10BASE-T Management Registers descriptions Status Register. contents latest read from external will stored shadow register Auto-Poll block. first read Status Register will just stored, subsequent reads will compared contents already stored shadow register. there been change contents Status Register, MAPINT (CSR7, interrupt will generated INTA MAPINTE (CSR7, Auto-Poll features disabled software driver polling required.
This followed start field (ST) operation field (OP). operation field (OP) indicates whether Am79C978 controller initiating read write operation. This followed external address (PHYAD) register address (REGAD) programmed BCR33. address 1D,1E, reserved should used. external have larger address space starting 1Fh. This address range aside IEEE vendor usable address space will vary from vendor vendor. This field followed turnaround field. During read operation, turnaround field used determine external responding correctly read request not. Am79C978 controller will tri-state MDIO both cycles. During second cycle, external synchronized Am79C978 controller, external will drive external does drive Am79C978 controller will signal MREINT (CSR7, interrupt, MREINTE (CSR7, indicating Am79C978 controller management frame read error that data BCR34 valid. data field to/from external read written into BCR34 register. last field IDLE field that necessary give ample time drivers turn before next access. Am79C978 controller will drive tristate MDIO anytime Management Port active. help speed reading writing management frames external PHY,
Am79C978
Auto-Poll's frequency generating management frames adjusted setting APDW bits (BCR32, bits 10-8). delay adjusted from periods 2048 periods. Auto-Poll default will only read Status register currently active PHY. Network Port Manager active, Network Port Manager will request status from selected generating management frames. These frames will sent roughly every These frames necessary that Network Port Manager monitor current active link notify software current link goes down.
Slave Interface Unit
slave Interface Unit (BIU) controls accesses configuration space, Control Status Registers (CSR), Configuration Registers (BCR), Address PROM (APROM) locations. Table shows response Am79C978 controller each commands slave mode. Table Slave Commands
C[3:0] 0000 0001 0010 0011 0100 0101 Command Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory mapped read CSR, BCR, APROM, Reset registers. Read Expansion Memory mapped write CSR, BCR, APROM used used Read CSR, BCR, APROM, Reset registers Write CSR, BCR, APROM
10BASE-T
10BASE-T transceiver incorporates physical layer function, including both clock recovery (ENDEC) transceiver function. Data transmission over 10BASE-T medium requires integrated 10BASE-T MAU. transceiver will meet electrical requirements 10BASE-T specified IEEE 802.3i. transmit signal filtered transceiver reduce harmonic content IEEE 802.3i. Since filtering performed silicon, external filtering modules needed. 10BASE-T transceiver receives Mbps data from across internal million nibbles second (parallel), million bits second (serial) 10BASE-T. then Manchester encodes data before transmission network. pins differential twisted-pair receivers. When properly terminated, each receiver will meet electrical requirements 10BASE-T specified IEEE 802.3i. Each receiver internal filtering does equir external modules. 10BASE-T transceiver receives Manchester coded 10BASE-T data stream from medium. then recovers clock decodes data. data stream presented internal interface parallel format.
0110
Memory Read
0111 1000 1001 1010 1011 1100 1101 1110 1111
Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate
Read Configuration Space Write Configuration Space Aliased Memory Read used Aliased Memory Read Aliased Memory Write
JTAG Configuration Information
device software configuration information follows Table Table Table Device
Vendor 1022 Device 2001 (offset 0x08)
Slave Configuration Transfers
host access configuration space with Am79C978 controller will assert DEVSEL during address phase when IDSEL asserted, AD[1:0] both access configuration cycle. AD[7:2] select DWord location configuration space. Am79C978 controller ignores AD[10:8], because
Table Software Configuration
CSR89 00001262h CSR88 00006003h JTAG 1262 6003h
Am79C978
single function device. AD[31:11] "don't cares." Table Table Slave Configuration Transfers
AD31 AD11 Don't care AD10 Don't care DWord Index
address match access cycle. configured memory mapped mode, Am79C978 controller will look address that falls within bytes memory address space (starting from memory mapped base address). Am79C978 controller asserts DEVSEL detects address match access memory cycle. DEVSEL asserted clock cycles after host asserted FRAME. Figure Figure Am79C978 controller will assert DEVSEL detects address match command correct type. memory mapped mode, Am79C978 controller aliases accesses resources command types Memory Read Multiple Memory Read Line basic Memory Read command. accesses type Memory Write Invalidate aliased basic Memory Write command. Eight-bit, 16-bit, 32-bit non-burst transactions supported. Am79C978 controller decodes address lines determine which resource accessed. typical number wait states added slave memory mapped read write access part Am79C978 controller seven clock cycles, depending upon relative phases internal Buffer Management Unit clock signal, since internal Buffer Management Unit clock divideby-two version signal. Am79C978 controller does support burst transfers access resources. When host keeps FRAME asserted second data phase, Am79C978 controller will disconnect transfer. Am79C978 controller supports fast back-to-back transactions different targets. This indicated Fast Back-To-Back Capable (PCI Status register, which hardwired Am79C978 controller capable detecting memory-mapped cycle even when address phase immediately follows data phase transaction different target, without idle state in-between. There will contention DEVSEL, TRDY, STOP signals, since Am79C978 controller asserts DEVSEL second clock after FRAME asserted (medium timing). Figure Figure
active bytes within DWord determined byte enable signals. Eight-bit, 16-bit, 32-bit transfers supported. DEVSEL asserted clock Am79C978 controller will assert TRDY third clock data phase. Am79C978 controller does support burst transfers access configuration space. When host keeps FRAME asserted second data phase, Am79C978 controller will disconnect transfer. When host tries access configuration space while automatic read EEPROM after H_RESET (see section RESET) on-going, Am79C978 controller will terminate access with disconnect/retry response. Am79C978 controller supports fast back-to-back transactions different targets. This indicated Fast Back-To-Back Capable (PCI Status register, which hardwired Am79C978 controller capable detecting configuration cycle even when address phase immediately follows data phase transaction different target without idle state in-between. There will contention DEVSEL, TRDY, STOP signals, since Am79C978 controller asserts DEVSEL second clock after FRAME asserted (medium timing).
Slave Transfers
After Am79C978 controller configured device setting IOEN (for regular mode) MEMEN (for memory mapped mode) Command register, starts monitoring access CSR, BCR, EEPROM locations. configured regular mode, Am79C978 controller will look address that falls within bytes address space (starting from base address). Am79C978 controller asserts DEVSEL detects
Am79C978
FRAME
FRAME
DATA
ADDR
ADDR
DATA
C/BE
1010
C/BE
1011
IRDY
IRDY
TRDY
TRDY
DEVSEL
DEVSEL
STOP
STOP
IDSEL
IDSEL
DEVSEL sampled
22206B-6
22206B-7
Figure Slave Configuration Read
Figure
Slave Configuration Write
FRAME
ADDR
DATA
C/BE
0010
IRDY
TRDY
DEVSEL
STOP
22206B-8
Figure
Slave Read Using Command
Am79C978
FRAME
ADDR
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
STOP
22206B-9
Figure
Slave Write Using Memory Command
Expansion Transfers
Since Am79C978 device does have expansion capabilities, configuration offset must During boot procedure, system will find Expansion ROM. system assumes that
pansion present when reads signature (byte (byte
Slave Cycle Termination
There three scenarios besides normal completion transaction where Am79C978 controller target slave cycle will terminate access.
FRAME
ADDR
DATA
C/BE
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
22206B-10
Figure Expansion Read
Am79C978
Disconnect When Busy Am79C978 controller cannot service slave access while reading contents EEPROM. Simultaneous access allowed order avoid conflicts, since EEPROM used initialize some configuration space locations most BCRs CSR116. EEPROM read operation will always happen automatically after deassertion pin. addition, host start read operation setting PREAD (BCR19, 14). While EEPROM read on-going, Am79C978 controller will disconnect slave access where target asserting STOP together with DEVSEL, while driving TRDY high. STOP will stay asserted until cycle. second situation where Am79C978 controller will generate disconnect/retry cycle when host tries access resources right after having read Reset register. Since access generates internal reset pulse about length, further slave accesses will deferred until internal reset operation completed. Figure Disconnect Burst Transfer Am79C978 controller does support burst access configuration space, resources, Expansion Bus. host indicates burst transaction keeping FRAME asserted during data phase. When Am79C978 controller sees FRAME IRDY asserted clock cycle before wants assert TRDY, also asserts STOP same time. transfer first data phase still successful, since IRDY TRDY both asserted. Figure host ready when Am79C978 controller asserts TRDY, device will wait host assert IRDY. When host asserts IRDY FRAME still asserted, Am79C978 controller will finish first data phase deasserting TRDY clock later. same time, will assert STOP signal disconnect host. STOP will stay asserted until host removes FRAME. Figure
22206B-11
FRAME
ADDR
DATA
C/BE
IRDY
TRDY
DEVSEL
STOP
Figure
Disconnect Slave Cycle When Busy
FRAME
DATA
DATA
C/BE
IRDY
TRDY
DEVSEL
STOP
22206B-12
Figure Disconnect Slave Burst Transfer Host Wait States
Am79C978
FRAME
FRAME
DATA
DATA
C/BE
ADDR
DATA
C/BE
IRDY
SERR
TRDY
DEVSEL
DEVSEL
STOP
22206B-14
Figure Address Parity Error Response
22206B-13
Figure
Disconnect Slave Burst Transfer Host Inserts Wait States
Parity Error Response
When Am79C978 controller current master, samples AD[31:0], C/BE[3:0], lines during address phase command parity error. When detects address parity error, Am79C978 controller sets PERR (PCI Status register, When reporting that error enabled setting SERREN (PCI Command register, PERREN (PCI Command register, Am79C978 controller also drives SERR signal clock cycle sets SERR (PCI Status register, assertion SERR follows Am79C978 controller will assert DEVSEL transaction that address parity error when PERREN SERREN Figure
During data phase write, memory-mapped write, configuration write command that selects Am79C978 controller target, device samples AD[31:0] C/BE[3:0] lines parity clock edge, data transferred indicated assertion IRDY TRDY. sampled following clock cycle. parity error detected reporting that error enabled setting PERREN (PCI Command register, PERR asserted clock later. parity error will always PERR (PCI Status register, even when PERREN cleared Am79C978 controller will finish transaction that data parity error normal asserting TRDY. corrupted data will written addressed location. Figure shows transaction that suffered parity error time data transferred (clock IRDY TRDY both asserted). PERR driven high beginning data phase then drops parity error clock clock cycles after data transferred. After PERR driven low, Am79C978 controller drives PERR high clock cycle, since PERR sustained tri-state signal.
Am79C978
FRAME
ADDR
DATA
C/BE
PERR
IRDY
TRDY
DEVSEL
22206B-15
Figure
Slave Cycle Data Parity Error Response
Master Interface Unit
master Interface Unit (BIU) controls acquisition accesses initialization block, descriptor rings, receive transmit buffer memory. Table shows usage commands Am79C978 controller master mode. Table
C[3:0] 0000 0001 0010 0011 0100 0101
Table
1010 1011 1100 1101 1110 1111
Master Commands (Continued)
used Read transmit buffer burst mode Read transmit buffer burst mode used
Configuration Read used Configuration Write Memory Read Multiple
Dual Address Cycle used Memory Read Line Memory Write Invalidate
Master Commands
used used used used
Command Interrupt Acknowledge Special Cycle Read Write Reserved Reserved
Acquisition microcode will determine when transfer should initiated. first step master transfer acquire ownership bus. This task handled synchronous logic within BIU. ownership requested with signal ownership granted arbiter through signal. Figure shows Am79C978 controller acquisition. asserted arbiter returns while ther ata. Am79C978 controller waits until idle (FRAME IRDY deasserted) before starts driving AD[31:0] C/BE[3:0] clock FRAME asserted clock indicating valid address command AD[31:0] C/BE[3:0]. Am79C978 controller does address stepping which reflected
0110
Memory Read
Read initialization block descriptor rings Read transmit buffer non-burst mode Write descriptor rings receive buffer
0111 1000 1001
Memory Write Reserved Reserved
Am79C978
ADSTEP (bit Command register being hardwired
Am79C978 controller will internally discard unneeded bytes. Am79C978 controller typically performs more than non-burst read transaction within single mastership period. FRAME dropped between consecutive non-burst read cycles. stays asserted until FRAME asserted last transaction. Am79C978 controller supports zero wait state read cycles. asserts IRDY immediately after address phase same time starts sampling DEVSEL. Figure shows non-burst read transactions. first transaction zero wait states. second transaction, target extends cycle asserting TRDY clock later. Basic Burst Read Transfer Am79C978 controller supports burst mode master read operations. burst mode must enabled setting BREADE (BCR18, allow burst transfers descriptor read operations, Am79C978 controller must also programmed SWSTYLE (BCR20, bits 7-0). burst read accesses initialization block descriptor ring command type Memory Read (type Burst read accesses transmit buffer typically longer than data phases. When MEMCMD (BCR18, cleared burst read accesses transmit buffer command type Memory Read Line (type 14). When MEMCMD (BCR18, burst read accesses transmit buffer command type Memory Read Multiple (type 12). AD[1:0] will both during address phase indicating linear burst order. Note that during burst read operation, byte lanes will always active. Am79C978 controller will internally discard unneeded bytes. Am79C978 controller will always perform only single burst read transaction mastership period, where transaction defined address Am79C978 controller supports zero wait state read cycles. asserts IRDY immediately after address phase same time starts sampling DEVSEL. FRAME deasserted when next last data phase completed. Figure shows typical burst read access. Am79C978 controller arbitrates bus, granted access, reads three 32-bit words (DWord) from system memory, then releases bus. example, memory system extends data phase each access wait state. example assumes that EXTREQ (BCR18, cleared therefore, deasserted same cycle FRAME asserted.
FRAME
ADDR
C/BE
IRDY
22206B-16
Figure Acquisition burst mode, deassertion depends setting EXTREQ (BCR18, EXTREQ cleared deasserted same time FRAME asserted. (The Am79C978 controller never performs more than burst transaction within single mastership period.) EXTREQ Am79C978 controller does deassert until starts last data phase transaction. Once asserted, remains active until become active independent subsequent setting STOP (CSR0, SPND (CSR5, assertion H_RESET S_RESET, however, will cause inactive immediately. Master Transfers There four primary types transfers. Am79C978 controller uses non-burst well burst cycles read write access main memory. Basic Non-Burst Read Transfer default, Am79C978 controller uses non-burst cycles master read operations. controller non-burst read accesses command type Memory Read (type Note that during non-burst read operation, byte lanes will always active.
Am79C978
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
22206B-17
Figure Non-Burst Read Transfer
FRAME
ADDR
DATA
DATA
DATA
C/BE
1110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
22206B-18
Figure Burst Read Transfer (EXTREQ MEMCMD
Am79C978
Basic Non-Burst Write Transfer default, Am79C978 controller uses non-burst cycles master write operations. controller non-burst write accesses command type Memory Write (type byte enable signals indicate byte lanes that have valid data. Am79C978 controller typically performs more than non-burst write transaction within single mastership period. FRAME dropped between consecutive non-burst write cycles. stays asserted until FRAME asserted last transaction. Am79C978 controller supports zero wait state write cycles except with descriptor write transfers. (See section Descriptor Transfers only exception.) asserts IRDY immediately after address phase. Figure shows non-burst write transactions. first transaction wait states. target inserts wait state asserting DEVSEL clock late another wait state also asserting TRDY clock late. second transaction shows zero wait state write cycle. target asserts DEVSEL TRDY same cycle Am79C978 controller asserts IRDY.
Basic Burst Write Transfer Am79C978 controller supports burst mode master write operations. burst mode must enabled setting BWRITE (BCR18, allow burst transfers descriptor write operations, Am79C978 controller must also programmed SWSTYLE (BCR20, bits 7-0). controller burst write transfers command type Memory Write (type AD[1:0] will both during address phase indicating linear burst order. byte enable signals indicate byte lanes that have valid data. Am79C978 controller will always perform single burst write transaction mastership period, where transaction defined address phase multiple data phases. Am79C978 controller supports zero wait state write cycles except with case descriptor write transfers. (See section Descriptor Transfers only exception.) device asserts IRDY immediately after address phase same time starts sampling DEVSEL. FRAME deasserted when next last data phase completed.
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0111
0111
IRDY
TRDY
DEVSEL
22206B-19
DEVSEL sampled
Figure
Non-Burst Write Transfer access, writes four 32-bit words (DWords) system memory then releases bus. this
Figure shows typical burst write access. Am79C978 controller arbitrates bus, granted
Am79C978
ample, memory system extends data phase first access wait state. following three data phases take clock cycle each, which determined timing TRDY. example assumes that EXTREQ (BCR18, therefore, deasserted until next last data phase finished. Target Initiated Termination When Am79C978 controller master, cycles produces terminated target three different ways: disconnect with data transfer, disconnect without data transfer, target abort.
Disconnect With Data Transfer Figure shows disconnection which last data transfer occurs after target asserted STOP. STOP asserted clock start termination sequence. Data still transferred during this cycle, since both IRDY TRDY asserted. Am79C978 controller terminates current transfer with deassertion FRAME clock IRDY clock later. finally releases clock wants transfer more data, Am79C978 controller will again request after clock cycles. starting address transfer will address next non-transferred data.
FRAME
ADDR
DATA
DATA
DATA
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
22206B-20
Figure Burst Write Transfer (EXTREQ
Am79C978
FRAME
ADDRi
DATA
DATA
ADDRi+8
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
22206B-21
Figure
Disconnect With Data Transfer
Disconnect Without Data Transfer Figure shows target disconnect sequence during which data transferred. STOP asserted clock without TRDY being asserted same time. Am79C978 controller terminates access with deassertion FRAME clock IRDY clock cycle later. finally releases clock Am79C978 controller will again request after clock cycles retry last transfer. starting address transfer will address last non-transferred data. Target Abort Figure shows target abort sequence. target asserts DEVSEL clock. then deasserts DEVSEL asserts STOP clock target target abort sequence indicate that cannot service data transfer that does want transaction retried. Additionally, Am79C978 controller cannot make assumption
about success previous data transfers current transaction. Am79C978 controller terminates current transfer with deassertion FRAME clock IRDY clock cycle later. finally releases clock Since data integrity guaranteed, Am79C978 controller cannot recover from target abort event. TheAm79C978 controller will reset locations their STOP_RESET values. configuration registers will cleared. on-going network transmission terminated orderly sequence. less than bits have been transmitted onto network, transmission will terminated immediately, generating runt packet. bits more have been transmitted, message will have current inverted appended next byte boundary guarantee error detected receiving station.
Am79C978
FRAME
ADDRi
DATA
ADDRi
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
22206B-22
Figure
Disconnect Without Data Transfer
RTABORT (PCI Status register, will indicate that Am79C978 controller received target abort. addition, SINT (CSR5, will When SINT set, INTA asserted enable SINTE (CSR5, This mechanism used inform driver system error. host read Status register determine exact cause interrupt. Master Initiated Termination There three scenarios besides normal completion transaction where Am79C978 controller will terminate cycles produces bus. Preemption During Non-Burst Transaction When Am79C978 controller performs multiple nonburst transactions, keeps asserted until assertion FRAME last transaction. When removed, Am79C978 controller will finish current transaction then release bus.
last transaction, will remain asserted regain ownership soon possible. Figure Preemption During Burst Transaction When Am79C978 controller operates burst mode, only performs single transaction mastership period, where transaction defined address phase multiple data phases. central arbiter remove time during transaction. TheAm79C978 controller will ignore deassertion continue with data transfers, long Latency Timer expired. When Latency Timer deasserted, Am79C978 controller will finish current data phase, deassert FRAME, finish last data phase, release bus. EXTREQ (BCR18, cleared will immediately assert regain ownership soon possible. EXTREQ will stay asserted.
Am79C978
FRAME
ADDR
DATA
C/BE
0111
0000
TheAm79C978 controller will reset locations their STOP_RESET values. configuration registers will cleared. on-going network transmission terminated orderly sequence. less than bits have been transmitted onto network, transmission will terminated immediately, generating runt packet. bits more have been transmitted, message will have current inverted appended next byte boundary guarantee error detected receiving station. RMABORT Status register, will indicate that Am79C978 controller terminated transaction with master abort. addition, SINT (CSR5, will When SINT set, INTA asserted enable SINTE (CSR5, This mechanism used inform driver system error. host read Status register determine exact cause interrupt. Figure Parity Error Response During every data phase read operation, when target indicates that data valid asserting TRDY, Am79C978 controller samples AD[31:0], C/BE[3:0], lines data parity error. When detects data parity error, Am79C978 controller sets PERR (PCI Status register, When reporting that error enabled setting PERREN (PCI Command register, Am79C978 controller also drives PERR signal sets DATAPERR (PCI Status register, assertion PERR follows corrupted data/ byte enables clock cycles clock cycle. Figure shows transaction that parity error data phase. TheAm79C978 controller asserts PERR clock clock cycles after data valid. data clock checked parity, because read access, only required valid TheAm79C978 controller then drives PERR high clock cycle, since PERR sustained tri-state signal. During every data phase write operation, Am79C978 controller checks PERR input target reports parity error. When sees PERR input asserted, Am79C978 controller sets PERR (PCI Status register, When PERREN (PCI Command register, Am79C978 controller also sets DATAPERR (PCI Status register,
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
22206B-23
Figure Target Abort When preemption occurs after counter counted down Am79C978 controller will finish current data phase, deassert FRAME, finish last data phase, release bus. Note that important host program Latency Timer according bandwidth requirement Am79C978 controller. host determine this bandwidth requirement reading MAX_LAT MIN_GNT registers. Figure assumes that Latency Timer counted down clock Master Abort TheAm79C978 controller will terminate cycle with Master Abort sequence DEVSEL asserted within clocks after FRAME asserted. Master Abort treated fatal error Am79C978 controller.
Am79C978
FRAME
ADDR
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
22206B-24
Figure
Preemption During Non-Burst Transaction
FRAME
ADDR
DATA
DATA
DATA
DATA
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
22206B-25
Figure
Preemption During Burst Transaction
Am79C978
FRAME
ADDR
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
22206B-26
Figure Master Abort
FRAME
ADDR
DATA
C/BE
0111
PERR
IRDY
TRDY
DEVSEL
DEVSEL sampled
22206B-27
Figure Master Cycle Data Parity Error Response
Am79C978
Whenever Am79C978 controller current master data parity error occurs, SINT (CSR5, will When SINT set, INTA asserted enable SINTE (CSR5, This mechanism used inform driver system error. host read Status register determine exact cause interrupt. setting SINT data parity error dependent setting PERREN (PCI Command register, default, data parity error does affect state engine. TheAm79C978 controller treats data master transfers that have parity error nothing happened.
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