PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller DISTINCTI
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Am79C961
PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller
DISTINCTIVE CHARACTERISTICS
Single-chip Ethernet controller Industry Standard Architecture (ISA) Extended Industry Standard Architecture (EISA) buses Supports IEEE 802.3/ANSI 8802-3 Ethernet standards Direct interface EISA Software compatible with AMD's Am7990 LANCE register descriptor architecture power, CMOS design with sleep mode allows reduced power consumption critical battery powered applications Individual 136-byte transmit 128-byte receive FIFOs provide packet buffering increased system latency, support following features: Automatic retransmission with FIFO reload Automatic receive stripping transmit padding (individually programmable) Automatic runt packet rejection Automatic deletion received collision frames Dynamic transmit generation programmable frame-by-frame basis Single power supply Internal/external loopback capabilities Supports 16K, 32K, Boot PROMs Flash diskless node applications Supports Microsoft's Plug Play System configuration jumperless designs Supports staggered drive reduced noise ground bounce Supports interrupts chip
Advanced Micro Devices
Look Ahead Packet Processing (LAPP) allows protocol analysis begin before receive frame Supports channels chip Supports locations Supports boot PROM locations Provides integrated Attachment Unit Interface (AUI) 10BASE-T transceiver with modes port selection: Automatic selection 10BASE-T Software selection 10BASE-T Automatic Twisted Pair receive polarity detection automatic correction receive polarity Supports bus-master shared-memory architectures application Supports edge level-sensitive interrupts Buffer Management Unit reduced intervention which allows higher throughput by-passing platform JTAG Boundary Scan (IEEE 1149.1) test access port interface board level production test Integrated Manchester Encoder/Decoder Supports following types network interfaces: external 10BASE2, 10BASE5, 10BASE-T 10BASE-F Internal 10BASE-T transceiver with Smart Squelch Twisted Pair medium Supports LANCE General Purpose Serial Interface (GPSI) 132-pin PQFP package
GENERAL DESCRIPTION
PCnet-ISA+ controller, single-chip Ethernet controller, highly integrated system solution PC-AT Industry Standard Architecture (ISA architecture. designed provide flexibility compatibility with existing application. This highly integrated 132-pin VLSI device specifically designed reduce parts count cost, addresses applications where higher system throughput desired. PCnet-ISA+
Publication# 18183 Rev. Issue Date: April 1994 Amendment
controller fabricated with AMD's advanced low-power CMOS process provide standby current power sensitive applications. PCnet-ISA+ controller DMA-based device with dual architecture that configured different operating modes suit particular application. Master Mode transfers performed using 1-475
This document contains information product under development Advanced Micro Devices, Inc. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
PRELIMINARY External remote boot Ethernet physical address PROMs Electrically Erasable Proms also supported. This advanced Ethernet controller built-in capability automatically selecting either port Twisted Pair transceiver. Only interface active time. individual 136-byte transmit 128-byte receive FIFOs optimize system overhead, providing sufficient latency during packet transmission reception, minimizing intervention during normal network error recovery. integrated Manchester encoder/decoder eliminates need external Serial Interface Adapter (SIA) node system. support external encoding/decoding scheme desired, embedded General Purpose Serial Interface (GPSI) allows direct access to/from MAC. addition, device provides programmable on-chip drivers transmit, receive, collision, receive polarity, link integrity activity, jabber status. PCnet-ISA+ controller also provides External Address Detection Interface(EADITM) allow external hardware address filtering internetworking applications.
integrated controller. This configuration enhances system performance allowing PCnet-ISA+ controller bypass platform controller directly address full 24-bit memory space. implementation Master Mode allows minimum parts count majority applications. PCnet-ISA+ controller configured perform Shared Memory operations compatibility with lowend machines, such PC/XTs that support Master high-end machines that require local packet buffering increased system latency. PCnet-ISA+ controller designed directly interface with EISA system bus. contains Plug Play interface unit, Buffer Management Unit, 802.3 Media Access Control function, individual 136-byte transmit 128-byte receive FIFOs, IEEE 802.3 defined Attachment Unit Interface (AUI), Twisted Pair Transceiver Media Attachment Unit. PCnet-ISA+ controller also register compatible with LANCE (Am7990) Ethernet controller PCnet-ISA. Buffer Management Unit supports LANCE descriptor software model.
RELATED PRODUCTS
Part Am79C98 Am79C100 Am7996 Am79C981 Am79C987 Am79C940 Am79C90 Am79C960 Am79C965 Am79C970 Description Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) IEEE 802.3/Ethernet/Cheapernet Transceiver Integrated Multiport Repeater Plus(IMR+TM) Hardware Implemented Management Information Base(HIMIBTM) Media Access Controller Ethernet (MACETM) CMOS Local Area Network Controller Ethernet (C-LANCE) PCnet-ISA Single-Chip Ethernet Controller (for bus) PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386, 486, local buses) PCnet-PCI Single-Chip Ethernet Controller (for bus)
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Am79C961
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination AM79C961 ALTERNATE PACKAGING OPTION Trimmed Formed (PQB132) OPTIONAL PROCESSING Blank Standard Processing TEMPERATURE RANGE Commercial +70°C) PACKAGE TYPE (per Prod. Nomenclature/16-038) Molded Carrier Ring Plastic Quad Flat Pack (PQB132) SPEED Applicable DEVICE NUMBER/DESCRIPTION Am79C961 Valid Combinations AM79C961 KC\W Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C961
1-477
TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS 1-475 GENERAL DESCRIPTION 1-475 RELATED PRODUCTS 1-476 ORDERING INFORMATION 1-477 BLOCK DIAGRAM: MASTER MODE 1-484 CONNECTION DIAGRAM: MASTER 1-484 DESIGNATIONS: MASTER LISTED NUMBER 1-486 LISTED NAME 1-487 LISTED GROUP 1-488 DESCRIPTION: MASTER MODE 1-490 INTERFACE 1-490 BOARD INTERFACE 1-491 BLOCK DIAGRAM: SHARED MEMORY 1-493 CONNECTION DIAGRAM: SHARED MEMORY 1-494 DESIGNATIONS: SHARED MEMORY LISTED NUMBER 1-495 LISTED NAME 1-496 LISTED GROUP 1-497 DESCRIPTION: SHARED MEMORY MODE 1-499 INTERFACE 1-499 BOARD INTERFACE 1-500 DESCRIPTION: NETWORK INTERFACES (mode independent) 1-502 1-502 TWISTED PAIR INTERFACE 1-502 IEEE 1149.1 TEST ACCESS PORT INTERFACE 1-502 DESCRIPTION: POWER SUPPLIES (mode independent) 1-502 FUNCTIONAL DESCRIPTION 1-503 MASTER MODE 1-503 SHARED MEMORY MODE 1-505 NETWORK INTERFACE 1-505 PLUG PLAY 1-507 DETAILED FUNCTIONS 1-514 EEPROM 1-514 SERIAL EEPROM BYTE 1-515 PLUG PLAY REGISTER 1-517 PLUG PLAY REGISTER LOCATIONS DETAILED DESCRIPTION 1-518 SHARED MEMORY CONFIGURATION BITS 1-520 WITHOUT EEPROM 1-521 EXTERNAL SCAN CHAIN 1-521 FLASH PROM 1-521 OPTIONAL IEEE ADDRESS PROM 1-521 EISA CONFIGURATION REGISTERS 1-521 1-478 Am79C961
INTERFACE UNIT (BIU) 1-521 Transfers 1-521 Initialization Block Transfers 1-521 Descriptor Transfers 1-522 Burst-Cycle Transfers 1-522 BUFFER MANAGEMENT UNIT (BMU) 1-522 Initialization 1-522 Reinitialization 1-522 Buffer Management 1-522 Descriptor Rings 1-522 Descriptor Ring Access Mechanism 1-523 Polling 1-523 Transmit Descriptor Table Entry (TDTE) 1-525 Receive Descriptor Table Entry (RDTE) 1-526 MEDIA ACCESS CONTROL 1-527 Transmit Receive Message Data Encapsulation 1-527 Media Access Management 1-528 MANCHESTER ENCODER/DECODER (MENDEC) 1-530 External Crystal Characteristics 1-530 External Clock Drive Characteristics 1-530 MENDEC Transmit Path 1-530 Transmitter Timing Operation 1-530 Receive Path 1-531 Input Signal Conditioning 1-531 Clock Acquisition 1-531 Tracking 1-531 Carrier Tracking Message 1-532 Data Decoding 1-532 Differential Input Terminations 1-532 Collision Detection 1-532 Jitter Tolerance Definition 1-532 Attachment Unit Interface (AUI) 1-532 TWISTED PAIR TRANSCEIVER (T-MAU) 1-532 Twisted Pair Transmit Function 1-533 Twisted Pair Receive Function 1-533 Link Test Function 1-533 Polarity Detection Reversal 1-533 Twisted Pair Interface Status 1-534 Collision Detect Function 1-534 Signal Quality Error (SQE) Test (Heartbeat) Function 1-534 Jabber Function 1-534 Power Down 1-534 EADI(External Address Detection InterfaceTM) 1-534 GENERAL PURPOSE SERIAL INTERFACE (GPSI) 1-536 IEEE 1149.1 TEST ACCESS PORT INTERFACE 1-537 Boundary Scan Circuit 1-537 Am79C961 1-479
PRELIMINARY 1-537 Supported Instructions 1-537 Instruction Register Decoding Logic 1-537 Boundary Scan Register (BSR) 1-537 Other Data Registers 1-537 POWER SAVING MODES 1-538 ACCESS OPERATIONS (SOFTWARE) Resources 1-538 Register Access 1-538 IEEE Address Access 1-538 Boot PROM Access 1-538 Static Access 1-538 CYCLES (HARDWARE) 1-538 Master Mode 1-539 Refresh Cycles 1-539 Address PROM Cycles External PROM 1-539 Ethernet Controller Register Cycles 1-540 RESET Cycles 1-540 Configuration Register Cycles 1-540 Boot PROM Cycles 1-540 Current Master Operation 1-540 Master Mode Memory Read Cycle 1-541 Master Mode Memory Write Cycle 1-541 Shared Memory Mode 1-541 Address PROM Cycles 1-541 Ethernet Controller Register Cycles 1-542 RESET Cycles 1-542 Configuration Register Cycles 1-542 Boot PROM Cycles 1-542 Static Cycles 1-542 TRANSMIT OPERATION 1-544 Transmit Function Programming 1-544 Automatic Generation 1-544 Transmit Generation 1-544 Transmit Exception Conditions 1-544 Loss Carrier 1-545 RECEIVE OPERATION 1-545 Receive Function Programming 1-545 Automatic Stripping 1-546 Receive Checking 1-546 Receive Exception Conditions 1-546 LOOPBACK OPERATION 1-547 LEDs 1-548
PCnet-ISA+ CONTROLLER REGISTERS 1-549 REGISTER ACCESS 1-549 CONTROL STATUS REGISTERS 1-549 1-480 Am79C961
CSR0: PCnet-ISA+ Controller Status Register 1-549 CSR1: IADR[15:0] 1-551 CSR2: IADR[23:16] 1-551 CSR3: Interrupt Masks Deferral Control 1-551 CSR4: Test Features Control 1-552 CSR6: RCV/XMT Descriptor Table Length 1-554 CSR8: Logical Address Filter, LADRF[15:0] 1-554 CSR9: Logical Address Filter, LADRF[31:16] 1-554 CSR10: Logical Address Filter, LADRF[47:32] 1-554 CSR11: Logical Address Filter, LADRF[63:48] 1-554 CSR12: Physical Address Register, PADR[15:0] 1-554 CSR13: Physical Address Register, PADR[31:16] 1-555 CSR14: Physical Address Register, PADR[47:32] 1-555 CSR15: Mode Register 1-555 CSR16: Initialization Block Address 1-557 CSR17: Initialization Block Address 1-557 CSR18-19: Current Receive Buffer Address 1-557 CSR20-21: Current Transmit Buffer Address 1-557 CSR22-23: Next Receive Buffer Address 1-557 CSR24-25: Base Address Receive Ring 1-557 CSR26-27: Next Receive Descriptor Address 1-558 CSR28-29: Current Receive Descriptor Address 1-558 CSR30-31: Base Address Transmit Ring 1-558 CSR32-33: Next Transmit Descriptor Address 1-558 CSR34-35: Current Transmit Descriptor Address 1-558 CSR36-37: Next Next Receive Descriptor Address 1-558 CSR38-39: Next Next Transmit Descriptor Address 1-558 CSR40-41: Current Receive Status Byte Count 1-558 CSR42-43: Current Transmit Status Byte Count 1-558 CSR44-45: Next Receive Status Byte Count 1-559 CSR46: Poll Time Counter 1-559 CSR47: Polling Interval 1-559 CSR48-49: Temporary Storage 1-559 CSR50-51: Temporary Storage 1-559 CSR52-53: Temporary Storage 1-559 CSR54-55: Temporary Storage 1-559 CSR56-57: Temporary Storage 1-560 CSR58-59: Temporary Storage 1-560 CSR60-61: Previous Transmit Descriptor Address 1-560 CSR62-63: Previous Transmit Status Byte Count 1-560 CSR64-65: Next Transmit Buffer Address 1-560 CSR66-67: Next Transmit Status Byte Count 1-560 CSR68-69: Transmit Status Temporary Storage 1-560 CSR70-71: Temporary Storage 1-560 CSR72: Receive Ring Counter 1-561 CSR74: Transmit Ring Counter 1-561 CSR76: Receive Ring Length 1-561 Am79C961 1-481
PRELIMINARY CSR78: Transmit Ring Length 1-561 CSR80: Burst FIFO Threshold Control 1-561 CSR82: Activity Timer 1-561 CSR84-85: Address 1-562 CSR86: Buffer Byte Counter 1-563 CSR88-89: Chip 1-563 CSR92: Ring Length Conversion 1-563 CSR94: Transmit Time Domain Reflectometry Count 1-563 CSR96-97: Interface Scratch Register 1-563 CSR98-99: Interface Scratch Register 1-563 CSR104-105: SWAP 1-563 CSR108-109: Buffer Management Scratch 1-564 CSR112: Missed Frame Count 1-564 CSR114: Receive Collision Count 1-564 CSR124: Buffer Management Unit Test 1-564 CONFIGURATION REGISTERS 1-564 ISACSR0: Master Mode Read Active 1-565 ISACSR1: Master Mode Write Active 1-565 ISACSR2: Miscellaneous Configuration 1-565 ISACSR3: EEPROM Configuration 1-566 ISACSR4: Link Integrity 1-567 ISACSR5: Default: 1-567 ISACSR6: Default: RCVPOL 1-568 ISACSR7: Default: 1-568 ISACSR8: Software Configuration (Read-Only Register) 1-569 INITIALIZATION BLOCK 1-569 RLEN TLEN 1-569 RDRA TDRA 1-570 LADRF PADR MODE RMD0 RMD1 RMD2 RMD3 TMD0 TMD1 TMD2 TMD3 1-570 1-570 1-570 1-571 1-571 1-572 1-572 1-572 1-572 1-573 1-573
RECEIVE DESCRIPTORS 1-571
TRANSMIT DESCRIPTORS 1-572
REGISTER SUMMARY 1-575 SYSTEM APPLICATION 1-578 INTERFACE 1-578 Compatibility Consideration 1-578
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Am79C961
Masters 1-578 Shared Memory 1-578 OPTIONAL ADDRESS PROM INTERFACE 1-582 BOOT PROM INTERFACE 1-582 STATIC INTERFACE 1-582 1-582 EEPROM INTERFACE 1-582 10BASE-T INTERFACE 1-582 ABSOLUTE MAXIMUM RATINGS 1-584 OPERATING RANGES 1-584 CHARACTERISTICS 1-584 SWITCHING CHARACTERISTICS 1-587 MASTER MODE 1-587 SHARED MEMORY MODE 1-591 EADI 1-595 JTAG (IEEE 1149.1) INTERFACE 1-595 GPSI 1-596 1-597 10BASE-T INTERFACE 1-598 SERIAL EEPROM INTERFACE 1-598 SWITCHING WAVEFORMS 1-699 SWITCHING TEST CIRCUITS 1-600 SWITCHING WAVEFORMS 1-602 MASTER MODE 1-602 SHARED MEMORY MODE 1-612 GPSI 1-622 EADI 1-623 JTAG (IEEE 1149.1) INTERFACE 1-623 1-624 10BASE-T INTERFACE 1-627 APPENDIX PCnet-ISA+ COMPATIBLE MEDIA INTERFACE MODULES 10BASE-T FILTERS TRANSFORMERS 1-629 ISOLATION TRANSFORMERS 1-629 MANUFACTURER CONTACT INFORMATION 1-630 APPENDIX LAYOUT RECOMMENDATION REDUCING NOISE DECOUPLING LOW-PASS FILTER DESIGN 1-631 APPENDIX SAMPLE CONFIGURATION FILE 1-633 APPENDIX ALTERNATIVE METHOD INITIALIZATION 1-635 APPENDIX INTRODUCTION CONCEPT LOOK AHEAD PACKET PROCESSING (LAPP) 1-636 APPENDIX SOME CHARACTERISTICS XXC56 SERIAL EEPROMs 1-646
Am79C961
1-483
BLOCK DIAGRAM: MASTER MODE
DACK[3, 5-7] DRQ[3, 5-7] IOCHRDY IOCS16 IRQ[3, MASTER MEMR MEMW RESET SBHE BALE FIFO Control Private Control RXD+/10BASE-T TXD+/TXPD+/ISA Interface Unit FIFO Encoder/ Decoder (PLS) Port FIFO 802.3 Core DXCVR/EAR
CI+/DI+/XTAL1 XTAL2 DO+/-
SD[0-15]
IRQ15/APCS BPCS LED[0-3] PRDB[0-7]
LA[17-23] SA[0-19] SLEEP SHFBUSY EEDO EEDI EESK EECS
Buffer Management Unit
EEPROM Interface Unit JTAG Port Control
DVDD[1-7] DVSS[1-13] AVDD[1-4] AVSS[1-2]
18183B-1
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Am79C961
CONNECTION DIAGRAM: MASTER
DVSS3 MASTER DRQ7 DRQ6 DRQ5 DVSS10 DACK7 DACK6 DACK5 LA17 LA18 LA19 LA20 DVSS4 LA21 LA22 LA23 SBHE DVDD3 DVSS5 DVSS6 SA10 SA11
Side View
Am79C961
18183B-2
DVDD4 SA12 SA13 SA14 SA15 DVSS7 SA16 SA17 SA18 SA19 IOCHRDY MEMW MEMR DVSS11 IRQ15/APCS IRQ12/FLASHWE IRQ11 DVDD5 IRQ10 IOCS16 BALE IRQ3 IRQ4 IRQ5 DVSS12 DRQ3 DACK3 IRQ9 RESET
DVDD2 EECS BPCS SHFBUSY PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 DVSS2 PRDB4 PRDB5 PRDB6 PRDB7 DVDD1 LED0 LED1 DVSS1 LED2 LED3 DXCVR/EAR AVDD2 CIDI+ DIAVDD1 DOAVSS1
XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXPD+ TXDTXPDAVDD4 RXD+ RXDDVSS13 SD15 SD14 DVSS9 SD13 SD12 DVDD7 SD11 SD10 DVSS8 SLEEP DVDD6
1-485
DESIGNATIONS: MASTER Listed Number
Name DVSS3 MASTER DRQ7 DRQ6 DRQ5 DVSS10 DACK7 DACK6 DACK5 LA17 LA18 LA19 LA20 DVSS4 LA21 LA22 LA23 SBHE DVDD3 DVSS5 DVSS6 SA10 SA11 DVDD4 SA12 SA13 SA14 SA15 DVSS7 SA16 SA17 SA18 SA19 Name IOCHRDY MEMW MEMR DVSS11 IRQ15/APCS IRQ12/FlashWE IRQ11 DVDD5 IRQ10 IOCS16 BALE IRQ3 IRQ4 IRQ5 DVSS12 DRQ3 DACK3 IRQ9 RESET DVDD6 SLEEP DVSS8 SD10 SD11 DVDD7 SD12 SD13 DVSS9 SD14 SD15 DVSS13 Name RXDRXD+ AVDD4 TXPDTXDTXPD+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 AVSS1 DODO+ AVDD1 DIDI+ CICI+ AVDD2 DXCVR/EAR LED3 LED2 DVSS1 LED1 LED0 DVDD1 PRDB7 PRDB6 PRDB5 PRDB4 DVSS2 PRDB3 PRDB2/EEDO PRDB1/EEDI PRDB0/EESK SHFBUSY BPCS EECS DVDD2
1-486
Am79C961
DESIGNATIONS: MASTER Listed Name
Name AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BALE BPCS CICI+ DACK3 DACK5 DACK6 DACK7 DIDI+ DODO+ DRQ3 DRQ5 DRQ6 DRQ7 DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVDD7 DVSS1 DVSS10 DVSS11 DVSS12 DVSS13 DVSS2 DVSS3 DVSS4 DVSS5 DVSS6 DVSS7 DVSS8 DVSS9 DXCVR/EAR Name EECS IOCHRDY IOCS16 IRQ10 IRQ11 IRQ12/FlashWE IRQ15/APCS IRQ3 IRQ4 IRQ5 IRQ9 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LED0 LED1 LED2 LED3 MASTER MEMR MEMW PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 RESET RXDRXD+ SA10 SA11 SA12 Name SA13 SA14 SA15 SA16 SA17 SA18 SA19 SBHE SD10 SD11 SD12 SD13 SD14 SD15 SHFBUSY SLEEP TXDTXD+ TXPDTXPD+ XTAL1 XTAL2
Am79C961
1-487
DESIGNATIONS: MASTER Listed Group
Name Interface BALE DACK[3, 5-7] DRQ[3, 5-7] IOCHRDY IOCS16 IRQ[3, LA[17-23] MASTER MEMR MEMW RESET SA[0-19] SBHE SD[0-15] Board Interfaces IRQ15/APCS BPCS DXCVR/EAR LED0 LED1 LED2 LED3 PRDB[3-7] SLEEP XTAL1 XTAL2 SHFBUSY PRDB(0)/EESK PRDB(1)/EEDI PRDB(2)/EEDO EECS IRQ15 Address PROM Chip Select Boot PROM Chip Select Disable Transceiver LED0/LNKST LED1/SFBD/RCVACT LED2/SRD/RXDATPOL LED3/SRDCLK/XMTACT PROM Data Sleep Mode Crystal Input Crystal Output Read access from EEPROM process Serial Shift Clock Serial Shift Data Serial Shift Data EEPROM Chip Select Address Enable Address Latch Enable Acknowledge Request Channel Ready Chip Select Read Select Write Select Interrupt Request Unlatched Address Master Transfer Progress Memory Read Select Memory Write Select Memory Refresh Active System Reset System Address System Byte High Enable System Data TS3/OD3 Function Driver
1-488
Am79C961
DESIGNATIONS: MASTER (continued) Listed Group
Name Attachment Unit Interface (AUI) RXD± TXD± TXPD± Power Supplies AVDD AVSS DVDD DVSS Analog Power [1-4] Analog Ground [1-2] Digital Power [1-7] Digital Ground [1-13] Collision Inputs Receive Data Transmit Data 10BASE-T Receive Data 10BASE-T Transmit Data 10BASE-T Predistortion Control Test Clock Test Data Input Test Data Output Test Mode Select Function Driver
Twisted Pair Transceiver Interface (10BASE-T)
IEEE 1149.1 Test Access Port Interface (JTAG)
Output Driver Types
Name Type Tri-State Tri-State Tri-State Open Drain (mA) (mA)
Am79C961
1-489
PRELIMINARY Because operation Plug Play registers, Channels PCnet-ISA+ must attached specific DACK signals PC/AT bus.
DESCRIPTION: MASTER MODE
These pins part master mode. order understand descriptions, definition some terms from draft IEEE P996 included.
IOCHRDY
Channel Ready Input/Output When PCnet-ISA controller being accessed, IOCHRDY HIGH indicates that valid data exists data reads that data been latched writes. When PCnet-ISA+ controller Current Master bus, extends cycle long IOCHRDY LOW.
IEEE P996 Terminology
Alternate Master: device that take control through assertion MASTER signal. ability generate addresses control signals order perform operations. Alternate Masters must devices drive SBHE. Ownership: Current Master possesses ownership assert control, address data lines. Current Master: Permanent Master, Temporary Master Alternate Master which currently ownership bus. Permanent Master: Each P996 will have device known Permanent Master that provides certain signals control functions described Section IEEE P996 spec), "Permanent Master". Permanent Master function reside Adapter backplane itself. Temporary Master: device that capable generating request obtain control directly asserting only memory strobes during transfer. Addresses generated device Permanent Master.
IOCS16
Chip Select Output When read write operation performed, PCnet-ISA+ controller will drive IOCS16 indicate that chip supports 16-bit operation this address. motherboard does receive this signal, then motherboard will convert 16-bit access 8-bit accesses.) PCnet-ISA+ controller follows IEEE P996 specification that recommends this function implemented pure decode SA0-9 AEN, with dependency IOR, IOW; however, some PC/AT clone systems compatible with this approach. this reason, PCnet-ISA+ controller recommended configured 8-bit machines. Since data moved memory cycles there virtually performance loss incurred running 8-bit compatibility problems virtually eliminated. PCnet-ISA+ controller configured 8-bitonly clearing Plug Play register
Interface
Address Enable Input This signal must driven when performs access device.
Read Input driven host indicate that Input/ Output Read operation taking place. only valid signal external address matches PCnet-ISA+ controller's predefined address location. valid, indicates that slave read operation performed.
BALE
Used latch LA20-23 address lines.
DACK
Acknowledge Input Asserted when Permanent Master acknowledges request. When DACK asserted PCnet-ISA+ controller becomes Current Master asserting MASTER signal.
Write Input driven host indicate that Input/ Output Write operation taking place. only valid signal external address matches PCnet-ISA+ controller's predefined address location. valid, indicates that slave write operation performed.
Request Output When PCnet-ISA+ controller needs perform transfer, asserts DRQ. Permanent Master acknowledges with assertion DACK. When PCnet-ISA+ controller does need deasserts DRQ.
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Interrupt Request Output attention signal which indicates that more following status flags set: BABL, MISS, MERR, RINT, IDON, RCVCCO, JAB, MPCO, TXDATSTRT. status flags have mask which allows suppression assertion. These flags have following meaning:
BABL RCVCCO MISS MERR MPCO RINT IDON TXDATSTRT Babble Receive Collision Count Overflow Jabber Missed Frame Memory Error Missed Packet Count Overflow Receive Interrupt Initialization Done Transmit Start
MEMW
Memory Write Input/Output MEMW goes perform memory write operation.
Memory Refresh Input When asserted, memory refresh active. PCnet-ISA+ controller uses this signal mask inadvertent Acknowledge assertion during memory refresh periods. DACK asserted when active, DACK assertion ignored. monitored eliminate arbitration problem observed some platforms.
RESET
Reset Input When RESET asserted HIGH PCnet-ISA+ controller performs internal system reset. RESET must held minimum XTAL1 periods before being deasserted. While reset state, PCnet-ISA+ controller will tristate deassert outputs predefined reset levels. PCnet-ISA+ controller resets itself upon power-up.
Because operation Plug Play registers, interrupts PCnet-ISA+ must attached specific signals PC/AT bus.
LA17-23
Unlatched Address Input/Output unlatched address driven PCnet-ISA+ controller during master cycle. functions these unlatched address pins will change when GPSI mode invoked. following table shows configuration GPSI mode. Please refer section General Purpose Serial Interface detailed information accessing this mode.
Number Function Master Mode LA17 LA18 LA19 LA20 LA21 LA22 LA23 Function GPSI Mode RXDAT SRDCLK RXCRS CLSN STDCLK TXEN TXDAT
SA0-19
System Address Input/Output This contains address information, which stable during operation, regardless source. SA17-19 contain same values unlatched address LA17-19. When PCnet-ISA+ controller Current Master, SA0-19 will driven actively. When PCnet-ISA+ controller Current Master, SA0-19 lines continuously monitored determine address match exists slave transfers Boot PROM accesses.
SBHE
System Byte High Enable Input/Output This signal indicates high byte system data used. SBHE driven PCnet-ISA+ controller when performing mastering operations.
SD0-15
System Data Input/Output These pins used transfer data from PCnet-ISA+ controller system resources data bus. SD0-15 driven PCnet-ISA+ controller when performing master writes slave read operations. Likewise, data SD0-15 latched PCnet-ISA+ controller when performing master reads slave write operations.
MASTER
Master Mode Input/Output This signal indicates that PCnet-ISA+ controller become Current Master bus. After PCnet-ISA+ controller received Acknowledge (DACK) response Request (DRQ), Ethernet controller asserts MASTER signal indicate Permanent Master that PCnet-ISA+ controller becoming Current Master.
Board Interface IRQ12/FlashWE
Flash Write Enable Output Optional interface Flash memory boot PROM Write Enable.
MEMR
Memory Read Input/Output MEMR goes perform memory read operation.
Am79C961
1-491
IRQ15/APCS
Address PROM Chip Select Output When programmed APCS Plug Play Register this signal asserted when external Address PROM read. When read operation performed first bytes PCnet-ISA+ controller's space, APCS asserted. outputs external Address PROM drive PROM Data Bus. PCnet-ISA+ controller buffers contents PROM data drives them lower eight bits System Data Bus. When programmed IRQ15 (default), this same function
PRDB3-7
Private Data Input/Output This data Boot PROM Address PROM.
PRDB2/EEDO
Private data 2/Data Input/Output multifunction which serves PRDB2 private data and, when ISACSR3 set, changes become DATA from EEPROM.
PRDB1/EEDI
Private data 1/Data Input/Output multifunction which serves PRDB1 private data and, when ISACSR3 set, changes become DATA EEPROM.
BPCS
Boot PROM Chip Select Output This signal asserted when Boot PROM read. SA0-19 lines match predefined address block MEMR active inactive, BPCS signal will asserted. outputs external Boot PROM drive PROM Data Bus. PCnet-ISA+ controller buffers contents PROM data drives them lower eight bits System Data Bus.
PRDB0/EESK
Private data Serial Clock Input/Output multifunction which serves PRDB0 private data and, when ISACSR3 set, changes become Serial Clock EEPROM.
DXCVR/EAR
Disable Transceiver/ Input/Output External Address Reject This disables transceiver. DXCVR output configured initialization sequence. HIGH level indicates Twisted Pair port active port inactive, SLEEP mode been entered. level indicates port active Twisted Pair port inactive. EADI mode selected, this becomes input. incoming frame will checked against internally active address detection mechanisms result this check will OR'd with value pin. defined REJECT. (See EADI section details regarding function timing this signal.)
Input/Output SHFBUSY output from PCnet-ISA+ which indicates that read from external EEPROM progress. active only when hardware reconfigure running (when data being shifted EEPROM hardware RESET EELOAD command being issued). This should have pull-up resistor VCC.
EECS
EEPROM CHIPSELECT Output This signal asserted when read write accesses being performed EEPROM. controlled ISACSR3. driven Reset during EEPROM Read.
SLEEP
Sleep Input When SLEEP asserted (active LOW), PCnet-ISA+ controller performs internal system reset proceeds into power savings mode. outputs will placed their normal reset condition. PCnet-ISA+ controller inputs will ignored except SLEEP itself. Deassertion SLEEP results wake-up. system must delay starting network controller seconds allow internal analog circuits stabilize.
LED0-3
Drivers Output These pins sink each driving LEDs. Their meaning software configurable (see section Configuration Registers) they active LOW. When EADI mode selected, pins named LED1, LED2, LED3 change function while LED0 continues indicate 10BASE-T Link Status.
EADI Function SF/BD SRDCLK
XTAL1
Crystal Connection Input internal clock generator uses crystal that attached pins XTAL1 XTAL2. Alternatively, external CMOS-compatible clock signal used drive this pin. Refer section External Crystal Characteristics more details.
XTAL2
Crystal Connection Output internal clock generator uses crystal that attached pins XTAL1 XTAL2. external clock used, this should left unconnected.
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Am79C961
BLOCK DIAGRAM: SHARED MEMORY MODE
DXCVR/EAR IOCHRDY IRQ[3, IOCS16 MEMR MEMW RESET SA[0-15] SBHE FIFO Control Private Control RXD+/10BASE-T TXD+/TXPD+/ISA Interface Unit FIFO Encoder/ Decoder (PLS) Port FIFO 802.3 Core
CI+/DI+/XTAL1 XTAL2 DO+/-
SD[0-15]
SLEEP BPAM SMAM SHFBUSY EEDO EEDI EESK EECS
Buffer Management Unit
IRQ15/APCS BPCS LED[0-3] PRAB[0-15] PRDB[0-7] SROE SRWE
EEPROM Interface Unit JTAG Port Control
18183B-3
DVDD[1-7] DVSS[1-13] AVDD[1-4] AVSS[1-2]
Am79C961
1-493
CONNECTION DIAGRAM: SHARED MEMORY
DVDD2 EECS BPCS SHFBUSY PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 DVSS2 PRDB4 PRDB5 PRDB6 PRDB7 DVDD1 LED0 LED1 DVSS1 LED2 LED3 DXCVR/EAR AVDD2 CIDI+ DIAVDD1 DOAVSS1 DVSS3 DVSS10 DVSS4 SA10 SA11 SA12 SBHE DVDD3 PRAB0 PRAB1 PRAB2 DVSS5 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 DVSS6 PRAB10 PRAB11
Side View
XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXPD+ TXDTXPDAVDD4 RXD+ RXDDVSS13 SD15 SD14 DVSS9 SD13 SD12 DVDD7 SD11 SD10 DVSS8 SLEEP DVDD6
DVDD4 PRAB12 PRAB13 PRAB14 PRAB15 DVSS7 SA13 SA14 SA15 SRWE IOCHRDY MEMW MEMR DVSS11 IRQ15 IRQ12 IRQ11 DVDD5 IRQ10 IOCS16 BPAM IRQ3 IRQ4 IRQ5 DVSS12 SROE SMAM IRQ9 RESET
18183B-4
1-494
Am79C961
DESIGNATIONS: SHARED MEMORY Listed Number
Name DVSS3 DVSS10 DVSS4 SA10 SA11 SA12 SBHE DVDD3 PRAB0 PRAB1 PRAB2 DVSS5 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 DVSS6 PRAB10 PRAB11 DVDD4 PRAB12 PRAB13 PRAB14 PRAB15 DVSS7 SA13 SA14 SA15 SRWE Name IOCHRDY MEMW MEMR DVSS11 IRQ15 IRQ12 IRQ11 DVDD5 IRQ10 IOCS16 BPAM IRQ3 IRQ4 IRQ5 DVSS12 SROE SMAM IRQ9 RESET DVDD6 SLEEP DVSS8 SD10 SD11 DVDD7 SD12 SD13 DVSS9 SD14 SD15 DVSS13 Name RXDRXD+ AVDD4 TXPDTXDTXPD+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 AVSS1 DODO+ AVDD1 DIDI+ CICI+ AVDD2 DXCVR/EAR LED3 LED2 DVSS1 LED1 LED0 DVDD1 PRDB7 PRDB6 PRDB5 PRDB4 DVSS2 PRDB3 PRDB2/EEDO PRDB1/EEDI PRDB0/EESK SHFBUSY BPCS EECS DVDD2
Am79C961
1-495
DESIGNATIONS: SHARED MEMORY Listed Name
Name AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BPAM BPCS CICI+ DIDI+ DODO+ DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVDD7 DVSS1 DVSS10 DVSS11 DVSS12 DVSS13 DVSS2 DVSS3 DVSS4 DVSS5 DVSS6 DVSS7 DVSS8 DVSS9 DXCVR/EAR EECS IOCHRDY IOCS16 IRQ10 IRQ11 IRQ12 Name IRQ15 IRQ3 IRQ4 IRQ5 IRQ9 LED0 LED1 LED2 LED3 MEMR MEMW PRAB0 PRAB1 PRAB10 PRAB11 PRAB12 PRAB13 PRAB14 PRAB15 PRAB2 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 PRDB0/DO PRDB1/DI PRDB2/SCLK PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 RESET RXDRXD+ SA10 SA11 SA12 Name SA13 SA14 SA15 SBHE SD10 SD11 SD12 SD13 SD14 SD15 SHFBUSY SLEEP SMAM SROE SRWE TXDTXD+ TXPDTXPD+ XTAL1 XTAL2
1-496
Am79C961
DESIGNATIONS: SHARED MEMORY Listed Group
Name Interface IOCHRDY IOCS16 IRQ[3, MEMR MEMW RESET SA[0-15] SBHE SD[0-15] Board Interfaces IRQ15/APCS BPCS BPAM DXCVR/EAR LED0 LED1 LED2 LED3 PRAB[0-15] PRDB[3-7] SLEEP SMAM SROE SRWE XTAL1 XTAL2 SHFBUSY PRDB(0)/EESK PRDB(1)/EEDI PRDB(2)/EEDO EECS IRQ15 Address PROM Chip Select Boot PROM Chip Select Boot PROM Address Match Disable Transceiver LED0/LNKST LED1/SFBD/RCVACT LED2/SRD/RXDATD01 LED3/SRDCLK/XMTACT PRivate Address PRivate Data Sleep Mode Shared Memory Architecture Shared Memory Address Match Static Output Enable Static Write Enable Crystal Oscillator Input Crystal Oscillator OUTPUT Read access from EEPROM process Serial Shift Clock Serial Shift Data Serial Shift Data EEPROM Chip Select Address Enable Channel Ready Chip Select Read Select Write Select Interrupt Request Memory Read Select Memory Write Select Memory Refresh Active System Reset System Address System Byte High Enable System Data TS3/OD3 Function Driver
Am79C961
1-497
DESIGNATIONS: SHARED MEMORY (continued) Listed Group
Name Attachment Unit Interface (AUI) RXD± TXD± TXPD± Power Supplies AVDD AVSS DVDD DVSS Analog Power [1-4] Analog Ground [1-2] Digital Power [1-7] Digital Ground [1-13] Collision Inputs Receive Data Transmit Data 10BASE-T Receive Data 10BASE-T Transmit Data 10BASE-T Predistortion Control Test Clock Test Data Input Test Data Output Test Mode Select Function Driver
Twisted Pair Transceiver Interface (10BASE-T)
IEEE 1149.1 Test Access Port Interface (JTAG)
Output Driver Types
Name Type Tri-State Tri-State Tri-State Open Drain (mA) (mA)
1-498
Am79C961
DESCRIPTION: SHARED MEMORY MODE Interface
Address Enable Input This signal must driven when performs access device.
which allows suppression assertion. These flags have following meaning:
BABL RCVCCO MISS MERR MPCO RINT IDON TXSTRT Babble Receive Collision Count Overflow Jabber Missed Frame Memory Error Missed Packet Count Overflow Receive Interrupt Initialization Done Transmit Start
IOCHRDY
Channel Ready Output When PCnet-ISA controller being accessed, HIGH IOCHRDY indicates that valid data exists data reads that data been latched writes.
MEMR
Memory Read Input MEMR goes perform memory read operation.
IOCS16
Chip Select Input/Output When read write operation performed, PCnet-ISA+ controller will drive this indicate that chip supports 16-bit operation this address. motherboard does receive this signal, then motherboard will convert 16-bit access 8-bit accesses.) PCnet-ISA+ controller follows IEEE P996 specification that recommends this function implemented pure decode SA0-9 AEN, with dependency IOR, IOW; however, some PC/AT clone systems compatible with this approach. this reason, PCnet-ISA+ controller recommended configured 8-bit machines. Since data moved memory cycles there virtually performance loss incurred running 8-bit compatibility problems virtually eliminated. PCnet-ISA+ controller configured 8-bitonly clearing Plug Play Register
MEMW
Memory Write Input MEMW goes perform memory write operation.
RESET
Reset Input When RESET asserted HIGH, PCnet-ISA+ controller performs internal system reset. RESET must held minimum XTAL1 periods before being deasserted. While reset state, PCnet-ISA+ controller will tristate deassert outputs predefined reset levels. PCnet-ISA+ controller resets itself upon power-up.
SA0-15
System Address Input This carries address inputs from system address bus. Address data stable during command active cycle.
Read Input perform Input/Output Read operation device must asserted. only valid signal external address matches PCnet-ISA+ controller predefined address location. valid, indicates that slave read operation performed.
SBHE
System High Enable Input This signal indicates HIGH byte system data used. There weak pull-up resistor this pin. PCnet-ISA+ controller installed 8-bit only system like PC/XT, SBHE will always HIGH PCnet-ISA+ controller will perform only 8-bit operations. There must least going edge this signal before PCnet-ISA+ controller will perform 16-bit operations.
Write Input perform Input/Output write operation device must asserted. only valid signal external address matches PCnet-ISA+ controller's predefined address location. valid, indicates that slave write operation performed.
SD0-15
System Data Input/Output This used transfer data from PCnet-ISA+ controller system resources data bus. SD0-15 driven PCnet-ISA+ controller when performing slave read operations. Likewise, data SD0-15 latched PCnet-ISA+ controller when performing slave write operations. 1-499
IRQ3,
Interrupt Request Output attention signal which indicates that more following status flags set: BABL, MISS, MERR, RINT, IDON TXSTRT. status flags have mask
Am79C961
EADI Function SF/BD SRDCLK
BOARD INTERFACE APCS/IRQ15
Address PROM Chip Select Output This signal asserted when external Address PROM read. When read operation performed first bytes PCnet-ISA+ controller's space, APCS asserted. outputs external Address PROM drive PROM Data Bus. PCnet-ISA+ controller buffers contents PROM data drives them lower eight bits System Data Bus. IOCS16 asserted during this cycle.
PRAB0-15
Private Address Input/Output Private Address address used drive Address PROM, Remote Boot PROM, SRAM. PRAB10-15 required buffered Buffer with ABOE control SA10-15 inputs.
BPAM
Boot PROM Address Match Input This indicates Boot PROM access cycle. Boot PROM installed, this default value HIGH thus left connected VDD.
PRDB3-7
Private Data Input/Output This data static RAM, Boot PROM, Address PROM.
BPCS
Boot PROM Chip Select Output This signal asserted when Boot PROM read. BPAM active MEMR active, BPCS signal will asserted. outputs external Boot PROM drive PROM Data Bus. PCnet-ISA+ controller buffers contents PROM data drives them System Data Bus. IOCS16 asserted during this cycle. 16-bit cycles performed, responsibility external logic assert MEMCS16 signal.
PRDB2/EEDO
Private Data 2/Data Input/Output multifunction which serves PRDB2 private data and, when ISACSR3 set, changes become DATA from EEPROM.
PRDB1/EEDI
Private Data 1/Data Input/Output multifunction which serves PRDB1 private data and, when ISACSR3 set, changes become DATA EEPROM.
DXCVR/EAR
Disable Transceiver/ External Address Reject Input/Output This disables transceiver. DXCVR output configured initialization sequence. high level indicates Twisted Pair Interface active inactive, SLEEP mode been entered. level indicates active Twisted Pair interface inactive. EADI mode selected, this becomes input. incoming frame will checked against internally active address detection mechanisms result this check will OR'd with value pin. defined REJECT. (See EADI section details regarding function timing this signal.)
PRDB0/EESK
Private Data Serial Clock Input/Output multifunction which serves PRDB0 private data and, when ISACSR3 set, changes become Serial Clock EEPROM.
SHFBUSY
Shift Busy Input/Output output from PCnet-ISA+ which indicates that read from external EEPROM progress. active only when hardware reconfigure running (when data being shifted EEPROM hardware RESET EELOAD command being issued). SHFBUSY should connected with resistor.
LED0-3
Drivers Output These pins sink each driving LEDs. Their meaning software configurable (see section Configuration Registers) they active LOW. When EADI mode selected, pins named LED1, LED2, LED3 change function while LED0 continues indicate 10BASE-T Link Status. DXCVR input becomes input.
EECS
EEPROM CHIPSELECT Output This signal asserted when read write accesses being performed EEPROM. controlled ISACSR3. driven Reset during EEPROM Read.
SLEEP
Sleep Input When SLEEP input asserted (active LOW), PCnet-ISA+ controller performs internal system reset
1-500
Am79C961
PRELIMINARY proceeds into power savings mode. outputs will placed their normal reset condition. PCnet-ISA+ controller inputs will ignored except SLEEP itself. Deassertion SLEEP results wake-up. system must delay starting network controller seconds allow internal analog circuits stabilize.
When Flash boot option selected, this becomes IRQ12.
SRWE/WE
Static Write Enable/ Write Enable Output This (SRWE) directly controls external SRAM's when Flash memory device implemented. When Flash memory device implemented, this becomes global write enable (WE) pin.
Shared Memory Architecture Input This sampled after hardware RESET sequence. must pulled permanently operation shared memory mode.
XTAL1
Crystal Connection Input internal clock generator uses crystal that attached pins XTAL1 XTAL2. Alternatively, external CMOS-compatible clock signal used drive this pin. Refer section External Crystal Characteristics more details.
SMAM
Shared Memory Address Match Input This indicates access shared memory when active. type access decided MEMR MEMW.
SROE
Static Output Enable Output This directly controls external SRAM's pin.
XTAL2
Crystal Connection Output internal clock generator uses crystal that attached pins XTAL1 XTAL2. external clock used, this should left unconnected.
SRCS/IRQ12
Static Chip Select Output This directly controls external SRAM's chip select (CS) when Flash boot option selected.
Am79C961
1-501
DESCRIPTION: NETWORK INTERFACES CI+,
Control Input Input This differential input pair used detect Collision (Signal Quality Error Signal).
Test Data Output Output This test data output path from PCnet-ISA+ controller. tri-stated when JTAG port inactive.
Test Mode Select Input This serial input stream used define specific boundary scan test executed. left unconnected, this default value HIGH.
DI+,
Data Input This differential receive data input pair PCnetISA+ controller.
DESCRIPTION: POWER SUPPLIES
power pins with prefix digital pins connected digital circuitry digital buffers. power pins with prefix analog power pins connected analog circuitry. analog pins quiet special precaution must taken when doing board layout. Some analog pins more noisy than others must separated from other analog pins.
DO+,
Data Output This differential transmit data output pair from PCnet-ISA+ controller.
Twisted Pair Interface RXD+, RXD-
Receive Data Input This 10BASE-T port differential receive input pair.
AVDD1-4
Analog Power Pins) Power Supplies power analog portions PCnet-ISA+ controller. Special attention should paid printed circuit board layout avoid excessive noise these lines.
TXD+, TXD-
Transmit Data Output These 10BASE-T port differential transmit drivers.
AVSS1-2
Analog Ground Pins) Power Supplies ground reference analog portions PCnet-ISA+ controller. Special attention should paid printed circuit board layout avoid excessive noise these lines.
TXP+, TXP-
Transmit Predistortion Control Output These 10BASE-T transmit waveform pre-distortion control differential outputs.
DVDD1-7 DESCRIPTION: IEEE 1149.1 (JTAG) TEST ACCESS PORT
Test Clock Input This clock input boundary scan test mode operation. operate MHz. does have internal pullup resistor must connected valid level high low. must left unconnected. Digital Power Pins) Power Supplies power digital portions PCnet-ISA+ controller. Four pins used Input/Output buffer drivers used internal digital circuitry.
DVSS1-13
Digital Ground Pins) Power Supplies ground reference digital portions PCnet-ISA+ controller. pins used Input/Output buffer drivers used internal digital circuitry.
Test Data Input Input This test data input path PCnet-ISA+ controller. left unconnected, this default value HIGH.
1-502
Am79C961
FUNCTIONAL DESCRIPTION
PCnet-ISA controller highly integrated system solution PC-AT architecture. provides Ethernet controller, port, 10BASE-T transceiver. PCnet-ISA+ controller directly interfaced system bus. PCnet-ISA+ controller contains interface unit, Buffer Management Unit, 802.3 Media Access Control function, separate 136-byte transmit 128-byte receive FIFOs, IEEE defined Attachment Unit Interface (AUI), Twisted-Pair Transceiver Media Attachment Unit. addition, Sleep function been incorporated which provides standby current power sensitive applications. PCnet-ISA+ controller register compatible with LANCE (Am7990) Ethernet controller PCnet-ISA (Am79C960). Buffer Management Unit supports LANCE descriptor software model PCnet-ISA+ controller software compatible with Novell NE2100 NE1500T add-in cards. External remote boot PROMs Ethernet physical address PROMs supported. location registers, Ethernet address PROM, boot PROM determined programming registers internal PCnet-ISA+. These registers loaded RESET from EEPROM. Normally, Ethernet physical address will stored EEPROM with other configuration data. This reduces parts count, board space requirements, power consumption. option standard parallel PROM provided manufactures concerned about non-volatile nature EEPROMs. PCnet-ISA+ controller's master architecture brings system manufacturers (adapter card motherboard makers alike) something they have been able enjoy with other architectures-a low-cost system solution that provides lowest parts count highest performance. bus-mastering device, costly power-hungry external SRAMs needed packet buffering. This results lower system cost fewer components, less real-estate less power.
PCnet-ISA+ controller's advanced mastering architecture also provides high data throughput utilization even better performance. offer greater flexibility, PCnet-ISA+ controller shared memory mode meet varying application needs. shared memory architecture compatible with very low-end machines, such PC/XTs that support mastering, very high machines which require local packet buffering increased system latency. network interface provides Attachment Unit Interface Twisted-Pair Transceiver functions. Only interface active particular time. allows connection isolation transformer 10BASE5 10BASE2, thick thin based coaxial cables. Twisted-Pair Transceiver interface allows connection unshielded twisted-pair cables specified Section supplement IEEE 802.3 Standard (Type 10BASE-T).
Master Mode
System Interface PCnet-ISA+ controller fundamental operating modes, Master Shared Memory. selection either Master mode Shared Memory mode must done through hard wiring; software configurable. Master mode provides Am7990 (LANCE) compatible Ethernet controller, Ethernet Address EEPROM PROM, Boot PROM, device configuration registers. optional Boot PROM memory address space expected 8-64K. On-chip address comparators control device selection based value EEPROM. address PROM, board configuration registers, Ethernet controller occupy bytes space located different starting addresses. Data buffers located system memory accessed PCnet-ISA+ controller when device becomes Current Master.
Am79C961
1-503
BPCS 16-Bit System Data SD[0-15] PRDB[2]/EEDO PRDB[1]/EEDI PRDB[0]/EESK PRDB[0-7]
D[0-7]
Boot PROM
PCnet-ISA+ Controller 24-Bit System Address SA[0-19] LA[17-23]
A[0-15]
SHFBUSY
EECS
EEPROM
18183B-6
Master Block Diagram Plug Play Compatible
1-504
Am79C961
SD[0-15] 16-Bit System Data
BPCS PRDB[0-7]
A[0-4] D[0-7] IEEE Address PROM
PRDB[0]/EESK PCnet-ISA+ Controller SA[0-19] LA[17-23] PRDB[1]/EEDI PRDB[2]/EEDO A[0-15] D[0-7] Flash EECS
24-Bit System Address
IRQ15/APCS IRQ12/FlashWE SHFBUSY
EEPROM
18183B-7
Master Block Diagram Plug Play Compatible with Flash Support
Shared Memory Mode
System Interface Shared Memory mode other fundamental operating mode available PCnet-ISA+ controller. PCnet-ISA+ controller uses same descriptor buffer architecture LANCE, these data structures stored static controlled PCnet-ISA+ controller. static visible memory resource other resources look same Master mode. Boot PROM selected external device which drives Boot PROM Address Match (BPAM) input PCnet-ISA+ controller. PCnet-ISA+ controller perform 8-bit accesses from 8-bit Boot PROM presents 16-bits data. shared memory works same way, with external device generating Shared Memory Address Match PCnet-ISA+ controller performing read write 16-bit data conversion. Converting shared memory accesses from 8-bit cycles 16-bit cycles allows much faster 16-bit cycle timing while cutting number cycles half.
This raises performance more than 400% what could achieved with 8-bit cycles. Converting boot PROM accesses 16-bit cycles allows memory resources same Kbyte block memory without clash between devices with different data widths. PCnet-ISA+ controller uses internal address comparator perform SRAM prefetches Private Data Bus; SA0-15 signals used internally determine whether SRAM read cycle prefetch match miss. Access Ethernet controller registers, board configuration registers, Address PROM done with on-chip address comparators. Network Interface PCnet-ISA+ controller connected IEEE 802.3 network network interface ports. Attachment Unit Interface (AUI) provides IEEE 802.3 compliant differential interface remote on-board transceiver. 10BASE-T interface provides twisted-pair Ethernet port. PCnet-ISA+ controller provides three modes network interface 1-505
Am79C961
PRELIMINARY both 10BASE-T interfaces connected, 10BASE-T interface selected over AUI. PCnet-ISA+ controller initialized software selection network interface, will read PORTSEL [1:0] bits Mode register (CSR15.8 CSR15.7) determine which interface needs activated.
A[0-15] Boot PROM
selection: automatic selection, software selection, jumper selection 10BASE-T interface. automatic selection mode, PCnet-ISA+ controller will select interface that connected network checking Link Status state machine.
PRAB(0:15) SD[0-15] 16-Bit System Data SA[0-15] 24-Bit System Address SMAM SHFBUSY BPAM SRWE
BPCS
D[0-7]
PRDB[0-7] PCnet-ISA+ Controller PRDB[2]/EEDO PRDB[1]/EEDI PRDB[0]/EESK EECS SROE
EEPROM
A[0-15] D[0-7] SRAM
BPAM SMAM SA[16] LA[17-23] MEMCS16
SHFBUSY External Glue Logic
18183B-9
Shared Memory Block Diagram Plug Play Compatible
1-506
Am79C961
A[0-15]
D[0-7]
PRAB[0-15] 16-Bit System Data 24-Bit System Address SD[0-15] PCnet-ISA+ Controller SA[0-19]
PRDB[0-7] BPCS SROE PRDB[2]/EEDO PRDB[1]/EEDI PRDB[0]/EESK EECS
Flash
EEPROM
SRWE SHFBUSY SRAM BPAM IRQ12/SRCS A[0-15] SRAM
D[0-7] MEMCS16
BPAM External Glue SRAM Logic SHFBUSY SA[16] LA[17-23]
18183B-10
Shared Memory Block Diagram Plug Play Compatible with Flash Memory Support
PLUG PLAY
Plug Play standardized method configuring jumperless adapter cards system. Plug Play Microsoft standard based central software configuration program, either operating system elsewhere, which responsible configuring Plug Play cards system. Plug Play fully supported PCnet-ISA+ ethernet controller. copy Microsoft Plug Play specification contact Microsoft Inc. This specification should referenced addition PCnet-ISA+ Technical Reference Manual this data sheet.
Operation
PCnet-ISA+ ethernet controller used boot network, device will come active RESET, otherwise will come inactive. Information stored serial EEPROM used identify card describe system resources required card, such space, Memory space, IRQs channels. This information stored standardized Read Only format. Operation Plug Play system shown follows.
Am79C961
1-507
Isolate Plug Play card Read cards resource data Identify card Configure resources
PRELIMINARY either reading READ_DATA PORT writing WRITE_DATA PORT. Once ADDRESS PORT been written, number reads writes occur without having rewrite ADDRESS PORT. ADDRESS PORT also address which initiation written which described later. WRITE_DATA PORT WRITE_DATA PORT address which writes internal Plug Play registers occur. destination data written WRITE_DATA PORT determined last value written ADDRESS PORT. READ_DATA PORT READ_DATA PORT used read information from internal Plug Play registers. register read determined last value ADDRESS PORT. address READ_DATA PORT writing chosen location Plug Play Register isolation protocol determine that address chosen free from conflict with other devices ports.
Plug Play mode operation allows following benefits user.
Eliminates jumpers switches from
adapter card
Ease greatly enhanced Allows ability uniquely address identical
cards system, without conflict
Allows software configuration program
read system resource requirements required card
Defines mechanism modify current
configuration each card
Maintain backward compatability with other
adapters
Auto-Configuration Ports
Three ports used Plug Play configuration software each Plug Play device communicate with Plug Play registers. ports listed table below. software configuration space defined registers. These registers used Plug Play software configuration issue commands, access resource information, check status, configure PCnet-ISA+ controller hardware.
Port Name ADDRESS WRITE-DATA READ-DATA
Initiation
PCnet-ISA+ controller disabled reset when operating Plug Play mode. will respond memory accesses, will PCnet-ISA+ controller drive interrupts channels. initiation places PCnet-ISA+ device into configuration mode. This done writing predefined pattern ADDRESS PORT. proper sequence writes detected PCnet-ISA+ device, Plug Play auto-configuration ports enabled. This sequence must sequential, i.e., other access this port will reset state machine which checking pattern. Interrupts should disabled during this time eliminate extraneous cycles. exact sequence initiation listed below hexadecimal.
Location 0X279 (Printer Status Port) 0xA79 (Printer status port 0x0800) Relocatable range 0x0203-0x03FF
Type Write-only Write-only Read-only
address Write_DATA ports located fixed, predefined addresses. Write_Data port located alias Address port. three auto-configuration ports 12-bit address decode. READ_DATA port relocatable within range 0x203-0x3FF command written WRITE_DATA port. ADDRESS PORT internal Plug Play registers accessed writing address ADDRESS PORT then
Isolation Protocol
simple algorithm used isolate each Plug Play card. This algorithm uses signals requires lock-step operation between Plug Play hardware isolation software.
1-508
Am79C961
State Isolation Read from serial isolation register from serial identifier
CheckSerial Vendor Number Byte Byte Byte Byte Byte Byte Byte Byte Byte
Shift
18183B-12
Shifting Serial Identifier shift order Plug Play serial isolation resource data defined bit[0], bit[1], through bit[7].
"1H"
Drive "55H" SD[7:0]
Leave high-impedance
SD[1:0] "01"
Hardware Protocol
isolation protocol invoked Plug Play software time. initiation key, described earlier, puts cards into configuration mode. hardware each card expects pairs read accesses READ_DATA port. card's response these reads depends value each serial identifier which being examined time sequence shown above. current serial identifier "1", then card will drive data 0x55 complete first read cycle. "0", then card puts data driver into high impedance. cards high impedance will check data during read cycle sense another card driving 1:0] "01". During second read, card(s) that drove 0x55, will drive 0xAA. high impedance cards will check data sense another card driving 1:0] "10". Between pairs Reads, software should wait least high impedance card sensed another card driving data with appropriate data during both cycles, then that card ceases participate current iteration card isolation. Such cards, which lose out, will participate future iterations isolation protocol.
Wait next read from serial isolation register Drive "AAH" SD[7:0] Leave high-impedance After read completes, fetch next from serial identifier Read bits from serial identifier Card Isolated
18183B-11
SD[1:0] "10" other card State Sleep
Plug Play Card Isolation Algorithm
element this mechanism that each card contains unique number, referred serial identifier rest discussion. serial identifier 72-bit unique, non-zero, number composed two, 32-bit fields 8-bit checksum. first 32-bit field vendor identifier. other bits value, example, serial number, part address, static number, long there will never cards single system with same number. serial identifier accessed bit-serially isolation logic used differentiate cards.
NOTE: During each read cycle, Plug Play hardware drives entire 8-bit databus, only checks lower bits. card driving card high impedance sense another card driving bus, then should prepare next pair reads. card shifts serial identifier uses shifted decide response. above sequence repeated entire 72-bit serial identifier.
this process, card remains. This card assigned handle referred Card Select Number (CSN) that will used later select card. Cards which have been assigned will participate subsequent iterations isolation protocol.
Am79C961
1-509
PRELIMINARY There other special considerations software protocol. During iteration, possible that 0x55 0xAA combination never detected. also possible that checksum does match either these cases occur first iteration, must assumed that READ_DATA port conflict. conflict detected, then READ_DATA port relocated. above process repeated until nonconflicting location READ_DATA port found. entire range between 0x203 0x3FF available, however practice expected that only locations will tried before software determines that Plug Play cards present. During subsequent iterations, occurrence either these special cases should interpreted absence further Plug Play cards (i.e. last card found previous iteration). This terminates isolation protocol.
Cards must assigned before they will respond other commands defined specification. should noted that protocol permits 8-bit checksum stored non-volatile memory card generated on-card logic real-time. same LFSR algorithm described initiation section Plug Play specification used checksum generation.
Software Protocol
Plug Play software sends initiation Plug Play cards place them into configuration mode. software then ready perform isolation protocol. Plug Play software generates pairs read cycles from READ_DATA port. software checks data returned from each pair reads 0x55 0xAA driven hardware. both 0x55 0xAA read back, then software assumes that hardware that position. other results assumed "0." During first bits, software generates checksum using received data. checksum compared with checksum read back last bits sequence.
NOTE: software must delay prior starting first pair isolation reads, must wait msec between each subsequent pair isolation reads. This delay gives card time access information from possibly very slow storage devices.
Plug Play Card Control Registers
state transitions card control commands PCnet-ISA+ controller shown following figure.
1-510
Am79C961
Power RESET Reset Command Active Commands
State
Wait active commands
Initiation Active Commands Reset Wait Wake[CSN] (WAKE (Wake CSN)
State
SLEEP
(WAKE (CSN
(WAKE CSN) Lose serial isolation (WAKE CSN) State Active Commands Reset Wait RD_Data Port Serial Isolation Wake[CSN] State Active Commands Reset Wait Wake[CSN] Resource Data Status Logical Device Range Check Activate Configuration Registers
18183B-13
Isolation
Config
Notes Card Select Number RESET Reset command causes state transition from current state Wait sets CSNs zero. Wait command causes state transition from current state Wait Key.
Plug Play Card State Transitions
Plug Play Registers
PCnet-ISA+ controller supports defined Plug Play card control registers. Refer tables following pages detailed information.
Am79C961
1-511
PRELIMINARY Plug Play Standard Registers
Name RD_DATA Port
Address Port Value 0x00
Definition Writing this location modifies address port used reading from Plug Play cards. Bits[7:00] become read port address bits [9:02]. Reads from this register ignored. Address bits 11:10 should read this register causes Plug Play card Isolation state compare board's This process fully described above. This register read only. Bit[0] Reset logical devices restore configuration registers their power-up values. Bit[1] Return Wait state Bit[2] Reset write bit[0] this register performs reset function logical devices. This resets contents configuration registers their default state. card's logical devices enter their default state preserved. write bit[1] this register causes cards enter Wait state CSNs preserved logical devices affected. write bit[2] this register causes cards reset their zero. This register write-only. values sticky, that hardware will automatically clear them there need software clear bits. write this port will cause cards that have that matches write data[7:0] from Sleep state either Isolation state write data this command zero Config state write data zero. This register write-only. Writing this register resets EEPROM pointer beginning Plug Play Data Structure. read from this address reads next byte resource information. Status register must polled until bit[0] before this register read. This register read-only. Bit[0] when indicates okay read next data byte from Resource Data register. This register read-only. write this port sets card's CSN. value uniquely assigned each card after serial identification process that each card individually selected during Wake [CSN] command. This register read/write. Selects current logical device. This register read only. PCnet-ISA+ controller only logical device, this register contains value 0x00
Serial Isolation
0x01
Config Control
0x02
Wake[CSN]
0x03
Resource Data
0x04
Status Card Select Number
0x05 0x06
Logical Device Number
0x07
Plug Play Logical Device Configuration Registers
PCnet-ISA+ controller supports subset defined Plug Play logical device control registers. reason only supporting subset registers
that PCnet-ISA+ controller does require many system resources Plug Play allows. instance, Memory Descriptor used, PCnet-ISA+ controller only requires memory descriptors, Boot PROM/Flash, SRAM Shared Memory Mode.
1-512
Am79C961
PRELIMINARY Plug Play Logical Device Control Registers
Name Activate Address Port Value 0x30 Definition
each logical device there activate register that controls whether logical device active bus. Bit[0], set, activates logical device. Bits[7:1] reserved must zero. This read/write register. Before logical device activated, range check must disabled. This register used perform conflict check port range programmed logical device. Bit[7:2] Reserved 1[1] Enable Range check, then Range Check enabled. range check only valid when logical device inactive. Bit[0], set, forces logical device respond reads logical device's assigned range with 0x55 when range check operation. clear, logical device drives 0xAA. This register read/write.
Range Check
0x31
Memory Space Configuration
Name Memory base address bits[23:16] descriptor Memory base address bits[15:08] descriptor Memory control Register Index 0x40 0x41 0x42 Definition Read/write value indicating selected memory base address bits[23:16] memory descriptor This Boot Prom Space. Read/write value indicating selected memory base address bits[15:08] memory descriptor Bits[2:1] specifies 8/16-bit control. encoding identical memory control (bits[4:3]) information field memory descriptor. Bit[0], indicates next field used range length decode (implies range length base alignment memory descriptor equal). Bit[0] read-only. Read/write value indicating selected memory high address bits[23:16] memory descriptor bit[0] memory control this range length. bit[0] memory control this considered invalid. Read/write value indicating selected memory high address bits[15:08] memory descriptor either memory address range length described above.
Memory upper limit address; bits[23:16] range length; bits[23:16] descriptor Memory upper limit bits[15:08] range length; bits[15:08] descriptor Memory descriptor
0x43
0x44
0x48-0x4C
Memory descriptor This SRAM Space Shared Memory.
Space Configuration
Name port base address bits[15:08] descriptor port base address bits[07:00] descriptor Register Index 0x60 Definition Read/write value indicating selected lower limit address bits[15:08] descriptor logical device indicates only uses encoding, then bits[15:10] need supported. Read/write value indicating selected lower limit address bits[07:00] descriptor
0x61
Am79C961
1-513
PRELIMINARY Interrupt Configuration
Name Interrupt request level select Interrupt request type select
Register Index 0x70
Definition Read/write value indicating selected interrupt level. Bits[3:0] select which interrupt level used Interrupt selects IRQL fifteen selects IRQL fifteen. IRQL valid interrupt selection represents interrupt selection. Read/write value indicating which type interrupt used Request Level selected above. Bit[1] Level, high, Bit[0] Type, level, edge PCnet-ISA+ controller only supports Edge High Level Interrupts.
0x71
Channel Configuration
Name channel select Register Index 0x74 Definition Read/write value indicating selected channels. Bits[2:0] select which channel Zero selects channel seven selects channel channel cascade channel used indicate channel active.
DETAILED FUNCTIONS EEPROM
Interface EEPROM supported PCnet-ISA+ controller industry standard 93C56 2-Kbit EEPROM device which uses 4-wire interface. This device directly interfaces PCnet-ISA+ controller through 4-wire interface which uses private data pins Data Data Out, Serial Clock. Chip Select dedicated from PCnet-ISA+ controller.
This 2-Kbit device organized words. device used PCnet-ISA+ controller below. information stored EEPROM follows:
IEEE address Reserved EISA ISACSRs Plug Play Defaults 8-Bit Checksum External Shift Chain Plug Play Config Info bytes bytes bytes bytes bytes byte bytes bytes
Note: data stored EEPROM stored bitreversal format. Each word bits) must written into EEPROM with swapped with swapped with etc.
1-514
Am79C961
Serial EEPROM Byte
following byte XXC56 series EEPROMs used PCnet-ISA+ Ethernet Controller.
This byte case where non-PCnet Family compatible software driver implemented.
Word Location Byte IEEE Address (Bytes 0-5) Byte Byte Byte Byte Byte Byte Byte EISA Byte EISA Config Reg. EISA Byte MSRDA, ISACSR0 MSWRA, ISACSR1 MISC Config, ISACSR2 Internal Registers LED1 Config, ISACSR5 LED2 Config, ISACSR6 LED3 Config, ISACSR7 0x61 0x71 Unused Plug Play Reg. 0x41 0x43 Unused 0x49 0x4b Unused 8-bit Checksum External Shift Chain 0x60 0x70 0x74 0x40 0x42 0x44 0x48 0x4A 0x4C 0xF0 Byte Byte Byte Byte Byte Byte Byte Byte EISA Byte EISA Byte Unused Locations Appendix Plug Play Starting Location
Note: Checksum calculated words through 0x1Ah (first Bytes).
Am79C961
1-515
PRELIMINARY This byte case where PCnet Family compatible software driver implemented. (This byte application reference developing software devices.)
Serial EEPROM Byte
following byte XXC56 series EEPROMs used PCnet-ISA+ Ethernet Controller.
Word Location EISA Config Reg. Internal Registers Plug Play Reg. Appendix Unused Locations Plug Play Starting Location Appendix 0x61 0x71 Unused 0x41 0x43 Unused 0x49 0x4b Unused 8-bit Checksum Byte Byte Byte Reserved HWID (01H) Byte Byte Byte Reserved Reserved User Space 16-Bit Checksum ASCII 57H) EISA Byte EISA Byte ASCII 57H) EISA Byte EISA Byte MSRDA, ISACSR0 MSWRA, ISACSR1 MISC Config, ISACSR2 LED1 Config, ISACSR5 LED2 Config, ISACSR6 LED3 Config, ISACSR7 0x60 0x70 0x74 0x40 0x42 0x44 0x48 0x4A 0x4C 0xF0 Vendor Byte Memory Ports Interrupts Channels Memory IEEE Address (Bytes 0-5)
External Shift Chain
Note: Checksum calculated words through plus word Checksum calculated words through 0x1Ah (first Bytes).
1-516
Am79C961
Plug Play Register
following chart descriptions show internal configuration registers associated with Plug
Plug Play Register 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x30 0x31 READ_DATA SERIAL_ISOLATION RST_CSN WAIT_KEY RST_ALL WAKE [CSN] READ_STATS RESOURCE_DATA ACTIVATE IORNG
Play operation. These registers control configuration PCnet-ISA+ controller.
READ_DATA SERIAL ISOLATION WAKE [CSN] RESOURCE_DATA IORNG ACTIVATE IORNG READ STATUS WAIT
Address Plug Play READ_DATA Port. Used Serial Isolation process. Resets register zero. Resets Wait State. Resets logical devices. Will wake write data matches Register. Read Status RESOURCE DATA. Next pending byte read from EEPROM. Plug Play Value. Indicates that PCnet-ISA+ device should activated. Bits used enable Range Check Command.
Am79C961
1-517
PRELIMINARY Play operation. These registers control PCnet-ISA+ controller Plug Play operation.
FL_SEL IRQ3 BP_CS IRQ2 DMA2 APROM_EN IRQ1 IRQ_LVL DMA1 BP_16B SR16B AEN_CS IOAM3 IRQ0 IRQ_TYPE DMA0 BPAM3 BPSZ3 SRAM3 SRSZ3 IO_MODE
following chart descriptions show internal command registers associated with Plug
Plug Play Register 0x60 0x61 0x70 0x71 0x74 0x40 0x41 0x42 0x43 0x44 0x48 0x49 0x4A 0x4B 0x4c 0xF0 IOAM2 BPAM2 BPSZ2 SRAM2 SRSZ2 IOAM1 BPAM1 BPSZ1 SRAM1 SRSZ1 IOAM0 BPAM0 BPSZ0 SRAM0 SRSZ0
Plug Play Register Locations Detailed Description (Refer Plug Play Register above.)
IOAM[3:0] Address Address Match bits [8:5] (PnP 0x60-0x61). Controls base address PCnet-ISA+. IOAM will written with value from EEPROM.
Base Address (Hex)
IRQ[3:0]
selection (PnP 0x70). Controls which interrupt will asserted. Edge sensitive EISA level mode controlled IRQ_TYPE 0x71. Default Edge Sensitive. signals will driven unless activate register set.
IRQ3 (Default) IRQ4 IRQ5 IRQ9 IRQ10 IRQ11 IRQ12 IRQ15
IOAM[3:0]
IRQ[3:0]
IRQ_TYPE
IRQ_LVL
Type (PnP 0x71). Indicates type interrupt setting; Level Edge Level (PnP 0x71). readonly register that indicates type setting, active high low. Always complement IRQ_TYPE.
1-518
Am79C961
PRELIMINARY DMA[2:0] Channel Select (PnP 0x74). Controls selection PCnet-ISA+. DMA[2:0] register will written with value from EEPROM. {For Master Mode Only} signal will driven unless EE_VALID Non-EEPROM sequential write process complete.
Channel (DRQ/DACK Pair) Channel Channel Channel Channel BPSZ[3:0] Boot PROM Size Boot PROM Selected
SRAM[3:0]
DMA[2:0]
BPAM[3:0]
Boot PROM Address Match bits [23:16] (PnP 0x40-0x41). Selects location where Boot PROM Address match decode started. BPAM will written with value from EEPROM.
Address Location (Hex) Size Supported bytes)
Static Address Match bits [16:13] (PnP 0x48-0x49). Selects starting location Shared memory using SA[16:13] performing address comparisons. shared memory address match, SMAM asserted low. SRAM[3] value must reflect external address match logic SA[16].
SA[15:13] SRAM Size bytes)
SRAM[2:0]
BPAM[3:0]
C0000 C2000 C4000 C6000 C8000 CA000 CC000 CE000 D0000 D2000 D4000 D6000 D8000 DA000 DC000 DE000
SR_16B
SRSZ[3:0]
Static 16-bit access (PnP 0x4A). Asserted SRAM cycles should respond 16-bit device. Static Size (PnP 0x4B- 0x4C). Selects size static selected.
Shared Memory Size Static Selected
BP_16B
BPSZ[3:0]
Boot PROM 16-bit access (PnP 0x42). asserted Boot PROM cycles should respond 16-bit device. Master mode, boot PROM cycles will only bits width. Boot PROM Size (PnP 0x43-0x44). Selects size boot PROM selected.
SRSZ[3:0]
Vendor Defined Byte (PnP 0x0F)
IO_MODE Mode. When one, internal selection will respond 16-bit port, (i.e. drive IOCS16 pin). When IO_MODE zero, (Default), internal
Am79C961
1-519
PRELIMINARY selection will respond 8-bit port. External Decode Logic Registers. When written with one, PCnet-ISA+ will chip select bar, allow external decode logic upper address [9:5]. purpose this allow locations, supported with IOAM[3:0], selection, defined outside range 0x200-0x3F7. When zero, (Default), Selection will IOAM[3:0]. External Parallel IEEE Address PROM. When set, IRQ15 reconfigured Address Chip Select low, similar APCS existing PCnet-ISA (Am79C960) device. purpose this allow both serial EEPROM parallel PROM coexist. When APROM_EN set, IEEE address located serial EEPROM will ignored parallel access will occur over PRDB bus. When APROM_EN cleared, default state, IEEE address will read from serial device written internal RAM. When space IEEE PROM selected, PCnet-ISA+, will access contents this read cycles. write cycles will ignored. Boot PROM Chip Select. When BP_CS one, BALE will external chip select (active low) above address bus. BALE will select boot PROM when MEMR asserted BP_CS BPAM[2:0] match SA[15:13] BPSZ[3:0] matches selected size. When BP_CS zero. BALE will normal address latch strobe capture upper address bits memory access boot PROM. BP_CS default low. primary purpose this allow non-ISA applications support larger Boot PROMS non-standard Boot PROM/Flash locations. Flash Memory Device Selected. When set, Boot PROM replaced with external Flash memory device. Master Mode, BPCS replaced with Flash_OE. IRQ12 becomes Flash_WE. Flash's grounded. shared memory mode, BPCS replaced with Flash_CS. IRQ12 becomes Static_RAM_CS pin. SROE SRWE signals connected both SRAM Flash memory devices. FL_SEL cleared reset, which default.
AEN_CS
Shared Memory Configuration Bits (Not Defined Master Mode)
Shared Memory Mode, address comparison above 15th must performed external logic. address comparisons 15th below will internal compare logic. SRAM[3:0], SR_16B, SRSZ[3:0] These defined busmaster mode. BP_16B must written with zero bus-master mode. Note: Master Mode, BP_16B always considered 8-bit device. SBHE signal left unconnected, shared memory mode (i.e. 8-bit Slot), memory access will assume 8-bit accesses. responsibility external logic drive MEMCS16 signal appropriate Kbit segment decoded from LA[23:17] signals. MEMCS16 should driven when accessing 8-bit memory resource.
APROM_EN
Checksum Failure
After RESET, PCnet-ISA+ controller begins reading EEPROM storing information registers inside PCnet-ISA+ controller. PCnet-ISA+ controller does checksum word locations 0-1Ah inclusive byte checksum 0FFh, then data read from EEPROM considered good. checksum equal 0FFh, then PCnet-ISA+ controller enters what called software relocatable mode. software relocatable mode, device functions same Plug Play mode, except that does respond same initiation Plug Play supports. Instead, different used bring PCnet-ISA+ controller Wait state. This follows:
BP_CS
FL_SEL
1-520
Am79C961
Without EEPROM
some designs, especially motherboard applications, desirable eliminate EEPROM altogether. This would save money, space, power consumption. operation this mode similar when PCnet-ISA+ controller encounters checksum error, except that enter this mode SHFBUSY left unconnected. device will enter software relocatable mode, BIOS motherboard wake device, configure load IEEE address (possibly stored Flash ROM) into PCnet-ISA+ controller, activate device.
SROE SRWE signals connected both SRAM Flash devices.
Optional IEEE Address PROM
Normally, Ethernet physical address will stored EEPROM with other configuration data. This reduces parts count, board space requirements, power consumption. option standard parallel PROM provided manufactures concerned about non-volatile nature EEPROMs. parallel prom store IEEE address data instead storing EEPROM, APROM_EN Plug Play registers EEPROM upon RESET. IRQ15 redefined setting this APCS, ADDRESS PROM CHIP SELECT. This connected external PROM, such 27LS19. address pins PROM connected lower address pins bus, data lines connected private data bus. this mode, accesses IEEE address will passed external PROM data will passed through PCnet-ISA+ controller system data bus.
External Scan Chain
External Scan Chain bits stored EEPROM which used PCnet-ISA+ controller which used with external hardware allow jumperless configuration external devices. After RESET, PCnet-ISA+ controller begins reading EEPROM storing information registers inside PCnet-ISA+ controller. SHFBUSY held high during read EEPROM. external circuitry added, such shift register, which clocked from SCLK attached from EEPROM, data read EEPROM will shifted into shift register. After reading EEPROM External Shift Chain, there correct checksum, SHFBUSY will low. This will used latch information from EEPROM into shift register. checksum invalid, SHFBUSY will low, indicating that EEPROM bad. more information this function, please refer technical reference manual.
EISA Configuration Registers
PCnet-ISA+ controller support 4-byte EISA Configuration Registers. These used EISA systems identify card load appropriate configuration file that card. This feature enabled using ISACSR2. When EISA Configuration registers will enabled will read location 0xC80-0xC83. contents these registers stored EEPROM automatically read RESET.
Flash PROM
Instead using PROM EPROM Boot PROM, desirable Flash EEPROM type device storing Boot code. This would allow in-system updates changes information Boot without opening also desirable store statistics drivers Flash device.
Interface Unit (BIU)
interface unit mixture state machine asynchronous logic. handles types accesses; accesses where PCnet-ISA+ controller slave accesses where PCnet-ISA+ controller Current Master. slave mode, signals like IOCS16 asserted deasserted soon appropriate inputs received. IOCHRDY asynchronously driven PCnet-ISA+ controller needs wait state. released synchronously when PCnet-ISA+ controller ready. When PCnet-ISA+ controller Current Master, signals generates synchronous onchip clock. Transfers will initiate transfers according type operation being performed. There three primary types transfers: Initialization Block Transfers 1-521
Interface
Flash-type device with PCnet-ISA+ controller, Flash Select register 0F0h Plug Play registers. Flash Select cleared RESET (default). master mode, BPCS becomes Flash_OE IRQ12 becomes Flash_WE. Flash devices connected ground. shared memory mode, BPCS becomes Flash_ IRQ12 becomes static Chip Select,
Am79C961
PRELIMINARY Initialization Block vectored contents CSR1 (least significant bits address) CSR2 (most significant bits address). block contains user defined conditions PCnet-ISA+ controller operation, together with address length information allow linkage transmit receive descriptor rings. There alternative method initialize PCnet-ISA+ controller. Instead initialization initialization block memory, data written directly into appropriate registers. Either method used discretion programmer. registers written directly, INIT must set, initialization block will read thus overwriting previously written information. Please refer Appendix details this alternative method. Reinitialization transmitter receiver section PCnet-ISA+ controller turned initialization block (MODE Register DTX, bits; CSR15[1:0]). state transmitter receiver monitored through CSR0 (RXON, TXON bits). PCnet-ISA+ controller should reinitialized transmitter and/or receiver were turned during original initialization subsequently required activate them, either section shut detection error condition (MERR, UFLO, BUFF error). Reinitialization done initialization block setting STOP CSR0, followed writing CSR15, then setting START CSR0. Note that this form restart will perform same PCnet-ISA+ controller LANCE. particular, PCnet-ISA+ controller reloads transmit receive descriptor pointers with their respective base addresses.This means that software must clear descriptor's bits reset descriptor ring pointers before restart PCnet-ISA controller. reload descriptor base addresses performed LANCE only after initialization, restart LANCE without initialization leaves LANCE pointing same descriptor locations before restart. Buffer Management Buffer management accomplished through message descriptor entries organized ring structures memory. There rings, receive ring transmit ring. size message descriptor entry words bytes). Descriptor Rings Each descriptor ring must organized contiguous area memory. initialization time (setting INIT CSR0), PCnet-ISA+ controller reads user-defined base address transmit receive descriptor rings, which must 8-byte boundary, well number entries contained descriptor rings. default, maximum ring entries permitted when utilizing initialization block, which uses values TLEN RLEN specify transmit
Once been granted mastership, will perform four data transfer cycles (eight bytes) before relinquishing bus. four transfers within mastership period will always read cycles contiguous addresses. There words transfer there will three mastership periods. Descriptor Transfers Once been granted mastership, will perform appropriate number data transfer cycles before relinquishing bus. transfers within mastership period will always same type (either read write), noncontiguous addresses. Only bytes which need read written accessed. Burst-Cycle Transfers Once been granted mastership, will perform series consecutive data transfer cycles before relinquishing bus. Each data transfer will performed sequentially, with issue address, transfer data with appropriate output signals indicate selection active data bytes during transfer. transfers within mastership cycle will either read write cycles, will contiguous addresses. number data transfer cycles within burst dependent programming DMAPLUS option (CSR4, 14). DMAPLUS maximum transfers will performed. This changed writing burst register (CSR80), default takes same amount time Am2100 family LANCE-based boards, little over DMAPLUS burst will continue until FIFO filled high threshold bytes transmit operation) emptied threshold bytes receive operation). exact number transfer cycles this case will dependent latency system BIU's mastership request speed operation.
Buffer Management Unit (BMU)
buffer management unit micro-coded state machine which implements initialization block descriptor architecture. Initialization PCnet-ISA+ controller initialization includes reading initialization block memory obtain operating parameters. initialization block read when INIT CSR0 set. INIT should before concurrent with STRT insure correct operation. Four words time read released each block reads, total three arbitration cycles. Once initialization block been read processed, knows where receive transmit descriptor rings are. completion read operation after internal registers have been updated, IDON will CSR0, interrupt generated IENA set. 1-522
Am79C961
PRELIMINARY receive descriptor ring lengths. However, ring lengths manually defined 65535) writing transmit receive ring length registers (CSR76,78) directly. Each ring entry contains following information:
address actual message data buffer
relinquish ownership write field descriptor entry. device that current owner descriptor entry cannot assume ownership change field entry. Descriptor Ring Access Mechanism initialization, PCnet-ISA+ controller reads base address both transmit receive descriptor rings into CSRs PCnet-ISA+ controller during subsequent operation. When transmit receive functions begin, base address each ring loaded into current descriptor address registers address next descriptor entry transmit receive rings computed loaded into next descriptor address registers.
user host memory
length message buffer Status information indicating condition
buffer Receive descriptor entries similar (but identical) transmit descriptor entries. Both composed four registers, each bits wide total bytes. permit queuing de-queuing message buffers, ownership each buffer allocated either PCnet-ISA+ controller host. within descriptor status information, either (see section RMD), used this purpose. "Deadly Embrace" conditions avoided ownership mechanism. Only owner permitted
Am79C961
1-523
PRELIMINARY
24-Bit Base Address Pointer Initialization Block CSR2 IADR[23:16] CSR1 IADR[15:0]
Descriptor Ring DESCRIPTOR RINGS desc. start
desc. start
RMD0
RMD0 RMD1 RMD2 RMD3
Initialization Block MODE PADR[15:0] PADR[31:16] PADRF[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLEN RDRA[23:16] TDRA[15:0] TLEN TDRA[23:16] Buffers Data Buffer Data Buffer Data Buffer
DESCRIPTOR RINGS Descriptor DESCRIPTOR RINGS Ring desc. start desc. start
TMD0
TMD0 TMD1 TMD2 TMD3
Buffers
Data Buffer
Data Buffer
Data Buffer
18183B-14 16907B-7
Initialization Block Descriptor Rings Polling When there channel activity there pre- post-receive transmit activity being performed PCnet-ISA+ controller then PCnet-ISA+ controller will periodically poll current receive transmit descriptor entries order ascertain their ownership. DPOLL CSR4 set, then transmit polling function disabled. typical polling operation consists following: PCnet-ISA+ controller will current receive descriptor address stored internally vector appropriate Receive Descriptor Table Entry (RDTE). will then current transmit descriptor address (stored internally) vector appropriate Transmit Descriptor Table Entry (TDTE). These accesses will made RMD1 RMD0 current RDTE
1-524
Am79C961
PRELIMINARY TMD1 TMD0 current TDTE periodic polling intervals. information collected during polling activity will stored internally appropriate CSRs. (i.e. CSR18-19, CSR40, CSR20-21, CSR42, CSR50, CSR52). Unowned descriptor status will internally ignored. typical receive poll occurs under following conditions: PCnet-ISA+ controller does possess ownership current RDTE poll time elapsed RXON PCnet-ISA controller does possess ownership next RDTE poll time elapsed RXON RXON PCnet-ISA+ controller will never poll RDTE locations. RXON system should always have least RDTE available possibility receive event. When there only RDTE, there polling next RDTE. typical transmit poll occurs under following conditions: PCnet-ISA+ controller does possess ownership current TDTE DPOLL TXON poll time elapsed, PCnet-ISA+ controller does possess ownership current TDTE DPOLL TXON packet just been received, PCnet-ISA+ controller does possess ownership current TDTE DPOLL TXON packet just been transmitted. poll time interval nominally defined 32,768 crystal clock periods, However, poll time register controlled internally microcode, other microcode controlled operation will interrupt incrementing poll count register. example, when receive packet accepted PCnet-ISA+ controller, device suspends execution polltime-incrementing microcode that receive microcode routine instead executed. Poll-timeincrementing code resumed when receive operation completely finished. Note, however, that following completion receive transmit operation, poll operation will always performed.
poll time count register never reset. Note that nondefault desired, then strict sequence setting INIT CSR0, waiting IDON CSR0, then writing CSR47, then setting STRT CSR0 must observed, otherwise default value will overwritten. CSR47 section details. Setting TDMD CSR0 will cause microcode controller exit poll counting code immediately perform polling operation. RDTE ownership been previously established, then RDTE poll will performed ahead TDTE poll. Transmit Descriptor Table Entry (TDTE) after TDTE access, PCnet-ISA+ controller finds that that TDTE set, then PCnet-ISA+ controller resumes poll time count reexamines same TDTE next expiration poll time count. TDTE set, PCnet-ISA+ controller will immediately request order reset this descriptor; this condition would normally found following LCOL RETRY error that occurred middle transmit packet chain buffers. After resetting this descriptor, PCnet-ISA+ controller will again immediately request order access next TDTE location ring. buffer length will reset. LANCE buffer length interpreted 4096-byte buffer. acceptable have length buffer transmit with acceptable have length buffer with start packet (STP) set, then microcode control proceeds routine that will enable transmit data transfers FIFO. transmit buffers data chained (ENP=0 first buffer), then PCnet-ISA+ controller will look ahead next transmit descriptor after performed least transmit data transfer from first buffer. More than transmit data transfer possibly take place, depending upon state transmitter. transmit descriptor lookahead reads TMD0 first TMD1 second. contents TMD0 TMD1 will stored Next Descriptor Address (CSR32), Next Byte Count (CSR66) Next Status (CSR67) regardless state bit. This transmit descriptor lookahead operation performed only once. PCnet-ISA+ controller does next TDTE (i.e. second TDTE this packet), then will complete transmission current buffer then update status current (first) TDTE with BUFF UFLO bits being set. This will cause transmitter disabled (CSR0, TXON=0). PCnet-ISA+ controller will have restarted restore transmit function. situation that matches this description implies that system been able stay ahead 1-525
Am79C961
PRELIMINARY operation poll avoids inserting poll time counts between successive transmit packets. Whenever PCnet-ISA+ controller completes transmit packet (either with without error) writes status information current descriptor, then TINT CSR0 indicate completion transmission. This causes interrupt signal IENA CSR0 been TINbit CSR3 reset. Receive Descriptor Table Entry (RDTE) PCnet-ISA+ controller does both current next Receive Descriptor Table Entry, then PCnet-ISA+ controller will continue poll according polling sequence described above. receive descriptor ring length there next descriptor, look ahead poll will take place. poll operation revealed that current next RDTE belongs PCnet-ISA+ controller, then additional poll accesses necessary. Future poll operations will include RDTE accesses long PCnet-ISA+ controller retains ownership current next RDTE. When receive activity present channel, PCnet-ISA+ controller waits complete address message arrive. then decides whether accept reject packet based active addressing schemes. packet accepted PCnet-ISA+ controller checks current receive buffer status register CRST (CSR40) determine ownership current buffer. ownership lacking, then PCnet-ISA+ controller will immediately perform (last ditch) poll current RDTE. ownership still denied, then PCnet-ISA+ controller buffer which store incoming message. MISS will CSR0 interrupt will generated IENA (CSR0) MISSM (CSR3). Another poll current RDTE will occur until packet finished. PCnet-ISA+ controller sees that last poll (either normal poll last-ditch effort described above paragraph) current RDTE shows valid ownership, then proceeds poll next RDTE. Following this poll, regardless outcome this poll, transfers receive data from FIFO begin. Regardless ownership second receive descriptor, PCnet-ISA+ controller will continue perform receive data transfers first buffer, using burst-cycle transfers. packet length exceeds length first buffer, PCnet-ISA+ controller does second buffer, ownership current descriptor will passed back system writing zero RMD1 status will written indicating buffer (BUFF possibly overflow (OFLO errors. packet length exceeds length first (current) buffer, PCnet-ISA+ controller does
PCnet-ISA+ controller transmit descriptor ring therefore, condition treated fatal error. avoid this situation, system should always transmit chain descriptor bits reverse order. PCnet-ISA+ controller does second TDTE chain, will gradually empty contents first buffer bytes needed transmit operation), perform single-cycle transfer update status (reset TMD1) first descriptor, then perform data access second buffer chain before executing another lookahead operation. (i.e. lookahead third descriptor.) PCnet-ISA+ controller queue packets transmit FIFO. Call them packet packet "Y", where after "X". Assume that packet currently being transmitted. Because PCnet-ISA+ controller perform lookahead data transfer over ENP, possible PCnet-ISA+ controller update TDTE buffer belonging packet while packet being transmitted packet uses data chaining. This operation will result non-sequential TDTE accesses packet completes transmission PCnet-ISA+ controller writes status, since packet "X"'s TDTE before TDTE accessed part lookahead data transfer from packet "Y". This should cause problem properly written software which processes buffers sequence, waiting ownership before proceeding. error occurs transmission before bytes current buffer have been transferred, then TMD2 TMD1 current buffer will written; that case, data transfers from next buffer will commence. Instead, following TMD2/TMD1 update, PCnet-ISA+ controller will next transmit packet, any, skipping over rest packet which experienced error, including chained buffers. This done returning polling microcode where will immediately access next descriptor find condition described earlier. that case, PCnet-ISA+ controller will reset this descriptor continue like manner until descriptor with OWN=0 more transmit packets ring) (the first buffer packet) reached. transmit operation, whether successful with errors, completion descriptor updates, PCnet-ISA+ controller will always perform another poll operation. described earlier, this poll operation will begin with check current RDTE, unless PCnet-ISA+ controller already owns that descriptor. Then PCnet-ISA+ controller will proceed polling next TDTE. transmit descriptor zero value, then PCnet-ISA+ controller will resume poll time count incrementation. transmit descriptor value ONE, then PCnet-ISA+ controller will begin filling FIFO with transmit data initiate transmission. This end-of1-526
Am79C961
PRELIMINARY second (next) buffer, ownership will passed back system writing zero RMD1 when first buffer full. Receive data transfers second buffer occur before PCnet-ISA+ controller proceeds look ahead ownership third buffer. Such action will depend upon state FIFO when status been updated first descriptor. case, lookahead will performed third buffer information gathered will stored chip, regardless state ownership bit. transmit flow, lookahead operations performed only once. This activity continues until PCnet-ISA+ controller recognizes completion packet (the last byte this receive message been removed from FIFO). PCnet-ISA+ controller will subsequently update current RDTE status with packet (ENP) indication set, write message byte count (MCNT) complete packet into RMD2 overwrite "current" entries CSRs with "next" entries.
APAD_XMT (bit CSR4), transmit messages will padded with sufficient bytes (containing 00h) ensure that receiving station will observe information field (destination address, source address, length/type, data FCS) 64-bytes. When ASTRP_RCV (bit CSR4), receiver will automatically strip bytes from received message observing value length field, stripping excess bytes this value below minimum data size bytes). Both features independently overridden allow illegally short (less than bytes packet data) messages transmitted and/or received. these features reduce bandwidth usage because bytes transferred from host memory.
Media Access Control
Media Access Control engine incorporates essential protocol requirements operation compliant Ethernet/802.3 node, provides interface between FIFO sub-system Manchester Encoder/Decoder (MENDEC). engine fully compliant Section ISO/ 8802-3 (ANSI/IEEE Standard 1990 Second Edition) ANSI/IEEE 802.3 (1985). engine provides programmable enhanced features designed minimize host supervision post-message processing. These features include ability disable retries after collision, dynamic generation packet-by-packet basis, automatic field insertion deletion enforce minimum frame size attributes. primary attributes engine are:
Transmit receive message data encapsulation
Framing (frame boundary delimitation, frame synchronization) engine will autonomously handle construction transmit frame. Once Transmit FIFO been filled predetermined threshold (set XMTSP CSR80), providing access channel currently permitted, engine will commence 7-byte preamble sequence (10101010b, where first transmitted engine will subsequently append Start Frame Delimiter (SFD) byte (10101011b) followed serialized data from Transmit FIFO. Once data been completed, engine will append (most significant first) which computed entire data portion message.
Note that user responsible correct ordering content each fields frame, including destination address, source address, length/type packet data. receive section engine will detect incoming preamble sequence lock encoded clock. internal MENDEC will decode serial stream present this engine. will discard first bits information before searching sequence. Once detected, subsequent bits treated part frame. engine will inspect length field ensure minimum frame size, strip unnecessary characters enabled), pass remaining bytes through Receive FIFO host. stripping performed, engine will also strip received bytes, although normal computation checking will occur. Note that apart from stripping, frame will passed unmodified host. length field value greater, engine will attempt validate length against number bytes contained message. frame terminates suffers collision before bytes information (after SFD) have been received, engine will automatically delete frame from Receive FIFO, without host intervention.
Framing (frame boundary delimitation, frame synchronization) Addressing (source destination address handling) Error detection (physical medium transmission errors) Media access management Medium allocation (collision avoidance) Contention resolution (collision handling) Transmit Receive Message Data Encapsulation engine provides minimum frame size enforcement transmit receive packets. When
Am79C961
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PRELIMINARY will ignore seven additional bits message (dribbling bits), which occur under normal network operating conditions. reception eight additional bits will cause engine de-serialize entire byte, will result received message being modified. PCnet-ISA+ controller handle dribbling bits when received packet terminates. During reception, generated every serial (including dribbling bits) coming from cable, although internally saved value only updated eighth each byte boundary). framing error reported user follows: number dribbling bits there error, then there Framing error (FRAM number dribbling bits less than there error, then there also Framing error (FRAM number dribbling bits then there Framing error. There (FCS) error. Counters provided report Receive Collision Count Runt Packet Count used network statistics utilization calculations. Note that engine detects received packet which pattern preamble (after first bits, which ignored), entire packet will ignored. engine will wait network inactive before attempting receive next packet. Media Access Management basic requirement stations network provide fairness channel allocation. 802.3/Ethernet protocol defines media access mechanism which permits stations access channel with equality. node attempt contend channel waiting predetermined time (Inter Packet interval) after last activity, before transmitting medium. channel multidrop communications medium (with various topological configurations permitted) which allows single station transmit other stations receive. nodes simultaneously contend channel, their signals will interact, causing loss data (defined collision). responsibility attempt avoid recover from collision, guarantee data integrity end-to-end transmission receiving station.
Addressing (source destination address handling) first bytes information after will interpreted destination address field. engine provides facilities physical, logical, broadcast address reception. addition, multiple physical addresses constructed (perfect address filtering) using external logic conjunction with EADIinterface. Error detection (physical medium transmission errors). engine provides several facilities which report recover from errors medium. addition, network protected from gross errors inability host keep pace with engine activity.
completion transmission, following transmit status available appropriate areas:
exact number transmission retry attempts
(ONE, MORE, RTRY).
Whether engine Defer (DEF)
channel activity.
Loss Carrier, indicating that there
interruption ability engine monitor transmission. Repeated LCAR errors indicate potentially faulty transceiver network connection.
Late Collision (LCOL) indicates that
transmission suffered collision after slot time. This indicative badly configured network. Late collisions should occur normal operating network.
Collision Error (CERR) indicates that
transceiver respond with Test message within predetermined time after transmission completed. This failed transceiver, disconnected faulty transceiver drop cable, fact transceiver does support this feature feature disabled). addition reporting network errors, engine will also attempt prevent creation network error inability host service engine. During transmission, host fails keep Transmit FIFO filled sufficiently, causing underflow, engine will guarantee message either sent runt packet (which will deleted receiving station) invalid (which will also cause receiver reject message). status each receive message available appropriate areas. Framing errors (FRAM) reported, although received frame still passed host. FRAM error will only reported error detected there nonintegral number bits message. engine
Medium allocation (collision avoidance) IEEE 802.3 Standard (ISO/IEC 8802-3 1990) requires that CSMA/CD monitor medium traffic looking carrier activity. When carrier detected medium considered busy, should defer existing message.
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Am79C961
PRELIMINARY IEEE 802.3 Standard also allows optional part deferral after receive message.
ANSI/IEEE 802.3-1990 Edition, 4.2.3.2.1: "Note: possible carrier sense indication fail asserted during collision media. deference process simply times interpacket based this indication possible short interFrame generated, leading potential reception failure subsequent frame. enhance system robustness following optional measures, specified 4.2.8, recommended when InterFrameSpacingPart1 other than zero: Upon completing transmission, start timing interpacket gap, soon transmitting carrierSense both false. When timing interpacket following reception, reset interpacket timing carrier Sense becomes true during first interpacket timing interval. During final interval timer shall reset ensure fair access medium. initial period shorter than interval permissible including zero." engine implements optional receive part deferral algorithm, with first part inter-frame-spacing time second part inter-frame-spacing interval therefore
PCnet-ISA+ controller will perform two-part deferral algorithm specified Section 4.2.8 (Process Deference). Inter Packet (IPG) timer will start timing InterFrameSpacing after receive carrier de-asserted. During first part deferral (InterFrameSpacingPart1 IFS1) PCnet-ISA+ controller will defer pending transmit frame respond receive message. counter will reset zero continuously until carrier de-asserts, which point counter will resume count once again. Once IFS1 period elapsed, PCnet-ISA+ controller will begin timing second part deferral (InterFrameSpacingPart2 IFS2) Once IFS1 completed, IFS2 commenced, PCnet-ISA+ controller will defer receive packet transmit packet pending. This means that PCnet-ISA+ controller will attempt receive receive packet, since will start transmit, generate collision PCnet-ISA+ controller will guarantee complete preamble (64-bit) (32-bit) sequence before ceasing transmission invoking random backoff algorithm. addition, transmit part deferral implemented option which disabled using DXMT2PD (CSR3). Two-part deferral after transmission useful ensuring that severe shrinkage cannot occur specific circumstances, causing transmit message follow receive message closely make them indistinguishable.
During time period immediately after transmission been completed, external transceiver case standard connected device), should generate Test message nominal burst 5-15 times duration) pair (within after transmission ceases). During time period which Test message expected PCnet-ISA+ controller will respond receive carrier sense.
ANSI/IEEE 802.3-1990 Edition, 7.2.4.6 (1)): conclusion output function, opens time window during which expects signal_quality_error signal asserted Control circuit. time window begins when CARRIER_STATUS becomes CARRIER_OFF. execution output function does cause CARRIER_ON occur, test occurs DTE. duration window shall least more than During time window Carrier Sense Function inhibited."
PCnet-ISA+ controller implements carrier sense "blinding" period within from de-assertion carrier sense after transmission. This effectively means that when transmit part deferral enabled (DXMT2PD cleared) IFS1 time from after transmission. However, since shrinkage below will rarely encountered correctly configured network, since fragment size will larger than blinding window, then counter will reset worst case shrinkage/fragment scenario PCnet-ISA+ controller will defer transmission. addition, PCnet-ISA+ controller will restart "blinding" period carrier detected within IFS1 period, will commence timing entire IFS1 period.
Contention resolution (collision handling) Collision detection performed reported engine integrated Manchester Encoder/ Decoder (MENDEC).
collision detected before complete preamble/ sequence been transmitted, Engine will complete preamble/SFD before appending sequence. collision detected after preamble/SFD been completed, prior bits being transmitted, Engine will abort transmission, append sequence immediately. sequence 32-bit zeroes pattern. Engine will attempt transmit frame total times (initial attempt plus retries) normal collisions (those within slot time). Detection collision will cause transmission re-scheduled, dependent backoff time that Engine computes. single retry required, will Transmit Frame Status (TMD1 Transmit Descriptor Ring). more than retry
Am79C961
1-529
PRELIMINARY External Crystal Characteristics When using crystal drive oscillator, crystal specification shown specification table used ensure less than ±0.5 jitter DO±. External Crystal Characteristics
Parameter 1.Parallel Resonant Frequency 2.Resonant Frequency Error 3.Change Resonant Frequency With Respect Temperature pF)* 4.Crystal Capacitance 5.Motional Crystal Capacitance (C1) 6.Series Resistance 7.Shunt Capacitance 8.Drive Level 0.022 Unit
required, MORE will set. attempts experienced collisions, RTRY TMD2) will (ONE MORE will clear), transmit message will flushed from FIFO. retries have been disabled setting DRTY MODE register (CSR15), Engine will abandon transmission frame detection first collision. this case, only RTRY will transmit message will flushed from FIFO. collision detected after times have been transmitted, collision termed late collision. Engine will abort transmission, append sequence, LCOL bit. retry attempt will scheduled detection late collision, FIFO will flushed. IEEE 802.3 Standard requires "truncated binary exponential backoff" algorithm which provides controlled pseudo-random mechanism enforce collision backoff interval, before re-transmission attempted.
ANSI/IEEE 802.3-1990 Edition, 4.2.3.2.5: enforcing collision (jamming), CSMA/CD sublayer delays before attempting re-transmit frame. delay integer multiple slotTime. number slot times delay before re-transmission attempt chosen uniformly distributed random integer range:
where (n,10)." PCnet-ISA controller provides alternative algorithm, which suspends counting slot time/IPG during time that receive carrier sense detected. This algorithm aids networks where large numbers nodes present, numerous nodes collision. algorithm effectively accelerates increase backoff time busy networks, allows nodes involved collision access channel while colliding nodes await reduction channel activity. Once channel activity reduced, nodes resolving collision time their slot time counters normal.
Requires trimming crystal spec; trim total
External Clock Drive Characteristics When driving oscillator from external clock source, XTAL2 must left floating (unconnected). external clock having following characteristics must used ensure less than ±0.5 jitter DO±.
Clock Frequency: Rise/Fall Time (tR/tF): XTAL1 HIGH/LOW Time (tHIGH/tLOW): XTAL1 Falling Edge Falling Edge Jitter: ±0.01% from VDD-0.5 duty cycle ±0.2 input (VDD/2)
MENDEC Transmit Path transmit section encodes separate clock data input signals into standard Manchester encoded serial stream. transmit outputs (DO±) designed operate into terminated transmission lines. When operating into terminated transmission line, transmit signaling meets required output levels skew Cheapernet, Ethernet, IEEE-802.3. Transmitter Timing Operation fundamental-mode crystal oscillator provides basic timing reference MENDEC portion PCnet-ISA+ controller. crystal input divided create internal transmit clock reference. Both clocks into Manchester Encoder generate transitions encoded data stream. internal transmit clock used MENDEC internally synchronize Internal Transmit Data (ITXDAT) from
Manchester Encoder/Decoder (MENDEC)
integrated Manchester Encoder/Decoder provides (Physical
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