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Design Considerations Am79761 Gigabit Ethernet Physical Layer GigaPHYTM-SD Device
This document intended assist customers using AMD's Gigabit Ethernet Physical Layer devices. Details concerning application information, circuit design, layout, component selection provided help ensure first-pass success implementing functional design which optimized signal quality.
This document applicable Am79761 GigaPHY-SD product. This document should used conjunction with product data sheet. elementary knowledge Ethernet high speed printed circuit layout techniques assumed. Contact your local Field Applications Engineer Sales Office discuss questions concerns have.
present inputs (GigaPHY-SD Encoder/ Decoder), that proper phase relationship maintained between GigaPHY-SD device Encoder/Decoder chip, since GigaPHY-SD device latches data rising edge this clock. GigaPHY-SD device provides input buffer which does support AC-coupling REFCLK signal. Although oscillators provide cleanest source REFCLK, oscillators over often cost more than acceptable specific design. this case, customers have used clock generator chips provide REFCLK lower cost than oscillator. Unfortunately, cost reduction accompanied significant increase REFCLK jitter, which adds jitter transmitted serial data resulting reduction maximum transmission distance. Another configuration generate REFCLK Encoder/Decoder chip. This desirable where REFCLK used latch incoming transmit data, since easier meet setup/hold time requirements transmitter, especially when using 10-bit interface MHz. When oscillator drives REFCLK Encoder/Decoder chip, clock-tooutput delay Encoder/Decoder chip impacts setup/hold time data with respect REFCLK. When Encoder/Decoder chip generates REFCLK, output buffer REFCLK output latch transmit data track each other thereby increase setup time. However, penalty this scheme increased jitter added Encoder/Decoder chip REFCLK. configurations REFCLK generation shown Figure Where possible, recommended oscillator drive both Encoder/Decoder chip GigaPHYSD device order provide cleanest REFCLK.
CLOCK GENERATION
most important aspects design generation REFCLK signal. This input provides reference clock internal which multiplied generate baud rate clock.The rising edge REFCLK continuously phase compared internal baud rate clock that will speed slow down order keep these signals aligned. therefore important that REFCLK jitter-free possible order minimize jitter introduced into baud rate clock. also desirable have fast rising edges this clock minimize time which signal transitions from level HIGH level. fast edge will reduce edge-detection ambiguity input buffer therefore reduce jitter PLL.
Note: rising edge this clock also latches data transmit into input latch care must taken ensure that transmit data meets setup hold time requirements transmitter.
most desirable solution generating REFCLK have crystal oscillator drive input Encoder/Decoder that interfaces GigaPHY-SD device. some cases, this oscillator will also have drive clock input Encoder/Decoder. Care must taken ensure that good quality signals
This document contains information product under development Advanced Micro Devices. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
Publication# 21582 Rev: Amendment/0 Issue Date: 1998
Refer AMD's Website (www.amd.com) latest information.
Encoder/Decoder Output Latch REFCLK
GigaPHY-SD Input Register
Encoder/Decoder Output Latch
GigaPHY-SD Input Register
REFCLK
±100 Oscillator
Less Jitter Worse Setup/Hold Time
±100 Oscillator
More Jitter Better Setup/Hold Time
21582B-1
Figure
Common REFCLK versus Separate REFCLK receiver inputs (RX±) differential PECL inputs which include resistor dividers bias point input (usually VDD/2). Normally, user supplies resistors terminate transmission line minimize reflections. AC-coupling capacitor provided isolate PECL input from transmission line input buffer bias point. Lastly, mechanism added provide offset, that input open, input buffer will oscillate. following sections describe designs various termination schemes which provide some, certainly all, options open user.
HIGH SPEED SIGNAL TERMINATION
differential high speed outputs transmitter (TX+ TX-) PECL outputs, which require unique termination ensure proper operation optimize signal quality. Since these signals clocked 1.25 transmit 8B/10B encoded data, they carry digital signals between MHz. Careful design layout terminations traces required maximize transmission distance minimize signal degradation. multiple media choices further complicate these circuits. purposes this discussion, four applications will described both transmitter outputs (TX±) receiver inputs (RX±): Single-Ended/Differential Coaxial Cable using connectors test equipment connectivity. Single Ended, Coaxial Cable using BNC/TNC connectors Fibre Channel Gigabit Ethernet compatibility Differential, 150- Duplex Twinax Cable using connectors Fibre Channel Gigabit Ethernet compatibility. Fiber Optic Module interface 50-. transmitter outputs (TX±) PECL outputs which capable sourcing current sinking Therefore pull-down resistor (traditionally required drive output when output turned off. resistance this pulldown determined parametrics part impedance signal trace. Since -2.0 usually present system, output should terminated ground (VSS) convenience. Also, PECL outputs conform input levels, therefore, high speed should AC-coupled eliminate mismatches signal levels.
Single-Ended, Termination
This application ideal connecting test equipment such oscilloscopes BERTs does conform Gigabit Ethernet specification. transmitter outputs, 182- pull-down resistor located near device order pull signal level when output turned off. value used with impedance traces/cables. AC-coupling capacitor (usually 0.01 added series eliminate component output signal allowing general-purpose connectivity. receiver inputs, 51.1- line termination resistor provided match impedance trace coaxial cable reduce reflections optimize signal quality. AC-coupling capacitor added series allow input buffer establish optimal DC-level provided internal resistor dividers. This will restore signal levels meet input requirements high speed buffer. unused receiver input ACcoupled ground reduce noise susceptibility, keeps input internal bias point. coaxial cable would normally connected using connectors ease with test equipment. shells connectors grounded. typical circuit this application shown Figure
Design Considerations Am79761 Gigabit Ethernet Physical Layer GigaPHYTM-SD Device
Coax
R1=R2=182 C1=C2=C3=C4=0.01
R3=51.1
21582B-2
Figure
Termination Example: Single-Ended Ethernet. connector transmit side (female board, male cable). connector receive side (female board, male cable). shell grounded, shell left open. These mismatched connectors provide built-in polarization. typical circuit this application shown Figure
Single-Ended, Termination
This Gigabit Ethernet-compatible application which similar previous example. However, this example, pull down resistors R1=R2=267 instead match transmission lines. Also, coaxial cabling connectors different order meet impedance required Gigabit
(Female)
(Female)
Coax
R1=R2=267 C1=C2=C3=C4=0.01
R3=75
21582B-3
Figure
Termination Example: Single-Ended receiver side AC-coupling capacitors since this resistor will affect bias circuit. connector this application 9-pin D-Subminiature (female board, male cable) with shield cable connected chassis ground both ends provide impedance grounded shield. cost-effective duplex twinax cable having effective shielding scheme that reduces emissions point that systems pass FCC-B CISPR levels available from Gore. typical circuit this application shown Figure
Differential, 150- Twinax Termination
more popular Gigabit Ethernet-compatible application 150- differential signals using 9-pin DSubminiature connectors (also known DB-9) duplex twinax cable. This provides better signal quality, longer transmission distance, reduced emissions compared single-ended configurations. Both outputs from transmitter terminated with 267- pull downs. percent components used maintain balanced load between differential outputs. receive side, single 150- line termination resistor used impedance matching. This located
Design Considerations Am79761 Gigabit Ethernet Physical Layer GigaPHYTM-SD Device
DB-9
DB-9 150- Twinax
R1=R2=267 C1=C2=C3=C4=0.01
R3=150
21582B-4
Figure
Termination Example: 150- Differential which interfaces Finisar's FTR-8510 Methode's MTR-8510 transceiver module described. AC-coupling capacitors required transmit side, only 180- pull-down resistors provided. This application example assumes short traces (less than inches), that termination resistors required traces transmit side. receive side, normal 51.1- AC-coupling capacitor provided. This illustrated Figure
Fiber Optic Module Termination
Many customers wish Gigabit Ethernet over fiber optic cable increased distance, reduced EMI, other reasons. general, this application. However, each vendor fiber optic transceivers have slightly unique interfacing requirements, recommended that user contact vendor prior design. purposes this example, circuit
Module
R1=R2=182 C1=C2 0.01
R4=51.1
21582B-5
Figure
Termination Example: Fiber Optic Transceiver input jitter seen receiver. example this shown Figure with values both impedance applications.
PREVENTING OSCILLATIONS
Since link disconnected transmitter disabled, there times when receiver's inputs might carry valid signal. absence signal, both inputs receiver (RX±) will their internally determined bias points which are, design, identical. When differential input buffer's inputs identical, buffer susceptible oscillations which could cause noise within receiver. AMD's input buffers oscillate normally; however, noisy environment oscillations occur. prevent this problem, Thevenin-equivalent resistor pair used both terminate transmission line provide small offset receiver. This offset kept possible introduce offset under normal conditions, which might
Unused Inputs
many applications receiver inputs might used. this situation, important terminate inputs that they will oscillate. single-ended application, unused receiver input AC-coupled ground reduce noise susceptibility, input internal bias point kept. differential inputs used, then circuit shown below recommended. variety useful circuits used this purpose, considerations follows: provide DC-offset provide low-impedance noise attenuation path.
Design Considerations Am79761 Gigabit Ethernet Physical Layer GigaPHYTM-SD Device
21582B-6
R1=R4=97.6 R2=R3=102 impedance, offset] R1=R4=147 R2=R3=154 impedance, offset] C1=C2=0.01
Figure
Termination Example: Preventing Oscillation advantage linear regulator that provides very quiet output that isolated from noise supply. Since signal jitter sensitive power supply noise, clean outputs linear regulator contribute improved signal quality. readily available, multiple-sourced linear regulator Linear Technology LT1086CM-3.3, which fixed output voltage regulator that provides output current. This more than adequate power GigaPHY-SD device. simple application circuit shown Figure Minimum values input output capacitance required provide stability regulator. Additional bypass capacitors must added additional power supply filtering pins chip. Similar linear regulators with different current limits LT1117CST-3.3 (800 SOT223) LT1586CM-3.3 (4A, TO-220), both from Linear Technology.
21582B-7
circuit shown Figure external resistors added parallel with internal pair. This results 50-mV offset. capacitor across inputs provides low-impedance path reduce noise susceptibility.
R1=R2=47K C1=0.01
Generating from DC/DC Converter
limitation linear regulator that efficient, therefore, heat generated. applications where excessive heat acceptable, DC/DC Converter used convert either supplies into supply. DC/DC converters available current levels needed this application have excellent efficiency, between 95%, which reduces heat generation. However, DC/DC converters more expensive, require more real estate, require more components, trivial use, noise supply. noise concern since power supply noise will couple into circuits buffers transmitter receiver, thereby, increasing jitter generation transmitter reducing jitter tolerance receiver. DC/DC converter used, extra care should taken reduce output noise.
Figure
Termination Example: Unused Inputs
POWER SUPPLY CONSIDERATIONS Generating from Linear Regulator
AMD's Gigabit Ethernet PHYs operate with power supply. Although migration logic power supplies underway, many systems have available supply. easiest, smallest, cheapest convert from power supply level through linear regulator. Converting from supply supply more difficult additional power dissipation regulator that must handled correctly. 10%, power dissipated regulator calculated (5.25 V)*IDD(max).
Design Considerations Am79761 Gigabit Ethernet Physical Layer GigaPHYTM-SD Device
LT1086 CM-3.3
21582B-8
Figure
Conversion using Linear Regulator between plane. preferred method layout bypassing capacitors shown Figure Since AMD's GigaPHY-SD device roughly constant power supply current, there need exotic bypassing methods (i.e., capacitors parallel aimed switching frequency internal circuit). also recommended that power ground planes remain intact rather than attempting steer current paths through sculpted planes. Most customers have tried isolate planes transmitters receivers usually produce more noise, rather than reduce noise. GigaPHY-SD internal PLLs which powered from separate supply pins usually called AVDD/AVSS where denotes analog. These pins particularly sensitive noise, additional care must taken filter noise. recommended that AVDD pass through ferrite bead (i.e., CB50-1206) bypass capacitor least power pin. layout shown Figure indicates preferred method layout this circuit.
DC/DC Converter that appropriate powering GigaPHY-SD device Linear Technology, LT1256 1.5A part. DC/DC converter circuit shown here since excellent application notes provided manufacturer.
BYPASSING
method which bypass capacitors used filter power supply GigaPHY-SD device significant impact upon signal quality. First, mandatory that design include power plane (Ground) which least copper. Secondly, similar power plane (3.3 strongly recommended. reduce inductance, vias used connect these planes should include thermal cut-outs similar those found VDD/VSS connections throughhole components. strongly suggested that each power ground supplied from their vias. Bypass capacitors more effective when located same side GigaPHY-SD device. course, capacitors must located closely possible pins chips. Furthermore, recommended that capacitor located
Ferrite CB50 -1206
0805
0805
DVSS
DVDD GigaPHY_SD
AVDD
AVSS
21582B-9
Figure
Bypassing Layout Example
Design Considerations Am79761 Gigabit Ethernet Physical Layer GigaPHYTM-SD Device
LAYOUT CONSIDERATIONS
When implementing 1-Gbps serial communications link, importance layout cannot overstressed. However, following general, simple-to-use guidelines will ensure success prove easier than most designers anticipate. prioritization signals follows: High speed serial lines REFCLK traces Power supplies bypass capacitors Control signals Data busses Careful placement components passives both bottom sides will generally ensure optimal layout. mentioned previously, solid ground power plane quite useful distributing clean power.
Eliminate reduce stub lengths. Reduce, eliminate, vias minimize impedance discontinuities. rounded corners rather than corners. Keep signal traces from other signals which might capacitively couple noise into signals. This includes other trace differential pair. route digital signals from other circuits across area transmitter receiver. power ground planes effort steer current paths. This usually produces more noise, less.
REFCLK Layout
most difficult issue with regard REFCLK that signal goes multiple inputs which require extremely clean clock with fast edges. This becomes clock distribution challenge. course, from emissions point view, goal eliminate high-frequency monics order reduce radiated emissions. Therefore, system developer have contradictory goals requiring compromise position.
High Speed Serial Layout
These signals contain digital data frequencies between require excellent frequency phase response least harmonic, harmonic. Improved signal quality longer practical transmission distances will result when designer follows general rules below: Keep traces short possible. Initial component placement should very carefully considered. impedance traces must match that termination resistors, connectors, cable order reduce reflections impedance mismatches. Impedance matching termination resistors (i.e., 51.1 should located close possible input receiver minimize stub length. Since AC-coupling capacitor often inserted between termination resistor, this sometimes difficult optimize. Differential impedance must maintained 150- differential application. Routing traces adequate. traces must separated enough distance maintain 150- differential impedance. good rule thumb that trace separation should least times trace width. When routing differential pairs, keep trace length identical between traces. Differences trace lengths translate directly into signal skew. When separations occur, differential impedance affected take care when this done. Keep differential pair traces same side minimize impedance discontinuities. Place impedance discontinuities close transmitter receiver locate them together. This will minimize their impact signal quality.
Power Supply Layout
These issues have been discussed previously will detailed here. Vias used connect power planes DVDD DVSS pins chips should least 0.010 inches diameter, preferably with thermal relief plated closed with copper solder. Also, should located opposite side bypass capacitor from pin.
Control Signal Layout
There time-critical control signals GigaPHY-SD device. However, important route control lines chips such avoid crosstalk noise injection.
Data Layout
problem with data busses that there signals small area. only consideration here keep traces roughly same length clock used latch them, that trace length differences reduce setup/hold times chips.
CONCLUSION
Following general guidelines described this design guide will help ensure that customers integrating Gigabit Ethernet components experience first-time success. Contact your local Field Applications Engineer will happy work with customers promote success their designs, including providing schematic layout reviews.
Design Considerations Am79761 Gigabit Ethernet Physical Layer GigaPHYTM-SD Device
COMPONENT SUPPLIER LIST
following table list vendors supply components interest Gigabit Ethernet customers. Where applicable, part number description
have been provided components required specific applications.
Component Supplier List Copper Cable Assemblies Berg Trompeter Electronics Gore Connectors Johnson Fiber Optic Modules AMP/Lytel Finisar Force Electronics Fujikura Technology Methode Electronics Fiber Optic Cable Fiber Optics Alcoa/Fujikura Methode Electronics Magnetics Coilcraft Technitrol Oscillators Connor-Winfield Motorola Semiconductor Pletronics Saronix Valpey Fisher Clock Generators Works (408) 922-0202 Clock Synthesizer (708) 851-4722 (888) GET-2FOX (800) 441-2447 (206) 776-1880 (415) 856-6900 (508) 435-6831 X607 PLLs Clock Distribution variety oscillators, spectrum analyzers, etc. (800) 322-2654 (215) 426-9105 Transformers Line interfacing Active Passive Equalizer/Buffers (908)544-9119 (800)866-3953 (800)323-6858 (800) 52A-MP52 (407) 984-3671 (415) 691-4000 (703) 382-0462 (408) 748-6991 (708) 867-9600 Modules Transmitter Receiver Gbps Modules FTR-8510 2684T Transmitter 2684R Receiver Modules Gbps transceivers MTR-8510. (800) 52A-MP52 (800) 247-8256 Coax, DB-9 Fibre Channel specific (HSSDC) connectors. Coaxial connectors (800) 52A-MP52 (717) 764-7200 (818) 707-2020 (302) 368-2575 High Frequency Coax, Twinax Quad Cable Assemblies Cable Assemblies Coaxial Cable Assemblies Quad Cable, FCN1008-xx, where distance meters
Trademarks Copyright 1998 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof trademarks Advanced Micro Devices, Inc. GigaPHY trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
Design Considerations Am79761 Gigabit Ethernet Physical Layer GigaPHYTM-SD Device

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