Semiconductor MSM9000B-xx MATRIX CONTROLLER This version: No
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E2B0041-27-Y3 Semiconductor
Semiconductor MSM9000B-xx
MATRIX CONTROLLER
This version: Nov. 1997 MSM9000B-xx Previous version: Mar. 1996
GENERAL DESCRIPTION
MSM9000B-xx dot-matrix control driver which functions displaying dots) characters lines) 120-dot arbitrators. MSM9000B-xx provided with 16-dot common driver, 60-dot segment driver, Display Data (DDRAM), Character Generator (CGROM). This device controlled with commands entered through serial interface parallel interface. font data CGROM changed mask option. Since MSM9000B-xx driving bias generator circuit, bias voltages obtained merely providing required capacitance externally. MSM9000B-xx applicable variety panels controlling contrast.
FEATURES
Logic voltage(VDD): driving voltage(VBI) current consumption: max.(operating) Switchable between 8-bit serial interface 8-bit parallel interface Contains 16-dot common driver 60-dot segment driver Contains CGROM with character fonts dots) Built-in bias voltage generator circuit Built-in contrast adjusting circuit Built-in 32.768 crystal oscillator circuit Provided with arbitrators duty mode line characters, lines arbitrators) 1/16 duty mode lines characters, lines arbitrators) Character blink operation switched between all-character lighting-on mode allcharacter lighting-off mode. Package: mounting with wide film Tin-plated (Product name MSM9000B-xx AV-Z-xx) Chip (Product name MSM9000B-xx) indicates code number.
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Semiconductor
MSM9000B-xx
BLOCK DIAGRAM
C1-C16 Common Regulator Halver Voltage Multiplier(4-fold) Latch Shift Register VSS6 VCC1 Gate bias Driver S1-S60 Segment Driver
VSS1 VSS2, VSS4 VSS5 VCC2
Voltage Multiplier (3/2-fold)
Display Data (DDRAM) (456 Bits)
Character Generator (CGROM) (256 Dots)
32K/EXT 9D/16D RESET TEST
Crystal Circuit
Timing Circuit
Registers
Interface DB7-0
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MSM9000B-xx
CONFIGURATION
RESET 32K/EXT 9D/16D TEST VCC1 VSS6 VCC2 VSS1 VSS2, VSS4 VSS5
COM1
COM8 SEG1 SEG2
SEG59 SEG60 COM16
COM9
Configuration Viewed From Pattern
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Semiconductor
MSM9000B-xx
DESCRIPTIONS
Number Pins
Function Interface
Symbol DB0-7
Type
Description Chip select input signal Write enable signal, latch serial interface Read enable signal Command/Data select input signal 8-bit parallel data inputs/outputs Serial data input Serial data output Shift clock input data input serial interface mode Crystal oscillation input, clock input Crystal oscillation output Parallel/Serial interface switching signal input Duty select signal input Clock select signal input Reset performed setting RESET input level Contrast control signal input Test signal input. Level leave open Segment outputs driving Common outputs driving Positive power supply LOGIC Boosted voltage output pins bias power supply pins Voltage multiplier output (3-/2-fold) Haver output Voltage multiplier (3-/2-fold) Voltage multiplier (4-fold)
Oscillation Control Signal
9D/16D 32K/EXT RESET TEST
Driving Output Power Supply
SEG1-SEG60 COM1-COM16 VSS1, VSS2, VSS4, VSS5 VSS6 VC1, VCC1 VC2, VCC2 Total
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ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Bias voltage Input voltage Storage temperature Symbol TSTG Condition Ta=25°C, VDD-VSS Ta=25°C, VDD-VSS5 Ta=25°C Chip Rating -0.3 +4.6 -0.3 -0.3 +150 Unit Applicable VDD, VDD, VSS5 input pins
Ambient temperature
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Bias voltage source oscillation Operating temperature Symbol fint Condition VDD-VSS VDD-VSS5 Range Unit Applicable VDD, VDD, VSS5
highest VSS5 lowest bias voltage. Connect specified capacitors voltage doubler bias generator. Make sure that crystal oscillation frequency divided clock frequency falls within this range. Note Ensure chip exposed light. Note bias voltage exceed some contrast stages. Adjust stage with software that bias voltage does exceed
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ELECTRICAL CHARACTERISTICS
Characteristics
(VDD +85°C) Parameter Input high voltage Input high voltage Input voltage Input voltage Input high current Input high current Input current leakage current Output high voltage Output voltage output resistance output resistance Drain current Symbol VIH1 VIH2 VIL1 VIL2 IIH1 IIH2 IIL1 Ioff VOL1 IDD1 Condition VI=VDD VI=VDD VI=0 VI=VDD/0 IO=-500 IO=500 IO=±50 IO=±20 During operation Crystal oscillation 32.768 During operation Drain current IDD2 External clock Drain current IDD3 During standby Min. VDD-0.25 0.8VDD 0.9VDD Typ. Max. 0.55 0.2VDD 0.1VDD Unit Applicable Other inputs Other input pins Input pins other than TEST TEST (pull-down resistor) Input pins other than TEST COM1 COM16 SEG1 SEG60
output load Note values this table assured when chip exposed light.
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Semiconductor Characteristics
MSM9000B-xx
(VDD=0 VSS=-3 Ta=-30 +85°C) Parameter Bias voltage Bias voltages Bias voltage Bias voltage Contrast pitch Symbol -VSS1 -VSS2, -VSS4 -VSS5 -Vcon Condition -VSS2, "A"V "L", Contrast -VSS2, "A"V -VSS2, "A"V each stage Min. 1/2A-0.1 3/2A-0.1 2A-0.2 0.18 Typ. 1/2A 3/2A 0.21 Max. 1/2A+0.1 3/2A+0.1 2A+0.2 0.26 Unit Applicable VSS1 VSS2, VSS4 VSS5
Note Connect capacitor bias generator. Note values this table assured when chip exposed light.
Characteristics Parallel interface
(VDD=2.5 VBI=3 Ta=-30 +85°C) Parameter high-level width low-level width high-level width low-level width WR-RD high-level width setup time hold time Write data setup time Write data hold time Read data output delay time Read data hold time External clock high-level width External clock low-level width RESET pulse width Rise fall time external clock Symbol tWRH tWRL tWWH tWWL tWWRH tDSW tDHW tDDR tDHR tWCH tWCL tWRE Condition CL=50 Min. Max. Unit
Note: values this table assured when chip exposed light.
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Semiconductor Serial interface
MSM9000B-xx
(VDD +85°C) Parameter setup time hold time setup time hold time high-level pulse width low-level pulse width clock cycle time delay time output delay time delay time BUSY delay time setup time low-level pulse width RESET pulse width Rise fall time external clock Symbol tSAS tSAH tWSHH tWSHL tSYS tOFF tBUSY tSHS tWWL tWRE Condition Min. Max. Unit
Note: values this table assured when chip exposed light.
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Semiconductor Timing Diagram Parallel Interface
MSM9000B-xx
tWWL
tWWH tWWRH tWRH tWRL
tDSW DB0-7 tWRE
tDHW
tDDR
tDHR
RESET
tWCH
tWCL
0.8VDD, 0.9VDD,
0.2VDD 0.1VDD
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Semiconductor Timing Diagram Serial Interface
MSM9000B-xx
tSAH
tSAS
tWSHL
tWSHH
tSHS
tSYS
tWWL
tBUSY
tOFF
tWRE
RESET
VDD, VDD,
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FUNCTIONAL DESCRIPTION
Functional Description (Chip Select) Chip select input pin. logic input selects chip logic high input does select chip. Command display data inputs enabled only when chip selected. When input high, pins high impedance state, causing SHT, pins high level internally. (Write Enable) When parallel interface used, this write signal input. Data written into register rising edge pulse. When serial interface used, this latch signal input. This normally high. (Read Enable) When parallel interface used, this read signal input. While pulse low, data read. normally high. When this made with low, display data pointed address pointer output from DB7. When made with high, busy data output from signals output from DB7. After rising edge busy data output. data automatically changes non-busy after specified time elapses. When serial interface used, this "L". (Command/Data Select) This input selects whether data input pins handled command display data, depending state rising edge When input data handled command. When display data input. (Data Buses Data input output pins parallel interface. Normally data buses high impedance, when driven low, display data busy signal output. When serial interface used, leave this open. (Serial Data Input) Data input serial interface. Commands display data read rising edge written registers rising edge eight-bit data immediately before rising edge valid. When parallel interface used, this "L". (Serial Data Output) Data output serial interface. display data pointed address pointer output rising edge SHT. After rising edge busy data output. data automatically changes non-busy after specified time elapses. When parallel interface used, this remains high impedance state. (Shift Clock) Clock input input output serial interface data. Data input synchronous with rising edge clock, data output synchronous with falling edge clock. This normally high. When parallel interface used, this "L". 11/38
Semiconductor
MSM9000B-xx
(Crystal) Input crystal oscillation. connecting 32.768-kHz crystal capacitors this pin, crystal oscillation circuit formed. When external clock used, input clock pin. (Crystal) Output crystal oscillation. connecting 32.768-kHz crystal capacitors this pin, crystal oscillation circuit formed. When external clock used, leave this open.
32.768 OPEN External clocks
When forming crystal oscillation circuit
When inputting external clock
Oscillation circuit diagram (Parallel/Serial Select) Input choose between parallel interface serial interface. select parallel interface, make this low. select serial interface, make this high. After power turned change setting this pin. 9D/16D (Duty Select) Input duty cycle. When this "H", duty cycle selected. When "L", duty cycle 1/16 selected. Choose either according panel used. When duty cycle chosen, leave common output pins COM10 COM16 open. 32K/EXT (Clock Select) Input choose crystal oscillation mode external clock input mode. Leave this level. RESET (Reset) Reset signal input pin. Setting this results initial state. modes display after reset input, "Mode Settings after Reset Input". (Contrast Change) Input pins that determine voltages VSS2 VSS3 together with contrast adjustment command. table below shows relationships between states contrast adjustment ranges.
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MSM9000B-xx
Contrast adjustment range command
TEST (Test Signal) Test signal input provided test manufacturer. this leave open. SEG1 SEG60 (Segment Segment Segment signal output pins drive LCD. Leave unused pins open. COM1 COM16 (Common Common Common signal output pins drive LCD. When duty cycle 1/9, COM1 COM9 leave COM10 COM16 open. Power supply logic section. Connect this positive terminal power supply. connected power supply. VSS1, VSS4, VSS5 Pins voltage multiplier outputs power supply. Connect capacitors between these pins charge distribution with VSS2, capacitor voltage stabilization during generation bias voltages. logical values bias voltage follows: Highest voltage: VSS1=VSS2, VSS2, VSS4=VSS2, 3+VSS2, Lowest voltage: VSS5=VSS2, 3+VSS2, 3/2+VSS2, both 1/16 duty, bias used. VSS2, Voltage regulator output bias generator input used reference voltage bias generator. Connect capacitor between this charge distribution among capacitors voltage stabilization during generation various bias voltages. VSS6 connect capacitor store 3-/2-fold voltage. Connect capacitor 0.1µF more between this VDD. Halves output voltage multiplier(3-/2-fold). Connect capacitor between this VDD. 13/38
Semiconductor
MSM9000B-xx
VC1, VCC1 Pins connect charge distribution capacitor used voltage malitiplier (3-/2-fold). Connect capacitor between VCC1. VC2, VCC2 Pins connect capacitor charge distribution generate bias voltages basis VSS2, Connect capacitor between VCC2.
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Semiconductor Parallel Interface Input-Output Timing Input timing diagram
MSM9000B-xx
DB7-0
DATA
Output timing diagram
DB7-1
DATA
DATA
BUSY
When C/D="L", display data output DB7-0 pins. When C/D="H" DB7-1="L", busy data output pin.
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Semiconductor Timings Serial Interface Input timing diagram
MSM9000B-xx
Output timing diagram
BUSY
BUSY
output, eight bits after pulse input valid.
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Semiconductor
MSM9000B-xx
LIST COMMANDS
Don't Care Mnemonics Operation Load Pointer Address BKCG Load Option Frequency Bank Change Comments Addresses 0-11, 16-27 characters addresses 32-43, 48-59 arbitrators Sets additional functions during execution AINC. Sets conditions master frequency.
Valid only duty. Changes display addresses 0-11, 16-27.
CONT
Contrast Up/Down
Adjusts VLCD stages. Adjustment range changed setting pins. Contrast level D0="1". Contrast level down D0="0".
STOP
Stop Mode
This mode cancelled D0="1" irrespective either C/D. Stops oscillation performs operation equivalent that DISP command.
SOE/D
Serial Enable/Disable
Switches between output high impedance
DISP
Display On/Off
Display D0="1". Display D0=0. commons segments level display OFF. Arbitrators alone displayed D4="1".
AINC
Address Increment
Pointer address incremented But, this command invalid operations that added setting (I1, I0).
Arbitrator Blink
Data that input after setting D0="1", data arbitrator blink (1-dot unit). This cancelled D0="0".
Character Blink Blink Pattern Control
Controls blinking character.
Sets blink patterns characters. chara) D0="1", chara) D0="0".
ABLC
Arbitrator Line Change
Sets arbitrator display lines.
Notes Pointer address changed even commands numbers enterd. Pointer address automatically incremented when commands numbers display code data, arbitrator data enterd.
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Semiconductor
Additional function additional function blank code written each subsequent AINC. Blinking canceled each subsequent AINC. above functions ORed.
MSM9000B-xx
Remarks Used automatically clear power-on.
Frequency source oscillation clocks input. Remarks Used generate optimum frequency when external
DISP
Character Arbitrator Remarks Used turn display.
Don't care ABLC (when duty 1/16)
Arbitrator COM1 COM15 COM16 Arbitrator COM2 COM16 COM1 Remarks Arbitrator indicates display data addresses while arbitrator indicates display data addresses
Don't care ABLC (when duty 1/9)
Arbitrator COM1 COM8 COM9 Arbitrator COM2 COM9 COM1 Remarks Arbitrator indicates display data addresses while arbitrator indicates display data addresses
Don't care
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MSM9000B-xx
Explanation Commands [D7, D0], Don't care (Load Pointer Address) This command sets address pointer address command executed address display data input. settable addresses inconsecutive addresses 0BH, 1BH, 2BH, represented When addresses 0FH, 1FH, 2FH, set, assumed. After RESET "L", address 00H. (Load Option) This command executes additional function specified display current address when AINC command executed. Additional functions shown below. After RESET "L",, both "0".
None After this command executed, blank code writtern each time AINC executed. After this command executed, blinking canceled each time AINC executed. above additional functions ORed. Additional function
(Set Frequency) This command sets number which external clock input from divided order source frequency inside This command valid when 32K/EXT "L". dividing ratio specified command. table below lists source oscillation frequencies After RESET "L", both "0".
Frequency source oscillation
BKCG1/0 (Bank Change 1/0) 1/0] This command changes addresses (banks) displayed. command valid only when duty 1/9. When addresses (character (arbitrators displayed. When "1", addresses (character (arbitrators displayed. command display data regardless bank setting. After RESET "L", "0".
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Semiconductor
MSM9000B-xx
CONT (Contrast Down) 1/0] This command selects voltage VSS2, that used reference voltage bias. When value VSS2, changed, contrast changed accordingly. contrast controlled value 3-bit up/down counter that eight stages supported. value up/down counter incremented when entered this command decremented when entered. counter changes within range When counter reaches goes back "0". According settings contrast stages changed stage bias voltage minimized. larger contrast stage, higher bias voltage. stage bias voltage maximized. After RESET input, counter minimum value specified Example: Note: some contrast stages, bias voltage increased higher. Adjust stage that bias voltage does exceed STOP (Set Stop Mode) This command sets standby mode. Specifically, command stops oscillation block prevent current form flowing through oscillation block outputs level output pins. Standby mode canceled when regardless setting pin. When command data with entered, command executed data input. same time, standby mode canceled. After RESET "L", standby mode disabled. SOE/D (Serial Enable/Disable) 1/0] This command controls impedance output pin. command valid only when serial interface used. When "0", high impedance state. After RESET "L", "0". DISP (Display On/Off) 1/0, 1/0] This command sets display mode. When "1", turned When "0", turned off, which case, level output segment common pins. When turned (D0="1"), "1", only arbitrators displayed when "0", both characters arbitrators displayed. table below lists display modes. After RESET "L", both "0".
Characters Arbitrators
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Semiconductor
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AINC (Address Increment) This command increments value address pointer one. Each time this command input, value incremented one. Addresses increased follows: This cycle repeated. function specified command performed previous address before address incremented every time this command input. (Arbitrator Blink) 1/0] This command turns arbitrator blinking off. Display data input after handled arbitrator blink data. Input blink data corresponds dots arbitrator same address one-to-one basis. When "1", blinking enabled. When "0", blinking disabled. While blinking, turned repeatedly. Blinking specified which enabling arbitrator specified, does blink. Dummy data must arbitrator data Data cannot written addresses After RESET "L", "0". (Character Blink) 1/0, This command enables disables character blinking. command executed address pointed address pointer. When "1", blinking enabled. When "0", blinking disabled. During blinking, turning dots dots) character display repeated. another blinking pattern, turning dots character display repeated. Either pattern selected command. After RESET "L", value address pointer automatically incremented one. (Blink Pattern Control) 1/0] This command selects character blinking pattern. When "1", turning dots dots) character display repeated. When "0", turning dots character display repeated. When character blank, character does blink visibly. When "0", character does blink visibly while dots turned After RESET "L", "0".
"1"]
"0"]
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Semiconductor
MSM9000B-xx
ABLC (Arbitrator Line Change) This command selects common line arbitrator display, according settings table below shows relationships between displayed common lines, assuming that display data addresses character display data addresses character display data addresses arbitrator display data addresses arbitrator Different common lines displayed duty duty. After RESET input, both "0". Common lines displayed ABLC command follows: When 1/16 duty chosen
Character COM3 COM1 COM2 Character COM10 COM8 COM9 Arbitrator COM1 COM15 COM16 Arbitrator COM2 COM16 COM1
When duty chosen
Character COM3 COM1 COM2 Character Arbitrator COM1 COM8 COM9 Arbitrator COM2 COM9 COM1
Note: When duty chosen, characters switched changing bank. Increment address pointer When display data arbitrator blink data input AINC command executed, address pointer incremented one.
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MSM9000B-xx
Mode Setting after Reset Input table below lists settings individual modes during RESET input.
Command BKCG CONT STOP SOE/D DISP ABLC "0", "0", Mode setting "0", "0", Remarks address pointer "00". Load Option command with additional function. dividing ratio Display addresses set. control counter (Stage Standby mode disabled. high impedance state. Both characters arbitrators display mode set, dispaly turned off. Display data input mode enabled. Blink mode such that turning dots character display repeated. Arbitrator corresponds COM1, arbitrator corresponds COM2.
Even when reset input, display initialized. clear display data, blank code must written. (This done with additional function AINC command.)
Mode Settings during Standby table below lists settings individual modes during standby.
Command BKCG CONT STOP SOE/D DISP ABLC change setting before standby mode retained. "0", count before standby mode retained. Standby state change. setting before standby mode retained. Both character arbitrator display mode set, display turned off. change setting before standby mode retained. Mode setting Remarks address pointer "00".
Data before standby mode retained display RAM.
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Semiconductor Display Screen Memory Addresses
MSM9000B-xx
Arbitrator Arbitrator Character Screen Character
Arbitrator Arbitrator Character Character
Note: Characters input codes. Arbitrators displayed directly without intervening ROM. Input data displayed shown below.
S5n+1
S5n+5
Segment
Dummy data must input data Either input input data
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Semiconductor Calculation Method Various Kinds Frequencies Frame frequency 1/16 duty (Source clock cycle) (1/Dividing ratio) Frame cycle duty (Source clock cycle) (1/Dividing ratio) Frame cycle Example Source oscillation frequency 32.768 Dividing ratio Specification: 1/16 Duty Clock cycle 30.5
MSM9000B-xx
Under these conditions, frame frequency calculated from expression follows: Frame cycle 30.5 10-6 13.66 Therefore Frame frequency 73.2 Calculating blinking frequency blinking frequency calculated from following expression: Blinking frequency (Source clock cycle) (1/Dividing ratio) Example Source oscillation frequency 32.768 Dividing ratio Clock cycle 30.5 Under these conditions, blinking frequency calculated from expression follows: Blinking cycle 30.5 10-6 Therefore Blinking frequency Source oscillation frequency busy time When data written read from command input, data processing time (busy time) taken. maximum busy time source clock cycle multiplied busy signal (not-busy "L", busy detected when serial interface used when parallel interface used. When display data commands input consecutively, wait must inserted source clock cycle multiplied Another detect busy signals input data commands during not-busy time only.
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Semiconductor Flowchart Power-on (parallel interface)
MSM9000B-xx
Turn power Input reset CS="L" modes BKCG1/0, BPC, ABLC LOT, I1="1", I0="1" AINC times LOT, I1="0", I0="0"
Input reset after VDD-VSS level exceeds 2.5V. 5ms, external, power-on reset Chip enable.
mode reset input according specifications. load option. blank code written blinking released each time AINC executed. data cleared. load option cleared.
Input data displayed initial screen
data displayed initial screen been input? DISP, D4="X", D0="1" Perform ordinary operation display turned initial screen displayed. according display.
When stage selected already determined, contrast adjusted before display turned (for example, same time when mode set). After command display data input, check busy data. Make sure that busy data ("H") changed not-busy data ("L") before making next input.
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Semiconductor Flowchart Power-on (serial interface)
MSM9000B-xx
Turn power Input reset CS="L" SOE/D, D0="1" Wait clocks modes BKCG1/0, BPC, ABLC LOT, I1="1", I0="1" AINC times LOT, I1="0", I0="0"
Input reset after VDD-VSS level exceeds 2.5V. 5ms, external, power-on reset Chip enable. output enabled detect busy signal. Insert wait only processing SOE/D command. busy signal detection subsequent inputs).
Change settings after reset, necessary. load option. blank code written blinking disabled each time AINC executed. data cleared. load option cleared.
Input data displayed initial screen
data displayed initial screen been input? DISP, D4="X", D0="1" Perform ordinary operation display turned initial screen displayed. according display.
When stage selected already determined, contrast adjusted before display turned (for example, same time when mode set). After command display data input, check busy data. Make sure that busy data ("H") changed not-busy data ("L") before making next input.
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Semiconductor
MSM9000B-xx
Flowcharts Cancel Standby Mode
Ordinary operation
Busy signal detection
Confirm not-busy signal.
Not-busy?
STOP Standby mode standby mode.
Standby mode Wait until oscillation stabilized. Wait until voltage multiplier stabilized. Ordinary operation length wait depends configuration oscillation circuit. When code which input, standby mode canceled regardless input.
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Semiconductor Liquid Crystal Applied Waveform Examples 1/16 duty
MSM9000B-xx
VSS1 VSS2, VSS4 VSS5 VSS1 VSS2, VSS4 VSS5
VSS1 VSS2, VSS4 VSS5 VSS1 VSS2, VSS4 VSS5
Lighting-on Lighting-off
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Semiconductor duty
MSM9000B-xx
VSS1 VSS2, VSS4 VSS5 VSS1 VSS2, VSS4 VSS5
VSS1 VSS2, VSS4 VSS5 VSS1 VSS2, VSS4 VSS5
Lighting-on Lighting-off
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Semiconductor Codes Character Fonts Code
MSM9000B-xx
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Semiconductor
MSM9000B-xx
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Semiconductor
MSM9000B-xx
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Semiconductor
MSM9000B-xx
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APPLICATION CIRCUITS
Example [1/16 duty, parallel interface, crystal oscillation circuit bias voltage generator used]
Panel
characters characters lines symbols lines
C=0.1 VCC1 VCC2 VSS1 VSS2, VSS4 VSS5
common drivers
Segment drivers
32.768 32K/EXT 9D/16D
MSM9000B-xx
RESET
DB7-0
VSS6 PORT
TEST
OPEN
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Semiconductor
MSM9000B-xx
Example [1/9 duty, serial interface, 32kHz external clock input bias voltage generator used]
Panel
characters characters line symbols lines
C=0.1 VCC1 VCC2 VSS1 VSS2, VSS4 VSS5
common drivers
OPEN
Segment drivers
32K/EXT External Clock OPEN
MSM9000B-xx
9D/16D
RESET
DB7-0
VSS6
TEST
OPEN PORT
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Semiconductor
MSM9000B-xx
CONFIGURATION
Layout Chip size: 4.76 3.29 Bump size:
Coordinates
Name TEST (µm) -2012 -1837 -1662 -1487 -1312 -1137 -962 -787 -612 -437 -262 1137 1312 (µm) -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 Name VCC1 VSS6 VCC2 VSS1 VSS2,3 VSS4 VSS5 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG60 SEG59 (µm) 1487 1662 1837 2012 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 (µm) -1508 -1508 -1508 -1508 -1375 -1255 -1135 -1015 -895 -775 -605 -495 -385 -275 -165
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Semiconductor
MSM9000B-xx
Name SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19
(µm) 2194 2194 2194 2194 2194 2194 2194 2194 2194 1980 1872 1765 1659 1552 1444 1337 1231 1123 1016 -161 -267 -374 -482 -588 -695 -803 -910 -1016 -1123 -1231
(µm) 1045 1155 1265 1375 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508
Name SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 RESET 32K/EXT 9D/16D
(µm) -1337 -1444 -1552 -1659 -1765 -1872 -1980 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194
(µm) 1508 1508 1508 1508 1508 1508 1508 1375 1265 1155 1045 -165 -275 -385 -495 -605 -775 -895 -1015 -1135 -1255 -1375
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