Auxiliary Motherboard Clock Generator/Buffer Features Figure

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Auxiliary Motherboard Clock Generator/Buffer Features Figure

Datasheet Thumbnail

Top Searches for this datasheet

FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Features
Figure Block Diagram
VDD_66
Develops peripheral clocks required 2-way 4-way multi-processor clock-partitioned platforms, including: buffered copies 66.67MHz 66REF reference input Twelve 33.3MHz clocks, developed divide-by-two 66REF reference input buffered copies 14.318MHz 14REF reference input 48MHz clocks, generated from 14REF reference input Serial-bus interface control clock outputs Three clock management controls enable, disable tristate banks clock outputs independently serial interface Active-low PWR_DWN# signal allows shuts down disables outputs Supports Test Mode tristate output control facilitate board testing Available 56-pin SSOP TSSOP
66REF
CK66_0:4 CK66_5
VSS_66 VDD_P
SEL_Q SEL_R SEL_S
PCI_0:5 PCI_6:7 SMBus Output Control PCI_8:11
VSS_P VDD_48
CK48_0 PWR_DWN# CK48_1
VSS_48 VDD_R
14REF
REF_0:1
FS6159
Figure Configuration
VSS_N 14REF VDD_N 66REF VSS_P PCI_0 VDD_R REF_1 REF_0 VSS_R VDD_66 CK66_5 CK66_4 VSS_66 VSS_66 CK66_3 CK66_2 VDD_66 VDD_66 CK66_1 CK66_0 VSS_66 VDD_48 CK48_1 CK48_0 VSS_48 SEL_S PWR_DWN# VDD_S VSS_S
VSS_R
Table Clock Parameters
CLOCK GROUP CK66 CK48 PINS SUPPLY VOLTAGE 3.3V 3.3V 3.3V 3.3V SUPPLY GROUP VDD_66 VDD_P VDD_R VDD_48 FREQUENCY (MHz) 66.67 33.33 14.318 48.008 SKEW (MAX) 250ps 300ps
PCI_1 VDD_P VSS_P PCI_2 PCI_3 VDD_P VSS_P PCI_4 PCI_5 VDD_P PCI_6 PCI_7 VSS_P
FS6159-01
Table Clock Offsets
RELATION CK66 leads PHASE 1.5ns 3.5ns
VDD_P PCI_8 PCI_9 VSS_P PCI_10 PCI_11 VDD_P SEL_Q SEL_R
Intel Pentium registered trademarks Intel Corporation. Lexmark trademark Lexmark International, Inc. Non-linear spread spectrum modulation profile licensed under Patent 5488627, Lexmark International, Inc. This document contains information preproduction product. Specifications information herein subject change without notice.
ISO9001
2.27.02 IntFF
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Table Descriptions
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active-low
TYPE
NAME 14REF 66REF CK48_0:1 CK66_0:5 PCI_0:11
DESCRIPTION 14.318MHz clock input, used develop CK48 clock outputs 66.67MHz clock input, used develop CK66 clock outputs 48MHz clock outputs 66MHz clock outputs, developed buffered copies 66REF reference input Twelve 33.33MHz clock outputs, developed divide-by-two 66REF reference input. Groups outputs disabled SEL_Q, SEL_R, SEL_S (see Table Individual outputs disabled serial interface. Asynchronous active-low LVTTL power-down signal shuts down oscillator PLL, puts clocks state. 3.3V clock outputs, developed buffered copies 14REF reference input SMBus serial interface clock input SMBus serial interface data input/output Three clock management select inputs, used enable, disable, tristate groups clock outputs 3.3V power supply core 3.3V power supply CK48 clock outputs 3.3V power supply CK66 clock outputs 3.3V power supply 14REF 66REF reference inputs 3.3V power supply clock outputs 3.3V power supply clock outputs 3.3V power supply serial interface digital input pins Ground core Ground CK48 clock outputs Ground CK66 clock outputs Ground 14REF 66REF reference inputs Ground clock outputs Ground clock outputs Ground serial interface digital input pins
SUPPLY VDD_N VDD_N VDD_48 VDD_66 VDD_P
PWR_DWN# REF_0:1 SEL_Q SEL_R SEL_S VDD_48 VDD_66 VDD_N VDD_P VDD_R VDD_S VSS_48 VSS_66 VSS_N VSS_P VSS_R VSS_S
VDD_S VDD_R VDD_S VDD_S VDD_S
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Programming Information
Table Clock Enable Configuration
CONTROL INPUTS
PWR_DWN# SEL_Q SEL_R SEL_S CK48_0 CK48_1 CK66_0:4
CLOCK OUTPUTS (MHz)
CK66_5 REF_0:1 PCI_0:5 PCI_6:7 PCI_8:11
48.008 48.008 48.008 48.008 tristate 48.008 48.008 48.008 stopped
48.008 48.008 48.008 48.008 tristate 48.008 48.008 stopped stopped
66.67 66.67 66.67 66.67 tristate 66.67 66.67 66.67 stopped
66.67 66.67 66.67 66.67 tristate stopped 66.67 66.67 stopped
14.318 14.318 14.318 14.318 tristate 14.318 stopped 14.318 stopped
33.33 stopped stopped stopped tristate 33.33 33.33 33.33 stopped
33.33 stopped 33.33 stopped tristate 33.33 33.33 33.33 stopped
33.33 33.33 33.33 stopped tristate 33.33 33.33 33.33 stopped
Control inputs override SMBus register settings situations where outputs stopped
Table Synthesis Offset
CLOCK CK48
DEVIATION (ppm) +167
Programming Interface
TARGET (MHz) 48.00
ACTUAL (MHz) 48.0080
This device supports SMBus Block Write Block Read commands. device address follows:
48MHz clock required 167ppm from 48.000MHz conform requirements.
Table Device Address
Block Write
Block Write command allows host write several bytes data sequential registers, starting with Byte Register. shown Figure Block Write starts with seven-bit device address followed logic-low bit. After acknowledge device address this device, command code containing zeroes (0000 0000) written. After zero command code acknowledge, host then issues byte count that describes number data bytes written. byte count must minimum byte maximum bytes.
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Table Byte Count
BYTE COUNT 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0001 1111 0010 0000 DESCRIPTION allowed: Must have least byte Writes byte (Byte Writes bytes (Byte order) Writes three bytes (Byte order) Writes four bytes (Byte order) Writes five bytes (Byte order) These byte counts ignored this device Maximum byte count supported (32)
Block Read
After acknowledge byte count, data bytes written starting with Register incrementing sequentially. acknowledge this device between each byte data must occur before next data byte sent.
Block Read command, shown Figure permits host read several bytes data from sequential registers, starting default Register perform Block Read procedure, seven-bit device address sent, followed logic-high bit. Following acknowledgement byte count host, this device will take command will transmit data beginning with Register After last byte data, host does acknowledge final transfer instead generates STOP command. NO-acknowledge does occur, device releases host will read ones. host does want receive data, host should acknowledge last data byte instead issue STOP command next clock.
Figure Block Write
DEVICE ADDRESS BYTE COUNT DATA BYTE DATA BYTE
7-bit Receive Device Address START Command
Command Code Acknowledge WRITE Command From host device
Byte Count
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
Acknowledge From device host
Figure Block Read
DEVICE ADDRESS BYTE COUNT DATA BYTE DATA BYTE
7-bit Receive Device Address Repeat START
Byte Count Acknowledge READ Command From host device
Data Acknowledge Acknowledge From device host
Data Acknowledge STOP Command
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Register Programming
Table Byte Register
CLOCK CK66_0 CK66_1 CK66_2 CK66_3 CK66_4 CK66_5 (reserved) (reserved) DESCRIPTION enabled, disabled enabled, disabled enabled, disabled enabled, disabled enabled, disabled enabled, disabled Initialize Initialize
logic-one written valid location enables (turns assigned output clock. Likewise, logic-zero written valid location disables (turns off) assigned output clock. unused reserved register bits should cleared zero. These registers expected configured power-up expected change during normal modes operation. Serial bits read this device starting with Byte proceeding Byte each byte read first, bits read descending order down Note that SEL_Q, SEL_R SEL_S pins will override register settings when disabling outputs. Register settings will only affect enabled outputs. Upon application device, register bits that outputs enabled active. programmed settings will retained device powered-down PWR_DWN# low. After powering-up device PWR_DWN# device will operate according internal register settings.
Table Byte Register
CLOCK (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) DESCRIPTION Initialize Initialize Initialize Initialize Initialize Initialize Initialize Initialize
Table Byte Register
CLOCK PCI_0 PCI_1 PCI_2 PCI_3 PCI_4 PCI_5 PCI_6 PCI_7 DESCRIPTION enabled, disabled enabled, disabled enabled, disabled enabled, disabled enabled, disabled enabled, disabled enabled, disabled enabled, disabled
Table Byte Register
CLOCK (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) DESCRIPTION Initialize Initialize Initialize Initialize Initialize Initialize Initialize Initialize
Table Byte Register
CLOCK PCI_8 PCI_9 PCI_10 PCI_11 CK48_0 CK48_1 REF_0 REF_1 DESCRIPTION enabled, disabled enabled, disabled enabled, disabled enabled, disabled enabled, disabled enabled, disabled enabled, disabled enabled, disabled
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Power Management
Power Down
expected that clock management inputs register settings will configured power-up will change during normal operation.
Clock Enable
Certain clock outputs disabled either combination logic states SEL_Q, SEL_R, SEL_S clock management control input pins shown Table SMBus register bits, shown Section 3.3. Disabling clock, determined clock management control inputs, will override SMBus register setting. active output, determined clock management control inputs, disabled time SMBus register. enable clock output, both control inputs SMBus register bits must appropriately. Enabled clocks will continue while disabled clocks stopped. Note that clocks disabled while active, glitches occur.
PWR_DWN# signal asynchronous, active-low LVTTL input that places device power inactive state without removing power from device. internal clocks turned off, clock outputs held low. reference clocks this device developed reference clock device (FS6158). assumed that PWR_DWN# signal same signal both devices Since PWR_DWN# asynchronous, signal synchronized internally falling edge each individual clock shown Figure Each clock stops immediately first falling edge after PWR_DWN#. Once powered down, both inputs tristated. register data retained.
Table Latency Table
SIGNAL SIGNAL STATE Power Power Output: Device: LATENCY MIN. clocks clocks MAX. clock clock
PWR_ DWN#
Upon release PWR_DWN# (power-up), external circuitry should allow minimum lock before enabling clocks.
Figure PWR_DWN# Timing
Clock (internal) PWR_DWN# Clock (output) After outputs shut off. Crystal Oscillator
Shaded regions Crystal Oscillator waveforms indicate that clock valid Crystal Oscillator active.
until clock valid
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
MIN. VSS-0.5 VSS-0.5 VSS-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION Core Input Buffers: (VDD, VDD_N, VDD_S) Clock Buffers: (VDD_48, VDD_66, VDD_P, VDD_R) 14REF 66REF 66REF, 14REF CK66 Load Capacitance CK48 MIN. 3.135 3.135 14.318 66.667 TYP. MAX. 3.465 3.465 UNITS
Supply Voltage
Operating Temperature Range Input Frequency Input Load Capacitance
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Table Electrical Specifications
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Negative currents indicate current flows device.
PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs Supply Current, Static Clock Inputs (14REF, 66REF) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
IDDs
3.3V supplies 3.465V PWR_DWN# low, supplies 3.465V
VSS-0.3
VDD+0.3
Digital Inputs (PWR_DWN#, SEL_Q, SEL_R, SEL_S) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Serial Interface (SCL, SDA) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage High-Level Input Current Low-Level Input Current (pull-up) Low-Level Output Sink Current (SDA) Vhys 0.4V, 3.465V 3.465V 3.465V 3.465V 2.52 VSS-0.3 1.44 VDD+0.3 1.08 VSS-0.3 VDD+0.3
REF_0:1, CK48_0:1 Clock Outputs (Type Clock Driver) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOSH IOSL shorted 30s, max. 3.3V; shorted 30s, max. VDD_R, VDD_48 3.135V, 1.0V VDD_R, VDD_48 3.465V, 3.135V VDD_R, VDD_48 3.135V, 1.95V VDD_R, VDD_48 3.465V, 0.4V Measured 1.65V, output driving Measured 1.65V, output driving high
PCI_0:11, CK66_0:5 Clock Outputs (Type Clock Driver) High Level Output Source Current Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOSH IOSL shorted 30s, max. 3.3V; shorted 30s, max. VDD_P, VDD_66 3.135V, 1.0V VDD_P, VDD_66 3.465V, 3.135V VDD_P, VDD_66 3.135V, 1.95V VDD_P, VDD_66 3.465V, 0.4V Measured 1.65V, output driving Measured 1.65V, output driving high
2.27.02
ISO9001
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Table Timing Specifications
Unless otherwise stated, power supplies 3.3V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Spread spectrum modulation disabled except Rise/Fall time measurements.
PARAMETER Overall Clock Offset Propagation Delay Tristate Enable Delay Tristate Disable Delay Clock Stabilization power-up) REF_0:1 Clock Outputs Duty Cycle Jitter, Period (peak-peak) Rise Time Fall Time CK48_0:1 Clock Outputs Duty Cycle Jitter, Period (peak-peak) Rise Time Fall Time
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
CK66 leads 1.5V, CL=30pF 1.5V, 30pF (measured rising edges) Rising edge 66REF rising edge CK66 Rising edge 66REF rising edge
tDZL, tDZH tDLZ, tDHZ tSTB
SEL_Q SEL_R SEL_S SEL_Q SEL_R SEL_S PWR_DWN#
tj(P)
Ratio high pulse width clock period, measured 1.5V From rising edge rising edge 1.5V, 20pF Measured 0.4V 2.4V; 10pF Measured 0.4V 2.4V; 20pF Measured 2.4V 0.4V; 10pF Measured 2.4V 0.4V; 20pF
1000
tj(P)
Ratio high pulse width clock period, measured 1.5V From rising edge rising edge 1.5V, 20pF Measured 0.4V 2.4V; 10pF Measured 0.4V 2.4V; 20pF Measured 2.4V 0.4V; 10pF Measured 2.4V 0.4V; 20pF
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Table Timing Specifications, continued
Unless otherwise stated, power supplies 3.3V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Spread spectrum modulation disabled except Rise/Fall time measurements.
PARAMETER PCI_0:11 Clock Outputs Duty Cycle Clock Skew Additive Jitter, Period (peak-peak) Rise Time Fall Time CK66_0:5 Clock Outputs Duty Cycle Clock Skew Additive Jitter, Period (peak-peak) Rise Time Fall Time
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
tsk(o) tj(P)
Ratio high pulse width clock period, measured 1.5V 1.5V From rising edge rising edge 1.5V, 30pF Measured 0.4V 2.4V; 10pF Measured 0.4V 2.4V; 30pF Measured 2.4V 0.4V; 10pF Measured 2.4V 0.4V; 30pF
tsk(o) tj(P)
Ratio high pulse width clock period, measured 1.5V CK66 CK66 1.5V From rising edge rising edge 1.5V, 30pF Measured 0.4V 2.4V; 10pF Measured 0.4V 2.4V; 30pF Measured 2.4V 0.4V; 10pF Measured 2.4V 0.4V; 30pF
Figure Measurement Points
3.3V 2.4V 2.0V 1.5V 0.8V 0.4V
Figure Timing Diagram
3.3V 2.4V
1.5V
0.4V
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Table Serial Interface Timing Specifications
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical.
PARAMETER Clock frequency free time between STOP START time, START (repeated) Hold time, START time, data input Hold time, data input Output data valid from clock Rise time, data clock Fall time, data clock High time, clock time, clock time, STOP
SYMBOL fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tsu:STO
CONDITIONS/DESCRIPTION
STANDARD MODE MIN. 1000 MAX.
UNITS
Minimum delay bridge undefined region falling edge avoid unintended START STOP
SDA, SDA,
Figure Timing Data
tsu:STA thd:STA tsu:STO
START
ADDRESS DATA VALID
DATA CHANGE
STOP
Figure Data Transfer Sequence
tsu:STA thd:STA thd:DAT tsu:DAT tsu:STO
tBUF
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Table REF_0:1, CK48_0:1 Clock Outputs
Voltage High Drive Current (mA) MIN. TYP. MAX. Voltage Drive Current (mA) MIN. TYP. MAX. -102 -101 -100
Output Current (mA)
-100 -120
Output Voltage
Data this table represents nominal characterization data only
Table PCI_0:11, CK66_0:5 Clock Outputs
Voltage
High Drive Current (mA)
MIN. TYP. MAX.
Voltage
Drive Current (mA)
MIN. TYP. MAX. -132 -131 -130 Output Current (mA) -129 -127 -126 -124 -121 -117 -112 -105
-100 -125 -150
Output Voltage
Data this table represents nominal characterization data only
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Package Information
Table 56-pin SSOP (0.300") Package Dimensions
DIMENSIONS INCHES MIN.
0.095 0.008 0.008 0.005 0.720 0.395 0.291 0.015 0.020
MILLIMETERS MIN.
2.41 0.20 0.20 0.13 18.29 10.03 7.39 0.38 0.51
MAX.
0.110 0.016 0.0135 0.010 0.730 0.420 0.299 0.025 0.040
MAX.
2.79 0.41 0.34 0.25 18.54 10.67 7.59 0.64 1.01
AMERICAN MICROSYSTEMS, INC.
SEATING PLANE
0.025
0.64
Table 56-pin SSOP (0.300") Package Characteristics
PARAMETER
Thermal Impedance, Junction Free-Air Lead Inductance, Self
SYMBOL
CONDITIONS/DESCRIPTION
flow Longest trace wire Shortest trace wire Longest trace wire first adjacent trace Shortest trace wire first adjacent trace Longest trace wire next adjacent trace Shortest trace wire next adjacent trace Longest trace wire Shortest trace wire Longest trace wire first adjacent trace Shortest trace wire first adjacent trace Longest trace wire next adjacent trace Shortest trace wire next adjacent trace
TYP.
6.41 2.49 3.65 1.35 2.50 0.90 0.94 0.50 0.48 0.20 0.07 0.02
UNITS
°C/W
Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Table 56-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS INCHES MIN.
0.002 0.0067 0.0035 0.547 0.236 0.018 0.008
MILLIMETERS MIN.
0.05 0.17 0.09 13.9 6.00 0.45 0.20
MAX.
0.047 0.006 0.011 0.008 0.555 0.244 0.030
MAX.
1.20 0.15 0.27 0.20 14.1 6.20 0.75
AMERICAN MICROSYSTEMS, INC.
0.318 0.019
8.10 0.50
SEATING PLANE
Table 56-pin TSSOP (6.1mm) Package Characteristics
PARAMETER
Thermal Impedance, Junction Free-Air Lead Inductance, Self
SYMBOL
CONDITIONS/DESCRIPTION
flow Longest trace wire Shortest trace wire Longest trace wire first adjacent trace Shortest trace wire first adjacent trace Longest trace wire next adjacent trace Shortest trace wire next adjacent trace Longest trace wire Shortest trace wire Longest trace wire first adjacent trace Shortest trace wire first adjacent trace Longest trace wire next adjacent trace Shortest trace wire next adjacent trace
TYP.
4.04 1.38 2.20 0.72 1.43 0.48 0.63 0.21 0.31 0.07 0.04 0.01
UNITS
°C/W
Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual
ISO9001
2.27.02
FS6159-01
Auxiliary Motherboard Clock Generator/Buffer
Ordering Information
ORDERING CODE 11920-801 11920-811
FS6159-01
DEVICE NUMBER
PACKAGE TYPE
56-pin (0.300") SSOP 56-pin (0.300") SSOP 56-pin (6.1mm) TSSOP 56-pin (6.1mm) TSSOP
OPERATING TEMPERATURE RANGE
70°C (Commercial) 70°C (Commercial) 70°C (Commercial) 70°C (Commercial)
SHIPPING CONFIGURATION
Tape Reel Tubes Tape Reel Tubes
11920-201 11920-211
Purchase components American Microsystems, Inc., sublicensed Associated Compa2 nies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. Copyright 1999, 2000 American Microsystems, Inc. Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
ISO9001
2.27.02

Auxiliary Motherboard Clock Generator/Buffer Features Figure

Top Searches for this datasheet

Other recent searches