Semiconductor MSM82C37B-5RS/GS/VJS Semiconductor PROGRAMMABLE CON

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Semiconductor MSM82C37B-5RS/GS/VJS Semiconductor PROGRAMMABLE CON

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E2O0016-39-81
Semiconductor MSM82C37B-5RS/GS/VJS
Semiconductor PROGRAMMABLE CONTROLLER
This version: Aug. 1999 MSM82C37B-5RS/GS/VJS Previous version: Jan. 1998
GENERAL DESCRIPTION
MSM82C37B-5RS/GS/VJS, (Direct Memory Access) controller capable highspeed data transfer without intervention used peripheral device microcomputer systems. device features four independent programmable channels. silicon gate CMOS technology, standby current (max.), power consumption (max.) when clock generated. items characteristics compatible with intel 8237A-5.
FEATURES
Maximum operating frequency (Vcc ±10%) High-speed operation very power consumption silicon gate CMOS technology Wide operating temperature range from -40°C +85°C 4-channels independent control request masking programming request priority function DREQ DACK input/output logic inversion address increment/decrement selection Memory-to-Memory Transfers Channel extension cascade connection transfer termination input Intel 8237A-5 compatibility Compatible 40-pin Plastic (DIP40-P-600-2.54): (Product name: MSM82C37B-5RS) 44-pin Plastic (QFJ44-P-S650-1.27): (Product name: MSM82C37B-5VJS) 44-pin Plastic (QFP44-P-910-0.80-2K): (Product name: MSM82C37B-5GS-2K)
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Semiconductor
MSM82C37B-5RS/GS/VJS
CONFIGURATION (TOP VIEW)
Plastic
MEMR MEMW READY HLDA ADSTB RESET DACK2 DACK3 DREQ3 DREQ2 DREQ1 DREQ0 DACK0 DACK1
Plastic
MEMW MEMR
READY HLDA ADSTB RESET
DACK2 DACK3
Plastic
MEMW MEMR
DREQ3
DREQ2
DREQ1
DREQ0
DACK1
DACK0
READY HLDA ADSTB RESET DACK2
DACK3
DREQ3
DREQ0
DACK1
DREQ2
DREQ1
DACK0
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Semiconductor
MSM82C37B-5RS/GS/VJS
BLOCK DIAGRAM
MEMR MEMW READY ADSTB RESET
Base Word Count Register Current Word Count Register Base Address Register Current Address Register
(Terminal Count) Timing Control Circuit
Decrementer
Temporary Word Count Register (16)
Incrementer/Decrementer
Temporary Address Register (16)
Output Buffer Input/Output Buffer
Command Control Circuit
HLDA DREQ0 DACK0 Priority Judgment Circuit Mode Register Command Register Mark Register Request Register Status Register Temporary Register Internal Data Input/Output Buffer
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Semiconductor
MSM82C37B-5RS/GS/VJS
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation Symbol VOUT TSTG Conditions with respect 25°C Rating
MSM82C37B-5RS MSM82C37B-5GS MSM82C37B-5VJS
Unit
-0.5 -0.5 +0.5 -0.5 +0.5 +150
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Input Voltage Input Voltage Symbol Min. -0.5 Typ. Max. +0.8 Unit
CHARACTERISTICS
Parameter Output Voltage Output Voltage Input Leak Current Output Leak Current Average Power Supply Current during Operations Symbol Conditions -1.0 VOUT Input frequency MHz, when RESET V/VCC, HLDA -40°C +85°C Min. Typ. Max. Unit
Power Supply Current Standby Mode
ICCS
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Semiconductor
MSM82C37B-5RS/GS/VJS
CHARACTERISTICS
(Master) Mode
Symbol tAEL tAET tAFAB tAFC tAFDB tAHR tAHS tAHW Item Delay Time from Falling Edge Leading Edge Delay Time from Rising Edge Trailing Edge Delay Time from Rising Edge Address Floating Status Delay Time from Rising Edge Read/Write Signal Floating Status Delay Time from Rising Edge Data Floating Status Address Valid Hold Time Read Signal Trailing Edge Data Valid Hold Time ADSTB Trailing Edge Address Valid Hold Time Write Signal Trailing Edge Delay Time from Falling Edge Active DACK Delay Time from Rising Edge Leading Edge Delay Time from Rising Edge Trailing Edge tASM tASS Time from Rising Edge Address Valid Data Set-up Time ADSTB Trailing Edge Clock High-level Time Clock Low-level Time Cycle Time Min. +85°C, Comments Max. Unit (Note (Note (Note (Note
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Semiconductor (Master) Mode (continued)
Symbol tDCL tDCTR tDCTW tEPS tEPW tFAAB tFAC tFADB tIDH tIDS tODH tODV tSTL tSTT Item Delay Time from Rising Edge Read/Write Signal Leading Edge Delay Time from Rising Edge Read Signal Trailing Edge Delay Time from Rising Edge Write Signal Trailing Edge Delay Time from Rising Edge Valid Leading Edge Set-up Time Falling Edge Pulse Width Delay Time from Rising Edge Address Valid Time from Rising Edge Active Read/Write Signal Delay Time from Rising Edge Data Valid HLDA Valid Set-up Time Rising Edge Input Data Hold Time MEMR Trailing Edge Input Data Set-up MEMR Trailing Edge Output Data Hold Time MEMW Trailing Edge Time from Output Data Valid MEMW Trailing Edge DREQ Set-up Time Falling Edge READY Hold Time Falling Edge READY Set-up Time Falling Edge Delay Time from Rising Edge ADSTB Leading Edge Delay Time from Rising Edge ADSTB Trailing Edge Min. Max.
MSM82C37B-5RS/GS/VJS
Unit
Comments (Note (Note (Note (Note
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Semiconductor Slave Mode
Symbol tRDE tRDF tRSTD tRSTS tRSTW tWWS Item Time from Address Valid Leading Edge Leading Edge Address Valid Set-up Time Trailing Edge Leading Edge Set-up Time trailing edge Data Valid Set-up Time Trailing Edge Address Hold Time Trailing Edge Data Access Time Leading Edge Delay Time Data Floating Status from Trailing Edge Supply Power Leading Edge Set-up time RESET Trailing Edge Time First Active from RESET Trailing Edge RESET Pulse Width Pulse Width Address Hold Time Trailing Edge Trailing Edge Hold Time Trailing Edge Data Hold Time Trailing Edge Pulse Width Min. 2tCY
MSM82C37B-5RS/GS/VJS
+85°C, Comments Max. Unit
Notes: Output load capacitance (pF). MEMW pulse widths (ns) normal writing, 2tCY (ns) extended writing. MEMR pulse widths 2tCY (ns) normal timing, (ns) compressed timing. DREQ DACK signal active level either high. timing chart, DREQ signal been active-high, DACK signal activelow. When executes continuous read write programming mode, interval during which read write pulse becomes active must least open drain output. value given obtained when pull-up resistance connected VCC. Rise time fall time less than Waveform measurement points both input output signals HIGH LOW, unless otherwise noted.
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Semiconductor
MSM82C37B-5RS/GS/VJS
TIMING CHART
Reset Timing
tRSTD tRSTW
RESET tRSTS IOR,
Slave Mode Write Timing
tWWS Input Valid Address Input Valid Data
Slave Mode Read Timing
Input Valid Address tRDE tRDF Output Valid Data
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Semiconductor Transfer Timing
MSM82C37B-5RS/GS/VJS
DREQ
HLDA
tAEL tAET
tSTL tSTT
ADSTB
tASS tFADB tAHS
tFAAB
tAFDB tAHW
tASM tAFAB
tAHR tDCL tDCTR
DACK
tFAC
IOR, MEMR
tDCL tDCTW
tAFC
IOW, MEMW Internal (Output) External (Input)
(Extended Write)
tEPS tEPW
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Semiconductor Memory Memory Transfer Timing
tSTL tSTT tSTL
MSM82C37B-5RS/GS/VJS
tSTT
ADSTB
tFAAB tAHS tASM tAHS tAFAB
tFADB
Valid Address
tAFDB
Valid Address
tAFDB
tFAC
tDCL
Data Input tDCTR tIDS
tFADB tIDH
Data Output tODV tODH tAFC tDCL tDCTW tAFC
MEMR
tFAC
MEMW
Internal (Output) External (Input)
tEPS tEPW
tEPS tEPW
Ready Timing
tDCL tDCTR
IOR, MEMR
tDCL tDCL tDCTW
IOW, MEMW
(Extended Write)
READY
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Semiconductor Compressed Transfer Timing
MSM82C37B-5RS/GS/VJS
tASM
tASM
tDCL
Valid Address
tDCTR tDCL tDCTR
IOR, MEMR
tDCTW tDCL tDCTW
IOW, MEMW
READY
Internal (Output) External (Input)
tEPS tEPW
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MSM82C37B-5RS/GS/VJS
FUNCTIONS
Symbol RESET Name Power Ground Clock Chip Select Reset Input/Output Input Input Input power supply Ground connection. Control MSM82C37B-5 internal operations data transfer speed. active-low input signal used select MSM82C37B-5 device idle cycle. RESET active-high asynchrounous input signal used clear command, status, request, temporary registers, first/last F/F, mask register. MSM82C37B-5 enters idle cycle following RESET. read write pulse width extended accomodate slow access memories devices when this input switched level. Note this input must change within prescribed set-up/hold time. HLDA active-high input signal used indicate that system control been released when hold request recieved CPU. DREQ asynchronous transfer request input signals. Although these pins switched active-high reset, they programmed become active-low. requests received accordance with prescribed order priority. DREQ must held until DACK becomes active. bidirectional three-state signals connected system data bus, which used input/output MSM82C37B-5 internal registers during idle cycles, output eight higher order bits transfer addresses during active cycles. Also used input output transfer data during memorymemory transfers. active-low bidirectional three-state signal used input control signal reading MSM82C37B-5 internal registers during idle cycles, output control signal reading device transfer data writing transfers during active cycles. active-low bidirectional three-state signal used input control signal writing MSM82C37B-5 internal registers during idle cycles, output control signal writing device transfer data writing transfers during active cycles. Function
READY
Ready
Input
HLDA
Hold Acknowledge
Input
DREQ0 DREQ3
Request Channels
Input
Data
Input/Output
Read
Input/Output
Write
Input/Output
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FUNCTIONS (continued)
Symbol Name Process Input/Output Input/Output Function active-low bidirectional three-state signal. Unlike other pins, this N-channel open drain. During operations, low-level output pulse obtained from this channel word count changes from 0000H FFFFH. transfers terminated pulling input level. Both these actions called terminal count (TC). When internal external generated, MSM82C37B-5 terminates transfer resets request. When used, necessary hold high level pull-up resistor prevent input error. Also note that function cannot satisfied cascade mode. bidirectional three-state signals used input signals specifying MSM82C37B-5 internal register accessed during idle cycles, output four lower order bits transfer address during active cycles. three-state signals used output four higher order bits transfer address during active cycles. active-high signal used output hold request system data control purposes. After become active, least clock cycle required before HLDA becomes active. DACK output signals used indicate that transfer peripheral devices been permitted. (Available each channel.) Although these pins switched active-low when reset, they programmed become active-high. Note that there DACK output signal during memory-memory transfers. active-high ouput signal used indicate that output signals sent from MSM82C37B-5 system valid. addition enabling external latch hold eight higher order bits transfer address, this signal also used disable other system buffers. ADSTB active-high signal used strobe eight higher order bits transfer address external latch. MEMR active-low three-state output signal used control signal reading data from memory during read transfers memory-memory transfers. MEMW active-low three-state output signal used control signal writing data into memory during write transfers memory-memory transfers.
Address
Input/Output
Address Hold Request
Output Output
DACK0 DACK3
Acknowledge Channels
Output
Address Enable
Output
ADSTB MEMR
Address Strobe Memory Read
Output Output
MEMW
Memory Write
Output
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RESET
Internal/ external Request HLDA Memory-Memory Transfer Setting External Compressed Timing Verify READY Internal/ External Single Transfer HLDA External Request Demand Transfer Internal/ External HLDA External Setting READY External Setting
READY
Carry Borrow
Note: (Active) (Inactive)
Figure Operation State Transition Diagram
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MSM82C37B-5RS/GS/VJS
OUTLINE FUNCTIONS
MSM82C37B-5 consists five blocks three logic sections, internal register section, counter section. logic sections include timing control block where internal timing external control signals generated, command control block where each instruction from decoded, priority decision block where order channel priority determined. purpose internal register section hold internal states instructions from CPU, while counter section computes addresses word counts.
DESCRIPTION OPERATIONS
MSM82C37B-5 operates cycles (called idle active cycles) which divided into independent states. Each state commenced clock falling edge continues single clock cycle. transition from state next operations outlined Figure
Idle Cycle idle cycle entered from state when there valid request MSM82C37B-5 channel. During this cycle, DREQ inputs monitored during each cycle. When valid request then received, active cycle commenced. HLDA inputs level, programming state started with MSM82C37B-5 reading writing executed IOW. Programming details described later.
Active Cycle request received unmasked channel while MSM82C37B-5 idle cycle, software DREQ generated, changed high level commence active cycle. initial state active cycle state which repeated until HLDA input from changed high level. (But because internal operational reasons, minimum clock cycle required HLDA changed high level after become high level. That state must repeated least twice.) After HLDA been changed high level, state proceeds operational states thru during I/O-memory transfers, operational states thru thru during memory-memory transfers. memory device cannot accessed within normal timing, state (wait state) inserted READY input extend timing.
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DESCRIPTION TRANSFER TYPES
MSM82C37B-5 transfers between memory devices, transfers between memory devices. three types transfers between memory devices read, write, verify.
I/O-Memory Transfers operational states during I/O-memory transfer state, output changed high level indicate that control signal from MSM82C37B-5 valid. eight lower order bits transfer address obtained from thru eight higher order bits obtained from thru DB7. ADSTB output changed high level this time eight higher order bits external address latch, DACK output made active channel where request acknowledged. Where there change eight higher transfer address during demand block mode transfers, however, state omitted. state, MEMR output changed level. state, MEMW changed level. Where compressed timing used, however, state omitted. states memory input/output timing control states. state, IOR, IOW, MEMR, MEMW changed high level, word count register decremented while address register incremented decremented) This completes transfer word. Note that I/O-memory transfers, data transferred directly without being taken MSM82C37B-5. differences three types I/O-memory transfers indicated below.
Read Transfer Data transferd from memory device changing MEMR level. MEMW kept high level during this time.
Write Transfer Data transferred from device memory changing MEMW level. MEMR kept high level during this time. Note that writing reading these write read transfers with respect memory.
Verify Transfer Although verify transfers involve same operations write read transfers (such transfer address generation input responses),they fact pseudo transfers where memory reading/writing control signals kept inactive. READY inputs disregarded verify transfers.
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Semiconductor Memory-memory Transfer
MSM82C37B-5RS/GS/VJS
Memory-memory transfers used transfer data blocks from memory area another. Memory-memory transfers require total eight states complete single transfer four states (S11 thru S14) reading from memory, four states (S21 thru S24) writing into memory. These states similar I/O-memory transfer states, distinguished using two-digit numbers. memory-memory transfers, channel used reading data from source area, channel used writing data into destination area. During initial four states, data specified channel address read from memory when MEMR made active, taken MSM82C37B-5 temporary register. Then during latter four states, data temporary register written address specified channel This completes transfer byte data. With channel channel addresses subsequently incremented decremented) channel word count decremented this operation repeated. transfer terminated when word count reaches FFFF(H) from 0000(H), when input applied from external source. Note that there DACK output signal during this transfer. following preparations programming requiring enable memory-memory transfers started.
Command Register Setting Memory-memory transfers enabled setting Channel address held transfers setting This setting used enable 1-word contents source area written into entire destination area.
Mode Register Setting transfer type destination disregarded channels Memory-memory transfers always executed block transfer mode.
Request Register Setting Memory-memory transfers started setting channel request bit.
Mask Register Setting Mask bits channels prevent selection other channel apart from channel
Word Count Register Setting channel word count validated, while channel word count disregarded. order autoinitialize both channels, necessary write same values into both word count registers.
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DESCRIPTION OPERATION MODES
Single Transfer Mode single transfer mode, only word transferred, addresses incremented decremented) while word count decremented then changed level return control CPU. DREQ remains active after completion transfer, changed level. After HLDA changed level CPU, then changes back high level commence fresh cycle. this reason, machine cycle inserted between cycles CPU.
Block Transfer Mode Once transfer started block mode, transfer continued until terminal count (TC) status reached. DREQ remains active until DACK becomes active, transfer continued even DREQ becomes inactive.
Demand Transfer Mode transfer continued demand transfer mode until DREQ longer active, until status reached. During transfer, intermediate address word count values held current address current word count registers. Consequently, transfer suspended result DREQ becoming inactive before status reached, DREQ that channel then made active again, suspended transfer resumed.
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Semiconductor Cascade Transfer Mode
MSM82C37B-5RS/GS/VJS
When transfers involving more than four channels required, connecting multiple number MSM82C37A-5 devices cascade connection (see Figure enables simple system extension. This mode setting first stage MSM82C37B-5 channel cascade mode. DREQ DACK lines first stage MSM82C37B-5 channel cascade mode connected HLDA lines respective MSM82C37B-5 devices second stage. first stage MSM82C37B-5 DACK signal must active-high, DREQ signal active-low. Since first stage MSM82C37B-5 only used functionally determining order priority each channel when cascade mode set, only DREQ DACK used-all other inputs disregarded. since system hung transfer activated software DREQ, software DREQ channels where cascade mode been set. addition dual stage cascade connection shown Figure triple stage cascade connections possible with second stage also cascade mode.
DREQ
HLDA DREQ DACK Stage MSM82C37B-5 HLDA DREQ
DREQ DACK
HLDA
DACK
DACK
Stage MSM82C37B-5
Figure MSM82C37B-5 Cascade Connection System
Autoinitialize Mode Setting mode register enables autoinitialization that channel. Following generation, autoinitialize involves writing base address base word count register values respective current address current word count registers. same values current registers written base registers CPU, changed during transfers. When channel been autoinitialize, that channel used second transfer without involving without mask being reset after generation.
Priority Modes MSM82C37B-5 makes priority decision modes, acknowledges channel highest priority among requesting channels. 19/33
Semiconductor Fixed Priority Mode
MSM82C37B-5RS/GS/VJS
fixed priority mode, channel highest priority, followed channels that order.
Rotating Priority Mode rotating priority mode, order priority changed that channel where current transfer been completed given lowest priority. This prevent channel from monopolizing system. fixed priority regained immediately after resetting.
Table MSM82C37B-5 Priority Decision Modes Priority Mode Service Terminated Channel Highest Order Priority Next Lowest Fixed Rotating
Compressed Timing Setting MSM82C37B-5 compressed timing mode enables state used extension read pulse access time omitted permitted system structure) three clock cycle transfers. state omitted, read pulse width becomes same write pulse width with address updated read write operation executed This mode disregarded transfer memory-memory transfer, transfer. Extended Writing When this mode set, MEMW signal which normally appears during state obtained during state, thereby extending write pulse width. purpose this extended write pulse enable system accomodate memories devices where access time slower. Although pulse width also extended using READY, that involves insertion state increase number states.
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MSM82C37B-5RS/GS/VJS
DESCRIPTION INTERNAL REGISTERS
Current Address Register Each channel equipped with 16-bit long current address register where transfer address held during transfers. register value incremented decremented) each cycle. Although this register bits long, accessed MSM82C37B-5 eight bits time, therefore necessitating successive 8-bit (lower higher order bits) reading writing operations using internal first/last flip-flops. When autoinitialize been set, register automatically initialized original value after
Current Word Count Register Each channel also equipped with bit-long current word count register where transfer count held during transfers. register value decremented each cycle. When word count value reaches FFFF(H) from 0000(H), generated. Therefore, word count value which less than actual number transfers must set. Since this register also bits long, accessed first/last flip-flops control same address register. autoinitialize been set, register automatically initialized original value after
Base Address Register Base Word Count Register Each channel equipped with 16-bit long base address register base word count register where initial value each current register held. same values written each base register current register CPU. contents current register made ready CPU, content base register cannot read.
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Semiconductor Command Register
MSM82C37B-5RS/GS/VJS
This 8-bit write-only register prescribes operations MSM82C37B-5 channels. outline bits given Figure When controller disabled setting there output even request active. DREQ DACK signals active high active setting DB7.
Memory-Memory Transfer Disabled Memory-Memory Transfer Enabled Channel Address Hold Disabled Channel Address Hold Enabled (Invalid when "0") Controller Enabled Controller Disabled Normal Timing Compressed Timing (Invalid when "1") Fixed Priority Rotating Priority Normal Write Pulse Width Extended Write Pulse Width DREQ Sense Active DREQ Sense Active DACK Sense Active DACK Sense Active
Figure Command Register
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Semiconductor Mode Register
MSM82C37B-5RS/GS/VJS
Each channel equipped with 6-bit write-only mode register, which decided setting DB0, which channel written when writing from programming status. description outlined Figure This register cleared Reset Master Clear instruction.
Channel Selected Channle Selected Channel Selected Channle Selected Verify Transfer Write Transfer Read Transfer Disabled (Invalid When "11")
Auto Initialize Disabled Auto Initialize Enabled Address Increment (+1) Selected Address Decrement (-1) Selected Demand Transfer Mode Selected Single Transfer Mode Selected Block Transfer Mode Selected Cascade Mode Selected
Figure Mode Register
Request Register addition using DREQ signal, MSM82C37B-5 request transfers software means. This involves setting request request register. Each channel corresponding request request register, order priority these bits determined priority decision circuit irrespective mask register. transfers acknowledged accordance with decided order priority. request bits reset when reached, when request certain channel been received, other request bits cleared. When memory-memory transfer commenced, channel request set. description outlined Figure
Channel Selected Channel Selected Channel Selected Channel Selected Request Cleared Request Used Figure Request Register
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Semiconductor Mask Register
MSM82C37B-5RS/GS/VJS
This register used disabling enabling transfers each channel. Each channel includes corresponding mask mask register, each when reached autoinitialize mode. This mask register different ways. method setting/resetting register each channel outlined Figure 6(a), while method setting/resetting register channels once outlined Figure 6(b).
Channel Selected Channel Selected Channel Selected Channel Selected Mask Cleared Mask
Used
Single Mask Register (Setting/Resetting Each Channel)
Channel Mask Cleared Channel Mask Channel Mask Cleared Channel Mask Channel Mask Cleared Channel Mask Channel Mask Cleared Channel Mask Used
Mask Register (Setting/Resetting Channels Once)
Figure Mask Register
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Semiconductor Status Register
MSM82C37B-5RS/GS/VJS
This register read-only register used reading MSM82C37B-5 status. four higher order bits indicate transfer request status each channel, being when DREQ input signal active. four lower order bits indicate whether corresponding channel reached not, being when status reached. These four lower order bits reset status register reading, RESET input master clearing. description each outlined Figure
Channel Reached Channel Reached Channel Reached Channel Reached Channel Reached Channel Reached Channel Reached Channel Reached Channel Requesting Channel Requesting Channel Requesting Channel Requesting Channel Requesting Channel Requesting Channel Requesting Channel Requesting Figure Status Register
Temporary Register temporary register register where transfer data held temporarily during memorymemory transfers. Since last item data transferred held after completion transfer, this item read CPU.
Software Command MSM82C37B-5 equipped with software commands executing special operations ensure proper programming. Software command irrespective data contents.
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Semiconductor Clear First/Last Flip-Flop
MSM82C37B-5RS/GS/VJS
16-bit address word count registers read written consecutive operations involving eight bits each (higher lower order bits) under data port control. fact that lower order bits accessed first MSM82C37B-5, followed accessing higher order bits, discerned internal first/last flip-flop. This command resets first/last flip-flop with eight lower order bits being accessed immediately after execution.
Master Clear same operation when hardware RESET input applied. Thus command clears contents command, status (four lower order bits), request, temporary registers, also clears first/last flip-flop, sets mask register. This command followed idle cycle.
Clear Mask Register When this command executed, mask bits channels cleared enable reception transfers.
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PROGRAMMING
MSM82C37B-5 switched programming status when HLDA input both level. this state, changed level with held high level enable reading CPU, else changed level while held high level enable writing CPU. list command codes reading from MSM82C37B-5 given Table list command codes writing MSM82C37B-5 given Table Note: transfer request received from device during MSM82C37B5 programming, that transfer commenced prevent proper programming. prevent this interference, channel must masked, controller disabled command register, system prevent DREQ becoming active during programming.
Table List MSM82C37B-5 Read Commands Internal First/Last Flip/Flop Status Register Temporary Register Output Data Invalid Channel Current Word Count Register Channel Channel Current Word Count Register Current Address Register Current Word Count Register Current Address Register Channel
Read Data Current Address Register Current Word Count Register Current Address Register Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits
Other Combinations
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Table List MSM82C37B-5 Write Commands Internal First/Last Flip-Flop Channel Current Base Word Count Registers Command Register Request Register Single Mask Register Mode Register Clear First/Last Flip-Flop (Software Command) Master Clear (Software Command) Clear Mask Register (Software Command) Mask Register Channel Channel Current Base Word Count Registers Current Base Address Registers Current Base Word Count Registers Current Base Address Registers Channel
Written Data Current Base Address Registers Current Base Word Count Registers Current Base Address Registers Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits Lower Order Bits Higher Order Bits
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NOTICE REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES
conventional speed devices replaced high-speed devices shown below. When want replace your speed devices with high-speed devices, read replacement notice given next pages.
High-speed device (New) M80C85AH M80C86A-10 M80C88A-10 M82C84A-2 M81C55-5 M82C37B-5 M82C51A-2 M82C53-2 M82C55A-2
Low-speed device (Old) M80C85A/M80C85A-2 M80C86A/M80C86A-2 M80C88A/M80C88A-2 M82C84A/M82C84A-5 M81C55 M82C37A/M82C37A-5 M82C51A M82C53-5 M82C55A-5
Remarks 8-bit 16-bit 8-bit Clock generator RAM, I/O, timer controller USART Timer
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Semiconductor
Differences between MSM82C37A-5 MSM82C37B-5
MSM82C37B-5RS/GS/VJS
Manufacturing Process These devices Si-CMOS process technology have same chip size. Function These devices have same logics except changes characteristics listed (3-2). Electrical Characteristics 3-1) Characteristics These devices have same characteristics. 3-2) Characteristics
Parameter Clock Time automatic initialization) Clock Time (Other than above)
Symbol
MSM82C37A-5 minimum minimum
MSM82C37B-5 minimum minimum
shown above, MSM82C37A-5 cannot satisfy clock time automatic initialization). other hand, MSM82C37B-5 satisfy clock time operation status. other characteristics, both MSM82C37A-5 MSM82C37B-5 identical. Package MSM82C37A-5 employed PLCC package having OKI's original layout, which compatible AMD's PLCC products which been commercialized before OKI's products. meet overseas customers needs, developed AMD-compatible PLCC productsMSM82C37B-VJS. OKI's FLAT package identical those AMD.
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Semiconductor
MSM82C37B-5RS/GS/VJS
PACKAGE DIMENSIONS
(Unit
DIP40-P-600-2.54
Package material Lead frame material treatment Solder plate thickness Package weight
Epoxy resin alloy Solder plating more 6.10 TYP.
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MSM82C37B-5RS/GS/VJS
(Unit
QFJ44-P-S650-1.27
Mirror finish
Package material Lead frame material treatment Solder plate thickness Package weight
Epoxy resin alloy Solder plating more 2.00 TYP.
Notes Mounting Surface Mount Type Package SOP, QFP, TSOP, TQFP, LQFP, SOJ, (PLCC), SHP, surface mount type packages, which very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
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MSM82C37B-5RS/GS/VJS
(Unit QFP44-P-910-0.80-2K
Mirror finish
Package material Lead frame material treatment Solder plate thickness Package weight
Epoxy resin alloy Solder plating more 0.41 TYP.
Notes Mounting Surface Mount Type Package SOP, QFP, TSOP, TQFP, LQFP, SOJ, (PLCC), SHP, surface mount type packages, which very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
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E2Y0002-29-62
NOTICE
information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission. MS-DOS registered trademark Microsoft Corporation.
Copyright 1999 Electric Industry Co., Ltd.
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Semiconductor MSM82C37B-5RS/GS/VJS Semiconductor PROGRAMMABLE CON

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