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Two-Way/Four Motherboard Clock Generator/Buffer Features Fig


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FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Features
Figure Block Diagram
XOUT ISEL_0:1 IREF PWR_DWN# SS_EN# SEL133/100# SEL_A:B APICON
VDD_A
Generates Host Memory clocks required 2-way 4-way multi-processor (MP) clockpartitioned platforms, including: differential current-mode Host clock pairs 3.3V Memory Reference clocks 66.67MHz 14.318MHz 3.3V Reference clocks FS6159 device Three optional 33.3MHz 1.8V APIC clocks Control current-mode Host clocks IREF current programming ISEL_0:1 current multiplier pins Optional APIC clocks enabled APICON input (see Table Pins 21-23 configuration) Host clock frequency selection SEL_A, SEL_B, SEL133/100# pins Active-low PWR_DWN# signal allows complete clock cycle each clock outputs then shuts down crystal oscillator, PLL, disables outputs Spread-spectrum modulation (-0.5% 31.5kHz) Host, Memory, APIC, 66MHz Reference clocks, enabled SS_EN# input Supports test mode tristate output control facilitate board testing Available 48-pin SSOP TSSOP
Crystal Oscillator
adjust
VDD_R
14REF
VSS_R
VDD_H
HOST_P1:6 HOST_N1:6
VSS_H VDD_66
66REF Control
VSS_66 VDD_M
MREF_P MREF_N
VSS_M
APIC_0:2
FS6158
VSS_A
optional
Figure Configuration
VSS_R 14REF VDD_R XOUT VDD_R APICON VDD_H HOST_P1 HOST_N1 VSS_H HOST_P2 HOST_N2 VDD_H HOST_P3 HOST_N3 VSS_H HOST_P4 HOST_N4 VDD_H HOST_P5 HOST_N5 VSS_H HOST_P6 HOST_N6 VDD_H IREF VSS_I VDD_I
Pair
Table Clock Parameters
CLOCK GROUP HOST_P HOST_N MREF_P MREF_N 66REF 14REF APIC (optional) PINS 3.3V VDD_H SUPPLY VOLTAGE SUPPLY GROUP FREQ. (MHz) 133.33 100.00 66.67 50.00 66.67 14.318 33.33 PHASE 180° 180° SKEW (MAX) 100ps Pair Pair
VSS_R VDD_M MREF_P MREF_N VSS_M VDD_66 66REF VSS_66 SEL133/100# ISEL_0 ISEL_1 VDD_A VSS_A SEL_A APIC_0 SEL_B APIC_1 SS_EN# APIC_2 PWR_DWN#
Pair Pair
FS6158-01
Pair
3.3V 3.3V 3.3V 1.8V
VDD_M VDD_66 VDD_R VDD_A
Intel Pentium registered trademarks Intel Corporation. Lexmark trademark Lexmark International, Inc. Non-linear spread spectrum modulation profile licensed under Patent 5488627, Lexmark International, Inc. This document contains information preproduction product. Specifications information herein subject change without notice.
Pair Pair
ISO9001
2.26.02 IntWBY
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Table Descriptions
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active-low
TYPE
NAME APICON APIC_0 SEL_A APIC_1
DESCRIPTION Enables (logic-high) disables (logic-low) optional 1.8V APIC clocks three optional APIC clocks, enabled disabled APICON frequency select inputs, used combination with SEL133/100#. Input signal levels referred VDD_H (3.3V) APICON low, VDD_A (1.8V) APICON high. three optional APIC clocks, enabled disabled APICON frequency select inputs, used combination with SEL133/100#. Input signal levels referred VDD_H (3.3V) APICON low, VDD_A (1.8V) APICON high. three optional APIC clocks, enabled disabled APICON Active-low spread spectrum enable turns spread spectrum modulation clocks. Input levels referred VDD_H (3.3V) APICON low, VDD_A (1.8V) APICON high. 14.318MHz clock output, provided reference clock companion clock device 66.67MHz clock output, provided reference clock companion clock device fixed precision resistor from this ground provides reference current used differential current-mode HOST clock outputs logic setting these pins selects multiplying factor IREF reference current HOST pair outputs Host clock pair pairs current-steering differential current-mode outputs. current established reference current IREF multiplying factor ISEL_0:1 Host clock pair pairs current-steering differential current-mode outputs Host clock pair pairs current-steering differential current-mode outputs Host clock pair pairs current-steering differential current-mode outputs Host clock pair pairs current-steering differential current-mode outputs Host clock pair pairs current-steering differential current-mode outputs clock pair outputs provided reference clock memory clock driver clock (180° phase with MREF_P) pair outputs provided reference clock memory clock driver Asynchronous active-low LVTTL power-down signal shuts down oscillator PLL, puts clocks state. Complete clock cycles outputs will occur before shut down begins. Selects 133MHz 100MHz Host clock frequency 3.3V core power supply 1.8V power supply optional APIC clocks 3.3V supply pins 21-23 3.3V power supply 66REF clock output 3.3V power supply differential HOST clock outputs 3.3V power supply IREF current reference input 3.3V power supply MREF clock outputs 3.3V power supply 14REF clock output crystal oscillator Core Ground Ground 66REF clock output Ground APIC clock outputs Ground differential HOST clock outputs Ground IREF current reference input Ground MREF clock outputs Ground 14REF clock output crystal oscillator 14.318MHz crystal oscillator input 14.318MHz crystal oscillator output
SUPPLY VDD_R VDD_A VDD_A, VDD_H VDD_A VDD_A, VDD_H VDD_A VDD_A, VDD_H VDD_R VDD_66 VDD_I VDD_66 VDD_H VDD_H VDD_H VDD_H VDD_H VDD_H VDD_M VDD_M VDD_I VDD_66 VDD_R VDD_R
2.26.02
SEL_B APIC_2
SS_EN# 14REF 66REF IREF ISEL_0 ISEL_1 HOST_P1 HOST_N1 HOST_P2 HOST_N2 HOST_P3 HOST_N3 HOST_P4 HOST_N4 HOST_P5 HOST_N5 HOST_P6 HOST_N6 MREF_P MREF_N PWR_DWN# SEL133/100# VDD_A VDD_66 VDD_H VDD_I VDD_M VDD_R VSS_66 VSS_A VSS_H VSS_I VSS_M VSS_R XOUT
ISO9001
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Programming Information
Table Function/Clock Enable Configuration
CONTROL INPUTS PWR_DWN#
CLOCK OUTPUTS (MHz) SEL_B HOST_P1:6 100.00 100.00 reserved tristate 133.33 reserved reserved XIN÷2 IREF HOST_N1:6 100.00 100.00 reserved tristate 133.33 reserved reserved XIN÷2 tristate MREF_P, MREF_N 50.00 reserved tristate 66.67 reserved reserved XIN÷4 66REF 66.67 reserved tristate 66.67 reserved reserved XIN÷4 APIC_0:2 (optional) 33.33 reserved tristate 33.33 reserved reserved XIN÷8 14REF 14.318 reserved tristate 14.318 reserved reserved
SEL133/100#
SEL_A
Certain clock outputs disabled through combination SEL_A, SEL_B, SEL133/100# logic states defined Table Enabled clocks will continue while disabled clocks stopped low. Note that clocks disabled while active, glitches occur.
Table Synthesis Error
CLOCK HOST_P1:6, HOST_N1:6 MREF_P, MREF_N 66REF APIC_0:2
ACTUAL (MHz) 99.9963 133.3072 49.9982 66.6536 66.6642 33.3321 DEVIATION (ppm) -36.657 -195.924 -36.657 -195.924 -36.657 -36.657
HOST Buffer Current Control
TARGET (MHz) 100.0000 133.3333 50.0000 66.6667 66.6667 33.3333
current supplied HOST outputs controlled parameters: value programming resistor from IREF ground (VSS), multiplier factor determined logic setting ISEL_0 ISEL_1 pins.
Current Reference
48MHz clock required +167ppm from 48.000MHz conform standards. Spread spectrum disabled
Table APICON Control
APICON FREQUENCY SELECT CONTROL APIC CLOCKS SEL_A Input (LVTTL) APIC_0 Output SEL_A Latched Input SEL_B Input (LVTTL) APIC_1 Output SEL_B Latched Input SS_EN# Input (LVTTL) APIC_2 Output SS_EN# Latched Input
HOST output current mirrored scaled copy reference current flowing through programming resistor IREF pin. Conceptually, circuit given Figure shows mirror current generated. voltage that appears IREF one-third voltage VDD_I pin. reference current
VDD_I RIREF
Current Scaling
mirrored reference current increased adding more copies mirror current together. additional current controlled logic settings ISEL_0 ISEL_1 pins.
ISO9001
2.26.02
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Table Current Multiplier
ISEL_0 ISEL_1 MULTPLIER IREF IREF IREF IREF
Table HOST Buffer Clock Outputs
Output Voltage 3.30 3.14 2.97 2.81 2.64 2.48 HIGH DRIVE CURRENT (mA) PRIMARY SYSTEM CONFIGURATION MIN. 0.00 -3.03 -5.66 -7.87 -9.67 -11.05 -11.98 -12.52 -12.77 -12.91 -12.99 -13.04 -13.07 -13.08 -13.09 -13.11 -13.12 -13.13 -13.13 -13.14 -13.15 TYP. 0.00 -4.22 -7.68 -10.30 -11.91 -12.56 -12.85 -13.07 -13.26 -13.42 -13.54 -13.64 -13.70 -13.73 -13.75 -13.76 -13.78 -13.79 -13.80 -13.81 -13.82 MAX. 0.00 -5.76 -9.86 -11.85 -12.45 -12.84 -13.16 -13.45 -13.72 -13.96 -14.17 -14.36 -14.52 -14.64 -14.71 -14.74 -14.76 -14.78 -14.80 -14.82 -14.83
Figure Current Reference Circuit
VDD_I (3.3V)
1.1V
Additional Mirror Current Mirror Current ISEL_0:1
2.31 2.14 1.98 1.81 1.65 1.48
IREF Reference Current IREF RIREF
HOST_N
HOST_P
1.32 1.15 0.99 0.82 0.66 0.49
Table HOST Current Selection
PROGRAM RESISTOR RIREF (1%) (1%) (1%) (1%) (1%) (1%) (1%) (1%) REFERENCE CURRENT CURRENT MULTIPLIER IREF 2.32mA 2.32mA 2.32mA 2.32mA IREF IREF IREF IREF IREF IREF IREF IREF TRACE IMPEDANCE OUTPUT VOLTAGE 0.71V 0.59V 0.85V 0.71V 0.56V 0.47V 0.99V 0.82V 0.75V 0.62V 0.90V 0.75V 0.60V 0.50V 1.05V 0.84V
0.33 0.16 0.00
Output Voltage
Output Current (mA)
NOTE: Shaded indicates Primary System Configuration
Data this table represents nominal characterization data only
ISO9001
2.26.02
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Power Management
Table Latency Table
SIGNAL SIGNAL STATE Power Power Output: Device: LATENCY MIN. clocks 14REF clocks MAX. clocks 14REF clocks
PWR_DWN# signal asynchronous, active-low LVTTL input that places device power inactive state without removing power from device. internal clocks turned off, clock outputs held low. Since PWR_DWN# asynchronous, signal synchronized internally each individual clock. shown Figure falling-rising-falling edge sequence individual clock output required before that clock output disabled low. This edge sequence ensures that complete clock cycle will occur before clock stops.
PWR_ DWN#
Upon release PWR_DWN# (power-up), external circuitry should allow minimum lock before enabling clocks.
Figure PWR_DWN# Timing
Clock (internal) PWR_DWN# Clock (output) After 14REF output shuts off. Crystal Oscillator
Shaded regions Crystal Oscillator waveforms indicate that clock valid Crystal Oscillator active.
until clock valid
Dual Function Pins
Figure Programming
Termination Resistor Device Solder Pads
Several pins this device serve dual function input/output pins. During initial application device, this type functions input pin. Upon completion power-up, logic state present latched internally, converted output driver. external pull-down resistor ground required logic pull-up resistor clock output required logic high. resistor presents insignificant load output driver that should affect output clock. Note that latching logic state occurs only application chip supply voltage (VDD). logic state latched PWR_DWN# signal used power-down device with still applied.
Clock Trace
Programming Resistor
Ground Power
ISO9001
2.26.02
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
MIN. VSS-0.5 VSS-0.5 VSS-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION Core (VDD) Supply Voltage Clock Buffers (VDD_66, VDD_H, VDD_I, VDD_M, VDD_R) APIC Clock Buffers (VDD_A) Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance fXTAL XIN, XOUT pins MREF_P, MREF_N Load Capacitance APIC_0:2 66REF 14REF Load Resistance HOST_P1 HOST_P6, HOST_N1 HOST_N6 MIN. 3.135 3.135 1.65 14.316 13.5 14.318 TYP. MAX. 3.465 3.465 1.95 14.32 22.5 UNITS
ISO9001
2.26.02
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Table Electrical Specifications
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Negative currents indicate current flows device.
PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs Supply Current, Static
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
IDDs
fHOST 133MHz; supplies 3.465V, RIREF= 475, IREF PWR_DWN# low, supplies 3.465V, RIREF= 475, IREF VSS-0.3 VDD+0.3
Digital Inputs (PWR_DWN#, ISEL_0, ISEL_1, SEL133/100#) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Crystal Oscillator Feedback (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance Input Loading Capacitance Crystal Oscillator Drive (XOUT) High Level Output Source Current Level Output Sink Current Current Reference (IREF) Bias Voltage Short Circuit Output Source Current load VDD_M, VDD_R, VDD_66 3.135V, 1.0V VDD_M, VDD_R, VDD_66 3.465V, 3.135V VDD_M, VDD_R, VDD_66 3.135V, 1.95V VDD_M, VDD_R, VDD_66 3.465V, 0.4V Measured 1.65V, output driving Measured 1.65V, output driving high shorted 30s, max. 3.3V; shorted 30s, max. (XIN) 3.3V, (XIN) 3.3V -8.0 CL(xtal) CL(XIN) 3.3V seen external crystal connected XOUT seen external clock driver XOUT; unconnected 13.5 22.5
MREF_P, MREF_N, 14REF, 66REF Clock Outputs (Type Clock Driver) High Level Output Source Current Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOSH IOSL
ISO9001
2.26.02
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Table Electrical Specifications, continued
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Negative currents indicate current flows device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
HOST_P1:4, HOST_N1:4 Clock Outputs (Type Clock Buffer) Crossover Voltage High-Level Output Source Current Output Source Current Tolerance Output Impedance Tristate Output Current VDD_A 3.3V, LVTTL Input (APICON=0) VDD_A 1.8V, Latched Input (APICON=1) VDD_A 3.3V, LVTTL Input (APICON=0) VDD_A 1.8V, Latched Input (APICON=1) VDD_A 1.8V, 1.4V VDD_A 1.8V, 0.4V Measured 0.7V, output driving Measured 0.7V, output driving high shorted 30s, max. 1.8V; shorted 30s, max. 33.2, 49.9, RIREF 475, IREF 0.65V, RIREF 475, IREF 0.74V, RIREF 475, IREF 3.30V, over settings Table VDD_I=3.3V±5%, over settings Table VO/IO, where 1.0V, VSS, RIREF 475, IREF 3000 12.9 14.9 %VOH %IOH
SEL_A APIC_0, SEL_B APIC_1, SS_EN# APIC_3 Latched Inputs Clock Outputs (1.8V Clock Buffer) High-Level Input Voltage Input Low-Level Input Voltage Input Leakage Current High Level Output Source Current Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current Output IOSH IOSL 1.17 VSS-0.3 VSS-0.3 VDD+0.3 VDD+0.3 0.63
ISO9001
2.26.02
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Table Timing Specifications
Unless otherwise stated, power supplies 3.3V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Spread spectrum modulation disabled except Rise/Fall time measurements.
PARAMETER Overall Spread Spectrum Modulation Frequency Spread Spectrum Modulation Index Tristate Enable Delay Tristate Disable Delay Clock Stabilization power-up)
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
tDZL, tDZH tDLZ, tDHZ tSTB
SS_EN# SS_EN# SEL_A:B=00, SEL133/100#=0 SEL_A:B=11, SEL133/100#=0 PWR_DWN#
31.5 -0.5
HOST_P1:4, HOST_N1:4 Clock Outputs Clock Skew Duty Cycle Jitter, Long Term (y()) Jitter, Period (peak-peak) Rise Time Rise/Fall Time Matching* MREF_P, MREF_N Clock Outputs Duty Cycle Jitter, Long Term (y()) Jitter, Period (peak-peak) Rise Time Fall Time tj(LT) tj(P) Ratio high pulse width clock period, measured 1.5V rising edges 500µs apart 1.5V relative ideal clock, CL=30pF From rising edge rising edge 1.5V, CL=30pF Measured 0.4V 2.4V; CL=10pF Measured 0.4V 2.4V; CL=30pF Measured 2.4V 0.4V; CL=10pF Measured 2.4V 0.4V; CL=30pF tsk(o) tj(LT) tj(P) HOST pair HOST pair RIREF 475, IREF, 33.2, 49.9 Ratio high pulse width clock period RIREF 475, IREF, RS=33.2, RP=49.9 rising edges 500µs apart relative ideal clock, RIREF 475, IREF, 33.2, 49.9 Rising edge rising edge VX,, RIREF 475, IREF, 33.2, 49.9 Rising edge rising edge VX,, RIREF 475, IREF, 33.2, 49.9 Rising edge rising edge VX,, RIREF 475, IREF, 33.2, 49.9
ISO9001
2.26.02
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Table Timing Specifications, continued
Unless otherwise stated, power supplies 3.3V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Spread spectrum modulation disabled except Rise/Fall time measurements.
PARAMETER 66REF Reference Clock Output Duty Cycle Jitter, Long Term (y()) Jitter, Period (peak-peak) Rise Time Fall Time 14REF Reference Clock Output Duty Cycle Jitter, Long Term (y()) Jitter, Period (peak-peak) Rise Time Fall Time
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
tj(LT) tj(P)
Ratio high pulse width clock period, measured 1.5V rising edges 500µs apart 1.5V relative ideal clock, CL=20pF From rising edge rising edge 1.5V, CL=20pF Measured 0.4V 2.4V; CL=10pF Measured 0.4V 2.4V; CL=20pF Measured 2.4V 0.4V; CL=10pF Measured 2.4V 0.4V; CL=20pF Ratio high pulse width clock period, measured 1.5V rising edges 500µs apart 1.5V relative ideal clock, CL=20pF From rising edge rising edge 1.5V, CL=20pF Measured 0.4V 2.4V; CL=10pF Measured 0.4V 2.4V; CL=20pF Measured 2.4V 0.4V; CL=10pF Measured 2.4V 0.4V; CL=20pF
tj(LT) tj(P)
Figure Measurement Points
3.3V 2.4V 0.4V 2.0V 0.8V
Figure Timing Diagram
3.3V 2.4V 1.5V 0.4V
Figure HOST Clock Measurement Point
HOST_P HOST_N
Figure HOST Clock Test Point
From output under test Test node
ISO9001
2.26.02
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Table MCLK_P, MCLK_N, 14REF, 66REF Clock Outputs
Voltage High Drive Current (mA) MIN. TYP. MAX. Voltage Drive Current (mA) MIN. TYP. MAX. -132 -131 -130 Output Current (mA) -129 -127 -126 -124 -121 -117 -112 -105
-100 -125 -150
Output Voltage
Data this table represents nominal characterization data only
Table APIC_0:2 Clock Outputs
Voltage High Drive Current (mA) MIN. TYP. MAX. Voltage Drive Current (mA) MIN. TYP. MAX.
-100
Output Current (mA)
0.25 0.75 1.25 1.75
Output Voltage
Data this table represents nominal characterization data only
2.26.02
ISO9001
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Package Information
Table 48-pin SSOP (0.300") Package Dimensions
DIMENSIONS INCHES MIN. 0.095 0.008 0.008 0.005 0.620 0.395 0.291 0.015 0.020 MAX. 0.110 0.016 0.0135 0.010 0.630 0.420 0.299 0.025 0.040 MILLIMETERS MIN. 2.41 0.20 0.20 0.13 15.75 10.03 7.39 0.38 0.51 MAX. 2.79 0.41 0.34 0.25 16.00 10.67 7.59 0.64 1.01
AMERICAN MICROSYSTEMS, INC.
0.025
0.64
SEATING PLANE
Table 48-pin SSOP (0.300") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Longest lead Longest lead adjacent lead Longest lead adjacent lead Longest lead Longest lead adjacent lead Longest lead adjacent lead
TYP. 0.94 0.46 0.05
UNITS °C/W
ISO9001
2.26.02
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Table 48-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS INCHES MIN. 0.002 0.0067 0.0035 0.488 0.236 0.018 0.008 MAX. 0.047 0.006 0.011 0.008 0.496 0.244 0.030 MILLIMETERS MIN. 0.05 0.17 0.09 12.40 6.00 0.45 0.20 MAX. 1.20 0.15 0.27 0.20 12.60 6.20 0.75
AMERICAN MICROSYSTEMS, INC.
0.318 0.019
8.10 0.50
SEATING PLANE
Table 48-pin TSSOP (6.1mm) Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Longest lead Longest lead adjacent lead Longest lead adjacent lead Longest lead Longest lead adjacent lead Longest lead adjacent lead
TYP. 3.50 1.82 1.17 0.63 0.30 0.03
UNITS °C/W
ISO9001
2.26.02
FS6158-01
Two-Way/Four Motherboard Clock Generator/Buffer
Ordering Information
ORDERING CODE 11915-801 11915-811 FS6158-01 11915-201 11915-211 48-pin (6.1mm) TSSOP 48-pin (6.1mm) TSSOP PACKAGE TYPE 48-pin (0.300") SSOP 48-pin (0.300") SSOP OPERATING TEMPERATURE RANGE 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) SHIPPING CONFIGURATION Tape Reel Tubes Tape Reel Tubes
DEVICE NUMBER
Copyright 1999, 2000 American Microsystems, Inc.
Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
ISO9001
2.26.02

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