EV3053/54 EV3053/54 S3053/54 Evaluation Board provides flexible p

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EV3053/54 EV3053/54 S3053/54 Evaluation Board provides flexible p

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GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD DESCRIPTION
EV3053/54 EV3053/54
S3053/54 Evaluation Board provides flexible platform verifying operation S3053 QUAD S3054 DUAL CROSSPOINT SWITCH interface circuit. This document provides information board contents. should used conjunction with S3053/54 data sheet, which contains full technical details chip operation. Figure shows outline S3053/54 Evaluation Board Figures show block diagram S3053/54 Evaluation Board should connected test equipment.
Figure S3053/54 Evaluation Board
IND1N (INB0N)
IND1P (INB0P)
IND0P (INB1P)
IND0N (INB1N)
INA0N (INA0N)
OUTB1P (OUTA0P)
INA0P (INA0P)
OUTB1N (OUTA0N)
AMCC S3053/54
INA1P (INA1P) OUTB0N (OUTA1N)
INA1N (INA1N)
AMCC
OUTB0P (OUTA1P)
APPLIED MICRO CIRCUITS CORP. 6290 SEQUENCE DRIVE DIEGO, 92121
S3053
SELA SELB SELC SELD
S3054
SELA0 SELA1 SELB1 SELB0
OUTC0P (OUTB0P)
OUTC0N (OUTB0N)
OUTC1N (OUTB1N)
OUTC1P (OUTB1P)
February 1999
EV3053/54
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
block diagram Figures show basic operation S3053 S3054.
Figure S3053 Functional Block Diagram
SELA SELB INA0P INA0N INA1P INA1N OUTB0P OUTB0N OUTB1P OUTB1N
OUTC0P OUTC0N OUTC1P OUTC1N
IND0P IND0N
IND1P IND1N
SELC SELD
Figure S3054 Functional Block Diagram
INA0P INA0N
OUTA0P OUTA0N
SELA0
OUTA1P INA1P INA1N SELA1 OUTA1N
INB0P INB0N
OUTB0P OUTB0N
SELB0
INB1P INB1N SELB1
OUTB1P OUTB1N
February 1999
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
Figure S3053 Schematic
EV3053/54
100pF
100pF
1.0uF
OPEN CLOSED
0.1uF
100pF
0.1uF 100pF
0.1uF
100pF 0.1uF 100pF
VSWC0 VEEC0
IND1N IND1P SELD
OUTC0P OUTC0N OUTC1N OUTC1P VEEC1 VSWC1
OUTB0N OUTB0P VEEB0 VSWB0
0.1uF 100pF
SELC IND0P IND0N
0.1uF 100pF
0.1uF
0.1uF
0.1uF
Figure external resistor values.
February 1999
DSW4
SELA SELB SELC SELD
100pF
100pF
100pF
0.1uF
0.1uF
0.1uF
1.0uF
1.0uF
0.1uF
0.1uF
1.0uF
1.0uF
CONN1X2PWR
1.0uF
0.1uF
0.1uF 100pF
0.1uF 100pF
SELA
SELB
INA1N
SELB INA1P
INAON INAOP SELA OUTB1N VEEB1 OUTB1P
SELD
S3053
VSWB1
SELC
0.1uF 100pF
0.1uF
100pF
0.1uF 100pF
EV3053/54
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
Figure S3054 Schematic
100pF
100pF
1.0uF
OPEN CLOSED
0.1uF
100pF
0.1uF 100pF
0.1uF
100pF 0.1uF 100pF
VSWC0 VEEC0
INB0N INB0P
OUTB0P OUTB0N OUTB1N OUTB1P VEEC1 VSWC1
SELB0 SELB1 INB1P INB1N
0.1uF 100pF
0.1uF 100pF
0.1uF 0.1uF
0.1uF
Figure external resistor values.
DSW4
SELA0 SELA1 SELB1 SELB0
100pF
100pF
100pF
0.1uF
0.1uF
0.1uF
1.0uF
1.0uF
0.1uF
0.1uF
1.0uF
1.0uF
CONN1X2PWR
1.0uF
0.1uF
0.1uF 100pF
SELA0
SELA1
0.1uF 100pF
INA1N
SELA1 INA1P
INAON INAOP SELA0
SELB0
S3054
OUTA0N VEEB1 OUTA0P VSWB1
SELB1
OUTA1N OUTA1P VEEB0 VSWB0
0.1uF 100pF
0.1uF
100pF
0.1uF
100pF
February 1999
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
Figure Typical Single-Ended Voltage Swing Rext. Temperature
EV3053/54
February 1999
EV3053/54
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
Figure depicts S3053/54 Evaluation Board connected measurements shows setup rise/fall time, propagation delay, jitter transfer opening measurements.
Figure S3053/54 Test Setup
TRIGGER INPUT
DIGITAL SAMPLING SCOPE
SIGNAL
POWER SUPPLY
Transmitter
TRIGGER DATA DATA
OUTXXP/N INXXP INXXN
BERT(>3GHZ)
S3053/54 DEMO BOARD
Receiver
DATA
OUTXXP/N
*Both sides MUST connected loading purposes
POWER BIASING
-3.3V
NOTES:
VCC/VEE Tolerance BERT 70481B Pattern Gen/701311A Source BERT 70004A/&0842B Error Detector "Trigger Out" Clock Option Bert Termination: GND; cables
February 1999
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
EV3053/54
Figure depicts S3053/54 Evaluation Board connected CROSSTALK measurement.
Figure S3053/54 Test Setup
TRIGGER INPUT
DIGITAL SAMPLING SCOPE
SIGNAL
POWER SUPPLY
Transmitter
TRIGGER DATA DATA
OUTXXP/N INXXP INXXN
BERT(>3GHZ)
S3053/54 DEMO BOARD
Receiver
DATA
OUTXXP/N
INYYP/N
*Both sides MUST connected loading purposes
POWER BIASING
-3.3V
DATA OUTP/N
BERT(>3GHZ) Pattern Gen.
NOTES:
VCC/VEE Tolerance BERT 70481B Pattern Gen/701311A Source BERT 70004A/&0842B Error Detector "Trigger Out" Clock Option Bert
page
February 1999
EV3053/54
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
CONNECTORS
connectors provided input/output signals.
S3053
INA0P/N, INA1P/N Differential inputs multiplexor. IND0P/N, IND1P/N Differential inputs multiplexor. inputs must driven high state. SELA level selects INA0P/N. SELA High level selects INA1P/N SELD level selects IND0P/N. SELD- High level selects IND1P/N. SELB level selects output. (See Figure SELB High level selects output. SELC level selects output. SELC High level selects output. OUTB0P/N, OUTB1P/N Serial output from (See Figure OUTC0P/N, OUTC1P/N Serial output from
S3054
INA0P/N, INB0P/N Differential inputs. INA1P/N, INB1P/N Differential inputs. inputs must driven high state. SELA0 level selects INA0P/N. SELA0 High level selects INA1P/N. SELA1 level selects INA0P/N. SELA1 High level selects INA1P/N. SELB0 level selects INB0P/N. SELB0 High level selects INB1P/N. SELB1 level selects INB0P/N. SELB1 High level selects INB1P/N. OUTA0P/N Channel serial output. OUTA1P/N Channel serial output. OUTBOP/N Channel Serial output. OUTB1P/N Channel serial output.
SWITCHES
Evaluation Board equipped with switch, control static control functions on-board devices. both arrays (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts logic high.
February 1999
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
Figures through show layout S3053/54 Evaluation Board.
EV3053/54
Figure
Figure
February 1999
EV3053/54
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
Figure
Figure
February 1999
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
Figure
EV3053/54
February 1999
EV3053/54
GBIT QUAD DUAL CROSSPOINT EVALUATION BOARD
Ordering Information
PREFIX DEVICE PACKAGE
Evaluation Board
3053/54
TQFP/TEP
Prefix
XXXX Device Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (619) 450-9333 (800) 755-2622 Fax: (619) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
February 1999

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