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2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD 2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD DESCRIPTION

EV3053 / 54 EV3053 / 54

2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD 2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD DESCRIPTION
EV3053 / 54 EV3053 / 54
The S3053 / 54 Evaluation Board provides a flexible platform for verifying the operation of the S3053 QUAD MUX and S3054 2 X 2 DUAL CROSSPOINT SWITCH interface circuit. This document provides information on board contents. It should be used in conjunction with the S3053 / 54 data sheet, which contains full technical details on chip operation. Figure 1 shows the outline of the S3053 / 54 Evaluation Board and Figures 7 and 8 show the block diagram of how the S3053 / 54 Evaluation Board should be connected to test equipment.
Figure 1. S3053 / 54 Evaluation Board
IND1N (INB0N)
IND1P (INB0P)
IND0P (INB1P)
IND0N (INB1N)
GND VEE
INA0N (INA0N)
OUTB1P (OUTA0P)
INA0P (INA0P)
OUTB1N (OUTA0N)
AMCC S3053 / 54
INA1P (INA1P) OUTB0N (OUTA1N)
INA1N (INA1N)
OUTB0P (OUTA1P)
APPLIED MICRO CIRCUITS CORP. 6290 SEQUENCE DRIVE SAN DIEGO, CA 92121
S3053
A B C D SELA SELB SELC SELD
S3054
SELA0 SELA1 SELB1 SELB0
OUTC0P (OUTB0P)
OUTC0N (OUTB0N)
OUTC1N (OUTB1N)
OUTC1P (OUTB1P)
February 26, 1999
EV3053 / 54
2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
The block diagram in Figures 2 and 3 show basic operation of the S3053 and S3054.
Figure 2. S3053 Functional Block Diagram
SELA SELB INA0P INA0N INA1P INA1N 0 MUX A 1 0 MUX B 1 OUTB0P OUTB0N OUTB1P OUTB1N
OUTC0P OUTC0N OUTC1P OUTC1N
IND0P 0 0 MUX MUX D D 1 1 IND0N
IND1P IND1N
SELC SELD
Figure 3. S3054 Functional Block Diagram
INA0P INA0N
0 OUTA0P 1 OUTA0N
SELA0
0 OUTA1P INA1P INA1N SELA1 1 OUTA1N
INB0P INB0N
0 OUTB0P 1 OUTB0N
SELB0
0 INB1P INB1N SELB1 1
OUTB1P OUTB1N
February 26, 1999
2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
Figure 4. S3053 Schematic
EV3053 / 54
100pF C27
1.0uF C25
0.1uF C26
100pF C27
0.1uF C31 100pF C32
0.1uF C33
100pF C34 0.1uF C39 100pF C40 J13 J14 J15
VEE VSWC0 VEEC0
VEE IND1N IND1P SELD VEE VCC VEE VCC VEE
OUTC0P OUTC0N VCC VEE VCC OUTC1N OUTC1P VEEC1 VSWC1 VEE
NC OUTB0N OUTB0P VEEB0 VSWB0
0.1uF C35 100pF C36
SELC IND0P IND0N VEE
0.1uF C37 100pF C38
0.1uF C24 R2
0.1uF C20 J11
0.1uF C41 R3
See Figure 6 for external resistor values.
February 26, 1999
SELA SELB SELC SELD
100pF C27
0.1uF C26
1.0uF C25
0.1uF C26
1.0uF C25
CONN1X2PWR
1.0uF C25
0.1uF C42
0.1uF C9 100pF C10
VEE VEE VEE
0.1uF C11 100pF C12
INA1N
VEE SELB INA1P 18
VCC VCC VCC VCC
VCC VCC
NC INAON INAOP SELA VEE OUTB1N VEEB1 OUTB1P
S3053
NC VSWB1
0.1uF C13 100pF C14
0.1uF C4
100pF C5
0.1uF C15 100pF C16
EV3053 / 54
2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
Figure 5. S3054 Schematic
100pF C27
1.0uF C25
0.1uF C26
100pF C27
0.1uF C31 100pF C32
0.1uF C33
100pF C34 0.1uF C39 100pF C40 J13 J14 J15
VEE VSWC0 VEEC0
VEE INB0N INB0P
OUTB0P OUTB0N VCC VEE VCC OUTB1N OUTB1P VEEC1 VSWC1 VEE
SELB0 VEE VCC VEE VCC VEE SELB1 INB1P INB1N VEE
0.1uF C35 100pF C36
0.1uF C37 100pF C38
0.1uF C24 R2 0.1uF C15
0.1uF C41
See Figure 6 for external resistor values.
SELA0 SELA1 SELB1 SELB0
100pF C27
0.1uF C26
1.0uF C25
0.1uF C26
1.0uF C25
CONN1X2PWR
1.0uF C25
0.1uF C42
0.1uF C9 100pF C10
SELA0
SELA1
VEE VEE VEE VEE
0.1uF C11 100pF C12
51 INA1N
50 J11
VEE SELA1 INA1P
VCC VCC VCC VCC 20 19
NC INAON INAOP SELA0 VEE
SELB0
S3054
OUTA0N VEEB1 OUTA0P NC VSWB1 VCC
SELB1
OUTA1N OUTA1P VEEB0 VSWB0 17 16 15
0.1uF C13 100pF C14
0.1uF C4
100pF C5
0.1uF C20
100pF C16
February 26, 1999
2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
Figure 6. Typical Single-Ended Voltage Swing vs. Rext. and Temperature
EV3053 / 54
February 26, 1999
EV3053 / 54
2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
Figure 7 depicts how the S3053 / 54 Evaluation Board can be connected for BER measurements and shows the setup for rise / fall time, propagation delay, jitter transfer and eye opening measurements.
Figure 7. S3053 / 54 Test Setup
TRIGGER INPUT
DIGITAL SAMPLING SCOPE
SIGNAL IN
POWER SUPPLY
Transmitter
TRIGGER OUT DATA OUT DATA OUT CLK OUT
OUTXXP / N INXXP INXXN
CLK IN
S3053 / 54 DEMO BOARD
Receiver
DATA IN
OUTXXP / N
Both sides MUST be connected for loading purposes
POWER BIASING
ECL VCC VEE 0V -3.3V
NOTES:
February 26, 1999
2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
EV3053 / 54
Figure 8 depicts how the S3053 / 54 Evaluation Board can be connected for CROSSTALK measurement.
Figure 8. S3053 / 54 Test Setup
TRIGGER INPUT
DIGITAL SAMPLING SCOPE
SIGNAL IN
POWER SUPPLY
Transmitter
TRIGGER OUT DATA OUT DATA OUT CLK OUT
OUTXXP / N INXXP INXXN
CLK IN
S3053 / 54 DEMO BOARD
Receiver
DATA IN
OUTXXP / N
INYYP / N
Both sides MUST be connected for loading purposes
POWER BIASING
ECL VCC VEE 0V -3.3V
DATA OUTP / N
NOTES:
See page 6.
February 26, 1999
EV3053 / 54
2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
SMA CONNECTORS
SMA connectors are provided for the input / output signals.
S3053
INA0P / N, INA1P / N - Differential inputs to the multiplexor. IND0P / N, IND1P / N - Differential inputs to the multiplexor. All inputs must be driven to high or low state. SELA - A Low level selects INA0P / N. SELA - A High level selects INA1P / N SELD - A Low level selects IND0P / N. SELD- A High level selects IND1P / N. SELB - A Low level selects MUX A output. (See Figure 2.) SELB - A High level selects MUX D output. SELC - A Low level selects MUX A output. SELC - A High level selects MUX D output. OUTB0P / N, OUTB1P / N - Serial output from MUX B. (See Figure 3.) OUTC0P / N, OUTC1P / N - Serial output from MUX C.
S3054
INA0P / N, INB0P / N - Differential inputs. INA1P / N, INB1P / N - Differential inputs. All inputs must be driven to high or low state. SELA0 - A Low level selects INA0P / N. SELA0 - A High level selects INA1P / N. SELA1 - A Low level selects INA0P / N. SELA1 - A High level selects INA1P / N. SELB0 - A Low level selects INB0P / N. SELB0 - A High level selects INB1P / N. SELB1 - A Low level selects INB0P / N. SELB1 - A High level selects INB1P / N. OUTA0P / N - Channel A0 serial output. OUTA1P / N - Channel A1 serial output. OUTBOP / N - Channel B0 Serial output. OUTB1P / N - Channel B1 serial output.
DIP SWITCHES
February 26, 1999
2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
Figures 9 through 13 show the layout of the S3053 / 54 Evaluation Board.
EV3053 / 54
Figure 9.
Figure 10.
February 26, 1999
EV3053 / 54
2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
Figure 11.
Figure 12.
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2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
Figure 13.
EV3053 / 54
February 26, 1999
EV3053 / 54
2.5 GBIT QUAD MUX AND 2 X 2 DUAL CROSSPOINT EVALUATION BOARD
Ordering Information
PREFIX DEVICE PACKAGE
EV - Evaluation Board
TT - TQFP / TEP
X Prefix
XXXX X Device Package
Applied Micro Circuits Corporation · 6290 Sequence Dr., San Diego, CA 92121 Phone: (619) 450-9333 · (800) 755-2622 · Fax: (619) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright ® 1999 Applied Micro Circuits Corporation
February 26, 1999