S3050 Evaluation Board provides flexible platform verifying operation

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

S3050 Evaluation Board provides flexible platform verifying operation

Datasheet Thumbnail

Top Searches for this datasheet

OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD DESCRIPTION
S3050 Evaluation Board provides flexible platform verifying operation AMCC OC-48 clock recovery units. This document provides information board's contents layout. should used conjuction with S3050 data sheet, which contains full technical details chip operation. S3050 board factory configured with S3050 device, includes test point monitor LOCKDET output. board configured with external oscillator connected REFCLKP/N connectors.
EV3050 EV3050
ELECTRICAL CONNECTIONS
Power Connections
Terminal posts provided edge board allowing separate control voltage levels S3050 itself. operation with standard test equipment, board should operated below ground, with supply
Figure Board Layout
Used internal purposes
VEE7
SERCLKOP TESTSIG (TESTEN)
SERCLKON
SERDATIP
SERDATOP
AMCC S3050
SERDATIN SERDATON
VCOD32**
RATESEL0 RATESEL1 RESET BYPASS LCKREFN
6290 SEQUENCE DRIVE DIEGO, 92121 S3050 MULTI-RATE SONET/SDH
AMCC
LOCKDET
REFCLKN*
REFCLKP*
REFCLKP labled REFCLKN REFCLKN labled REFCLKP this board. VCOD32 internal only.
July 1999
EV3050
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
SET-UP JITTER MEASUREMENT
Figure depicts S3050 Evaluation Board connected Jitter measurements shows switch settings power supply requirements. connection from will used PK-PK edge/PK-PK Jitter (Digital Storage Oscilloscope). connection from will used Jitter Transfer, Jitter Tolerance Jitter Generation measurement Transition Analyzer.
Figure Jitter Measurement Setup
POWER VCC=GND -5.0V
70820A Transition Analyzer
INPUT INPUT
D.S.O.
CONNECTION
MEASUREMENT
(Note
PK-PK JITTER
3325
MAIN SIGNAL 0955-0731 0955-0731 Bandpass filter 2.488 Bandpass filter 2.488
JITTER TRANSFER JITTER TOLERANCE JITTER GENERATION
MODULATION INPUT
70841B
SERDATIP SERDATIN
SERCLKOP SERCLKON
70842B
B.E.R.T. (2.488 GHz)
S3050
SERDATOP SERDATON
B.E.R.T. (2.488 GHz)
SWITCH RATESEL (Note RATESEL REFCLKP REFCLKN RESET BYPASS LCKREFN
(0V) TABLE TABLE RESETS DATA VCO/OFF LCK/DATA DATA OUT/OFF
(-5.0V) TABLE TABLE NORMAL VCO/ON LCK/REF DATA OUT/ON
8624B
REFCLK 155.52
BUFFER
Notes: Edge Jitter measured SERDATON edge with data eye. single-ended with REFCLK (REFCLKP) REFCLKN terminated with ground. Make sure that cables BERT (SERCLK/SERDAT) equal length (EXACT). Different lengths will create errors. (When measuring, cables signals under test must equal length.)
July 1999
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
Table Power Connections Test Equipment Interface
Power Supply Nominal Input Voltage -5.0V Type Signal Input Output Output Termination
EV3050
Connectors
connectors provided differential serial data input/output signals output clock. Cables these connectors must same length. Serial Data [SERDATIP/N] Differential inputs. Serial Data Clock recovered from transitions these inputs. Reference Clock [REFCLKP/N] Differential inputs. These inputs used establish initial operating frequency clock recovery also used standby clock absence data. These inputs must provided with differential clock 155.52 MHz. Coupled). Serial Data [SERDATOP/N] outputs. This signal delayed version incoming data stream (SERDATI) updated falling edge Serial Clock (SERCLKOP). Serial Clock Output [SERCLKOP/N] outputs. This signal phase aligned with Serial Data (SERDATOP).
Jumper
Lock Detect [LOCKDET] output. Indicates that Clock Recovery locked onto incoming data stream.
Switches
Evaluation Board equipped with switch control static control functions on-board devices. both arrays (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts Logic High. Figure shows switch settings needed particular test case. (Should show Logic Logic "0").
July 1999
10uF
0.1uF
100pF
0.1uF
0.1uF
AVEE
CAP1
RESET
AVCC
CAP2
RATESEL0
3050VEE 0.1uF
AVEE AVEE SERDATIP SERDATOP SERDATON VCODIV32 SERDATIN REFCLKP SERCLKON AVCC SERCLKOP TESTEN RATESEL1
RATESEL1
100pF
100pF
REFCLKN
LCKREFN
REFCLKP
0.1uF
REFCLKN
3050VEE
0.1uF
LOCKDET
0.1uF
100pF
0.1uF
RATESEL0
RATESEL1
RESET
3050VEE
OPEN ="0" CLOSED ="1"
BYPASS
1N4148
1N4148
100pF
EV3050
3050VEE
Figure Schematic
subject change
10µF
10µF 2.2µF
RATESEL0
LOOPS
150K 150K
RESET
TESTEN
SERCLKOP SERCLKON
100pF
0.1uF 100pF
SERDATIP
0.1uF
S3050
AVEE
SERDATOP SERDATON VCOD32
SERDATIN
0.1uF
LOCKDET
1N4148
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
July 1999
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
Figures through show layout S3050 Evaluation Board.
EV3050
Figure
Figure
July 1999
EV3050
Figure
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
Figure
July 1999
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
Figure
EV3050
Figure
July 1999
EV3050
Ordering Information
PREFIX
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
DEVICE
PACKAGE
Evaluation Board
3050
TQFP/TEP
Prefix
XXXX Device Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
July 1999

S3050 Evaluation Board provides flexible platform verifying operation

Top Searches for this datasheet

Other recent searches