SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD SONET/SDH OC-48 TRANSCEIV
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
EV3041A EV3041A
EVALUATION BOARD OVERVIEW
This document describes operation usage AMCC S3041/S3042 Evaluation Board with HFCT-5402D Single Mode Fiber Transceiver. evaluation board allows users become familiar with functionality S3041 transmitter S3042 receiver combination. Specifically, error rate (BER), jitter generation, loopback mode tested using this evaluation board. This document provides complete board description, explains various test configurations, board layout, test equipment list, contains board schematic. This document should used conjunction with S3041,S3042 HFCT-5402D data sheets application notes. Figure shows outline S3041/S3042 Evaluation Board.
Figure S3041/S3042 Evaluation Board (Top View)
S3041 RSTB
THDIODE
THDIODE
LLEB DLEB KILLTXCLKN TESTEN
LLEB
REFCLKP
EL51
EL51 EL16
EL16
KILLRXCLK
FRAMEN
SDPECL
DLEB
S3041 NOISE INJECT
S3041 (+3.3V)
S3042 (+3.3V)
S3042 NOISE INJECT
REFCLKN
77MCK POCLKP/N
RSCLKP
EXT.
PICLKP/N
POUT[7:0]P/N FPP/N RX311MCKP/N SEARCH
S3041
EL33 EL33
PCLKP/N PIN[7:0]P/N LOCKDET
S3042
RSCLKN
TSCLKP RSDN
TSCLKN RSDP
APPLIED MICRO CIRCUITS CORPORATION 6290 SEQUENCE DIEGO, 92121 S8401/S8501 SERIALIZER DESERIALIZER
AMCC
TSDN
HFCT-5402D 2.488GB/s Single-Mode Fiber Transceiver
19.44MHz PECL XTAL OSCILLATOR OPTICS POWER TSDP 19.44 EXT.REF
LMLM+ TXDIS
S3042 RSTB
NOISE INJECT
NOISE INJECT
location.
Zero jumper
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PRELIMINARY
EV3041A
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
EVALUATION BOARD DESCRIPTION
This section describes functionality connectors recommended settings S3041/S3042 Evaluation Board. brief description connectors, switch descriptions settings, power grounds, output levels, probes, header settings will discussed. letters "A", "B", "C", correspond specific parts evaluation board, described following section according their letter designation shown Figure
Connectors
connectors provided differential serial data input/output signals, noise injects, reference clocks. Table gives description connectors S3041/S3042 Evaluation Board.
Table Connectors Description
Connector Receive Serial Data [RSDP/RSDN] Receive Serial Clock [RSCLKP/RSCLKN] Transmit Serial Data Output [TSDP/TSDN] Transmit Serial Clock [TSCLKP/TSCLKN] Reference Clock [REFCLKP/N] External Clock [EXT. CLK] 19.44 External Clock [19.44 EXT. CLK] Fiber Optic Module Noise Inject NOISE INJECT] Fiber Optic Module Noise Inject NOISE INJECT] S3041 Noise Inject Input [S3041 NOISE INJECT] S3042 Noise Inject Input [S3042 NOISE INJECT] Description Differential LVPECL Inputs. Serial data inputs S3042. Differential LVPECL Inputs. Recovered clock synchronous with data inputs. This clock used receive section master clock perform framing deserialization functions. Differential Outputs. Serial data stream signal S3041. Normally connected optic module. Differential Outputs. Transmit serial clock that used retime serial data. optical transmitter rising edge TSCLK retime data. LVPECL Input. 155MHz. clock generator circuit S3041 will lock this reference clock comparing REFCLK with internally divided down clock. External clock used comparative reference (after being divided down) clock generator circuit transmit section (S3041). External reference clocking fiber optic module. Noise inject fiber optic module receiver. Used power supply noise immunity testing. Noise inject fiber optic module transmitter. Used power supply noise immunity testing. Noise inject S3041 transmitter. Used power supply noise immunity testing. Noise inject S3042 receiver. Used power supply noise immunity testing.
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Switches
EV3041A
Evaluation Board equipped with switch switch switch switch control static control functions S3042 S3041 respectively. both devices (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts logic high. Note that printed evaluation board. Table describes each switches evaluation board. Table shows specific switch setting needed various test conditions.
Table Switch Descriptions
Names S3041 TESTEN Test Clock Enable. Active high "1". When high "1", LLCLK selected instead internally generated clock system clock. When "0", internally generated clock selected normal operation. Diagnostic Loopback Enable. Active "0". When active, diagnostic loopback selected. LSCLK, outputs become active addition TSCLK. high normal operation. Line Loopback Enable. Active "0". Selects Line Loopback. When active, S3041 will route data from LLD/LLCLK inputs TSD/TSCLK outputs. high normal operation. Kill Transmit Clock Input. Active "0". When low, PCLK PULSE0 forced output low. high normal operation. Description
DLEB
LLEB
KILLTXCLKN S3042 SDPECL
LVPECL Signal Detect. Active high "1". single-ended LVPECL input driven external optical receiver module indicate loss received optical power. When SDPECL inactive, data Serial Data (RSDP/N) pins will internally forced constant zero. When SDPECL active, data RSDP/N pins will processed normally. Kill Receive Clock Input. Active "0". When low, will force RX311MCK POCLK outputs logic state. high normal operation. Frame Enable Input. Active "0". When low, will disable frame detector circuit will lock last byte alignment state. When high "1", enables frame detector circuit detect alignment lock word boundary (normal operation). Frame. Indicator used enable framing pattern detection logic S3042. Enabled rising edge OOF, remains enabled until frame boundary detected. Line Loopback Enable. Active "0". Selects Line Loopback. When active, S3041 will route data from LLD/LLCLK input TSD/TSCLK output. high normal operation. Diagnostic Loopback Enable. Active "0". When active (low "0"), diagnostic loopback selected. LSCLK from S3041 will routed S3042 input instead RSCLK.
KILLRXCLK FRAMEN
LLEB
DLEB
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EV3041A
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Table Switch Settings Test Evaluation Configurations
S3041 TEST JITTER TEST LINE LOOPBACK S3042 TEST JITTER TEST LINE LOOPBACK TESTEN SDPECL DLEB KILLRXCLK LLEB FRAMEN KILLTXCLKN LLEB DLEB
RSTB Pushbutton Switch This momentary contact switch controls master reset S3041/S3042. Please refer S3041/S3042 data sheet details specific control functions. Normal mode this master reset input normally high. Depressing switch connects this input logic zero resets S3041/S3042.
Power/Ground
Terminal posts provided edge board (Terminal post voltage settings given Table 4.). Figure demonstrates type input setting corresponding output waveform that S3042 outputs.
Table Evaluation Board Terminal Post Power Ground Settings
Terminal Post S3041VCC -2V2 S3042VCC OSCVCC RXVCC TXVCC Voltage +3.3V1 +3.3V1 +5V1
These voltages vary based type test equipment used. Table shows alternate voltage settings. Supplies rail Motorola ECLIPs parts.
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
EV3041A
external test equipment environment other standard and/or +3.3V Referenced systems interface S3041/S3042 Evaluation Board. board shown Figures powered allow easy connection standard ground inputs high performance oscilloscopes spectrum analyzers well standard serial Error Rate Testers (BERT) Jitter Analyzers (see Table voltage settings). nominal input voltages (per Table with resulting voltage levels shown Figures Figure shows S3042 output with S3042 +3.3V. Note that output voltage levels dependent VCC. Figure shows that output voltages track with VCC. input output signal types terminations, refer respective device datasheet.
Table Power Connections Interface Test Equipment
Power Supply S3041VCC S3042VCC (Power buffers) Nominal Input Voltage +3.3 +3.3 Type Signal
Figure S3042 Outputs (D0-D7) with S3042VCC +3.3V
+3.3V 2.2V 1.35V 0.5V
Figure S3041 Differential Output (TSDP/N) with S3041 +3.3V
+3.3V +0.2V -0.2V
Termination Ohms
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EV3041A
Probes/Header Terminals
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
normal operation, PIN[7:0]P/N POUT[7:0]P/N headers jumpered. Table reveals probe connection points header descriptions S3041/S3042 Evaluation Board. Table Evaluation Board Probe/Header Descriptions
Connector THDIODE Optic Module Signal Detect. Normal optical data input results logic "1". Loss optical power receiver results logic "0". Laser Bias Monitor (-). Analog current monitored measuring voltage drop across resistor placed between high impedance resistors connected pins internal transceiver. Laser Bias Monitor (+). Analog current monitored measuring voltage drop across resistor placed between high impedance resistors connected pins internal transceiver. Transmitter Disable. Transmitter output disabled: Vcct -1.5V Vcct. Transmitter output enabled: Veet Vcct open circuit. Ground. Thermal Diode. Allows calculation junction temperature. Description
TXDIS
S3041 77MCK PICLKP/N PCLKP/N 77MHz Clock Output. LVTTL S3041 Output. output derived from S3041/S3042 available header monitoring. Parallel Input Clock S3041. LVDS output from S3041. byte rate output reference from transmitter PLL. This output used coordinate byte-wide transfers between upstream logic S3041 logic. Lock Detect. Goes after locked clock provided REFCLK pins. LOCKDET asynchronous output. Parallel Data Input S3041.
LOCKDET PIN[7:0]P/N S3042 SEARCH
Frame Search S3042 Output. high this output indicates frame detection circuit activated searching byte alignment. This ouput will high during entire period frame search. Once alignment found, this signal will remain high minimum clock period beyond third byte before will low. Free running clock output from S3042. This clock generated dividing down RSCLK signal eight. Frame Pulse. LVDS output from S3042. Indicates frame boundaries incoming data stream (RSDP/N). Parallel Output Clock. nominaly duty cycle, byte rate output clock that aligned POUT[7:0] byte serial output clock. Parallel Data Output from S3042.
RX311MCKP/N FPP/N POCLKP/N POUT[7:0]P/N
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD TEST CONFIGURATIONS
EV3041A
This section describes various test setups S3041/S3042. error rate (BER), jitter generation, line loopback test setups discussed.
Testing
test setup provides evaluate number errors accumulated S3042 S3041 transmission. This setup allows user track number bits that were unsuccessfully transmitted. 10-14 errors considered quasi error-free. Figure shows block diagram S3041/S3042 Evaluation Board should connected test equipment Error Rate (BER) testing. this configuration S3041/S3042 configured with 155.52MHz reference operating STS-48.
Figure S3041/42 Test Setup
SWITCH SETTING: DS1: LLEB=1 DLEB=1 OOF=1 FRAMEN=1 KILLRXCLKN=1 SDPECL=1 DS2: TESTEN=0 DLEB=1 LLEB=1 KILLTXCLKN=1 DS=Dip Switch REFCLKP REFCLKN ERROR DETECTOR 70842B DATA TSCLKN
BLOCK
GROUND
GROUND
S3041
S3042
NOISE INJECT
NOISE INJECT
EXTCLK
S3041
TSCLKP
RSCLKP
BLOCK
POWER DIVIDER
CLOCKP
70841B PATTERN GENERATOR 2.48832Ghz
S3042
RSCLKN
BLOCK
POWER DIVIDER
CLOCKN
TSDP
RSDN
DATAN
OPTICS MODULE
TRIG (PATTERN)
BLOCK
TSDN 19.44MHz EXT.CLK OPTICS POWER
RSDP
DATAP
OSCILLOSCOPE 11801A
TRIG INPUT
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EV3041A
Test Setup
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure shows S3041/S3042 evaluation board connected measurements. Table switch settings Table power supply requirements with test equipment that utilizes ohms ground termination. following description test setup shown Figure above. letters through following description correspond letter designations (A-F) shown Figure pattern generator outputs desired signal that user chosen. this test signal transmitted rate 2.48832 Gbps. output pattern generator goes RSDP/RSDN inputs evaluation board. clock inputs provided from pattern generator evaluation board. deserialized data from S3042 then sent S3041 jumpered serialized S3041. resulting output sent TSDP terminal evaluation board error detector. error detector receives signal directly from pattern generator through Modular System Interface (MSIB) link well signal from S3041/S3042 Evaluation Board. error detector compares signal coming from TSDP terminal evaluation board signal from pattern generator. signal considered error free signals logically equivalent shifted phase. oscilloscope used visual output verification TSDN TSCLK signal.
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Jitter Generation Test Configuration
EV3041A
following setup used test evaluate S3041/S3042 jitter generation performance. Figure shows block diagram jitter generation testing S3041/S3042 Evaluation Board with jitter analyzer test equipment. Switch settings this test configuration given Table
Figure Jitter Generation Test Configuration
SWITCH SETTING: DS1: LLEB=1 DLEB=1 OOF=1 FRAMEN=1 KILLRXCLKN=1 SDPECL=1 DS2: TESTEN=0 DLEB=1 LLEB=1 KILLTXCLKN=1 DS=Dip Switch REFCLKP REFCLKN
GROUND
GROUND
S3041
S3042
NOISE INJECT
NOISE INJECT
MICROWAVE TRANSITION ANALYZER 70820A INPUT
2.48832Ghz Band Pass Filter
EXTCLK
RSCLKP
BLOCK
CLOCKP
PATTERN GENERATOR 70841B
S3041
TSCLKP TSCLKN
S3042
RSCLKN
BLOCK
CLOCKN
2.48832Ghz
INPUT
RSDN RSDP
BLOCK
DATAN
TRIG (PATTERN)
BLOCK
DATAP
2.48832Ghz Band Pass Filter
TSDP TSDN
OPTICS POWER
OPTICS MODULE
19.44MHz EXT.CLK
OSCILLOSCOPE 11801A
TRIG INPUT
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EV3041A
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Jitter Generation Configuration Test Setup
following describes jitter generation system configuration shown Figure letters through following description correspond letter designations (A-E) shown Figure DATAP DATAN outputs from pattern generator received RSDP/RSDN inputs S3041/S3042 Evaluation Board, CLOCKP CLOCKN outputs from pattern generator received RSCLKP RSCLKN. data that received deserialized S3042, sent across data (using jumpers), through S3041 where data serialized sent TSDP/TSDN outputs evaluation board terminated with resistor ground. TSCLKP output sent through 2.48832 band pass filter INPUT Microwave Transition Analyzer 70820A). This band pass filter used filter extraneous noise possible harmonics that Microwave Transition Analyzer will evaluate only frequency interest. inverted output signal (TSCLKN) sent oscilloscope visual output verification. CLOCKN output pattern generator sent through 2.48832 band pass filter INPUT Microwave Transition Analyzer 70820A) comparison jitter signal received from TSCLKP output. pattern generator provides reference clocking S3041/S3042 EXTCLK input.
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Line Loopback Test Configuration
EV3041A
following setup used test evaluate S3041/S3042 performance Line Loopback Mode. Figure shows block diagram Line Loopback (LLEB) mode.
Figure Line Loopback Configuration
SWITCH SETTING: DS1: LLEB=0 DLEB=1 OOF=1 FRAMEN=1 KILLRXCLKN=1 SDPECL=1 DS2: TESTEN=0 DLEB=1 LLEB=0 KILLTXCLKN=1 DS=Dip Switch REFCLKP REFCLKN ERROR DETECTOR
70842B
GROUND
GROUND
S3041
S3042
NOISE INJECT
NOISE INJECT
EXTCLK
RSCLKP
DATA TSCLKN
S3041
TSCLKP
BLOCK
POWER DIVIDER
CLOCKP
70841B PATTERN GENERATOR 2.48832Ghz
S3042
RSCLKN
BLOCK
POWER DIVIDER
CLOCKN
RSDN
BLOCK DATAN
TSDP
OPTICS MODULE
TRIG (PATTERN) RSDP
BLOCK DATAP
TSDN 19.44MHz EXT.CLK OPTICS POWER
OSCILLOSCOPE
11801A
TRIG INPUT
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PRELIMINARY
EV3041A
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Line Loopback Configuration Test Setup
Figure shows block diagram line loopback S3041/S3042 Evaluation Board. Line Loopback Mode, S3041 routes serial data from LLD/LLCLK inputs TSD/TSCLK outputs. following describes operational system configuration shown Figure letters through following description correspond letter designations (A-F) shown Figure pattern generator outputs desired signal that user chosen. this test signal transmitted rate Gbps. output pattern generator goes RSDP/RSDN inputs evaluation board. clock inputs provided from pattern generator evaluation board block. block removes offset from incoming signal. Before data entering S3042 deserialized, data sent straight S3041 serial output. resulting output sent TSDP terminal evaluation board error detector. error detector receives signal directly from pattern generator (through MSIB link) well signal from S3041/S3042 evaluation board. error detector compares signal coming from TSDP terminal evaluation board signal from pattern generator. signal considered error free signals logically equivalent shifted phase. oscilloscope used visual output verification TSDN signal.
Figure Line Loopback Data Flow
S3042
DLEB
(SERIAL
LLEB
(SERIAL)
S3041
Note: Diagnostic loopback mode (DLEB) cannot with current board, because there parallel data input capability.
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Test Equipment/Schematic
EV3041A
following list equipment used various test setups S3041/S3042 Evaluation Board. Provided part number each component along with brief description part used. S3041/S3042 Evaluation Board schematic also provided visual representation component layout evaluation board.
Table BER/Line Loopback Setup
Part S3041/S3042 Eval Board 70841B equivalent) 70842B equivalent) Tektronix 11801A equivalent) Weinschel 93459 Model 1515 11742A 3383-36 Description board platform used house S3041/S3042 testing applications. Pattern Generator. Generates user input pattern send through device under test. Error Detector Taking line straight from pattern generator, line from output S3041/S3042, error detector compare signals determine amount errors that have occurred. Oscilloscope. Used visual output verification signals under testing. Power Divider. Used equally divide distribute power from clock outputs. Block. Used eliminate offset incoming signal. Cables. Quantity
Table Jitter Test Setup
Part S3041/S3042 Eval Board 70841B equivalent) Tektronix 11801A equivalent) 70820A1 Description board platform used house S3041/S3042 testing applications. Pattern Generator. Generates user input pattern send through device under test. Oscilloscope. Used visual output verification signals under testing. Microwave Transition Analyzer. Used calibrate clock setting test. During testing this device controls unit interval (UI) frequency that test performed Block. Used eliminate offset incoming signal. Cables. Quantity
11742A 3383-36
Part HP71501C Jitter Analysis System.
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LSCLKP LSCLKN LSDP LSDN LLCLKP LLCLKN LLDP LLDN PULSEON PULSEOP READN READP
PCLKN PCLKP PINN2 DLEB LLEB KILLTXCLKN POUTN1 POUTP1 POUTN2 POUTP2 POUTN3 POUTP3 POUTN4 POUTP4 POUTN5 POUTP5 POUTN6 POUTP6 POUTN7 POUTP7 RX311MCKN RX311MCKP SEARCH PINN0 PINP0 PINN1 PINP1 RSTB TESTEN POCLKN POCLKP POUTN0 POUTP0
Figure EV3041/3042 Evaluation Board Schematic
REFCLKP
REFCLKN PINP2 PINN3 PINP3 PINN4 PINP4 PINN5
S3041
EXT.
EXT.CLK DIVIDER
PINP6 PINN7 PINP7 LOCKDET PINN6
REFCLKP REFCLKN
PINP5
TSCLKP TSCLKN TSDN
TSDP
RSDP RSDN RSCLKN RSCLKP
LLDN LLDP LLCLKN LLCLKP LSDN LSDP LSCLKN LSCLKP FRAMEN KILLRXCLK SDPECL
TSCLKN TSDN TSDP
OPTICS MODULE
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
PRELIMINARY
March 1999
Zero jumper.
EV3041A
SWITCH /RSTB SWITCH /RSTB
PULSE/ READ CIRCUIT
77MCK PICLKN PICLKP
INTERFACE
LLEB DLEB RSTB
S3042
RSCLKP RSCLKN RSDN
TSCLKP
RSDP
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure S3041
EV3041A
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EV3041A
Figure S3042
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure Clock Divider
EV3041A
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EV3041A
Figure Pulse/Read Circuit
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure Control
EV3041A
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EV3041A
Figure HFCT-5401 Optics
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD EVALUATION BOARD LAYOUT TECHNIQUES
EV3041A
This section provides recommended power/ground termination techniques EV3401A Evaluation Board.
Terminations
S3041 S3042 LVDS inputs need line-to-line terminations. high frequency traces should designed transmission lines with termination. S3042 outputs terminated driver line-to-line termination resistor line. Differential signal traces should have matched length consistent spacing (for equal transit time). Differential line geometries shall fixed ohms operation. Incident noise coupled into closely spaced parallel lines becomes common mode phenomenon, which effectively cancels far-end differential inputs. Optical receiver outputs must coupled rest system because optical receiver module powered from downstream processing powered from +3.3V. Capacitors data lines should exhibit less than ohms reactance minimize effects baseline shift. Coupling capacitors clock lines should have less than ohms reactance fundamental clock frequency. Chips that terminate high speed lines equipped with internal bias insert appropriate offset. Coupling capacitors should placed close source possible. destination line terminated line's characteristic impedance. Differential high speed LVPECL inputs (RSDP/N, RSCLKP/N) S3042 terminated internal with resistors line-to-line biased Vcc-0.65V.
Power Ground
Each device power must equipped with decoupling capacitors. capacitors should positioned close power possible. ground-side decoupling capacitors should immediately feed into solid ground plane. power should distributed through solid power plane. Device ground pins should immediately ground plane. Ground should consist single continuous plane encompassing full area. good separate analog digital power feeds isolate each power sub-net. Inductors ferrite beads used should: handle load current without significant drop have self-resonance characteristics that concern specific filtering task. need isolated power plane built internal signal layer.
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PRELIMINARY
EV3041A
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
EVALUATION BOARD LAYOUT
This section provides layer layer design layout EV3041A Evaluation Board.
Figure
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure
EV3041A
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EV3041A
Figure
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure
EV3041A
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EV3041A
Figure
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure
EV3041A
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EV3041A
Figure
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure
EV3041A
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EV3041A
Ordering Information
PREFIX
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
DEVICE
PACKAGE
Evaluation Board
3041
TQFP/TEP
Prefix
XXXX Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (619) 450-9333 (800) 755-2622 Fax: (619) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
March 1999
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