EV3038 EV3038 S3038 evaluation board provides flexible platform v

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EV3038 EV3038 S3038 evaluation board provides flexible platform v

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SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD DESCRIPTION
EV3038 EV3038
S3038 evaluation board provides flexible platform verifying operation S3038 Quad Transceiver interface circuit. This document provides information board contents. should used conjunction with S3038 data sheet, which contains full technical details chips operation. Figure shows outline S3038 evaluation board. Figures contain S3038 evaluation board schematic. Figure shows placement loop filter. Figure shows block diagram S3038 evaluation board should connected test equipment testing. Figure shows jitter generation test Figure contains S3038 jitter tolerance test
Figure Evaluation Board (Top View)
REFCLK
AMCC
OUTPUT
POCLKCP POCLKCN POUTC0 POUTC1 POUTC2 POUTC3 APPLIED MICRO CIRCUITS CORP 6290 SEQUENCE DIEGO, 92121
PECL
VDDA
TTLVDD
SDTTLD OOFD PIND0
TSDC0N
TSDC0P
TSDD0N
TSDB1P
TSDC1N
TSDD1P
PICLKD
PIND1
PIND2
PIND3
PIND4
PIND5
PIND6
PIND7
INPUT
SDTTLC OOFC PINC0 PINC1 PINC2 PINC3 PINC4 PINC5 PINC6 PINC7 PICLKC SDTTLB OOFB PINB0 PINB1 PINB2 PINB3 PINB4 PINB5 PINB6 PINB7 PICLKB SDTTLA OOFA PINA0 PINA1 PINA2 PINA3 PINA4 PINA5 PINC6 PINA7 PICLKA PCLK
TSDA1N
TSDA1P
TSDD0P
TSDB1N
TSDC1P
TSDD1N
INPUT OUTPUT
POCLKDN
POCLKDP
POUTD0 POUTD1
POUTD2
POUTD3
POUTD4
POUTD5
POUTD6
POUTD7
TSDB0P
TSDB0N
POUTC4 POUTC5 POUTC6 POUTC7
TSDA0N
TSDA0P
POCLKBP POCLKBN RSDD1P RSDD1N
S3038 SONET/SDH/AOC-12 QUAD TRANSCEIVER
RSDD0P RSDD0N
POUTB0 POUTB1 POUTB2 POUTB3 POUTB4
RSDC0N
RSDC0P
AMCC
S3038
POUTB5 POUTB6 POUTB7
RSDC1P
RSDC1N POCLKAP POCLKAN POUTA0 POUTA1 POUTA2 POUTA3 RSDB1P RSDB0P RSDA0N RSDA1N
RSDDSEL RSDCSEL RSDBSEL CH_LOCK RSDASEL CLKSEL TMODE
POUTA4 POUTA5 POUTA6 POUTA7
RSDB1N
RSDB0N
RDSA0P
RSDA1P
RESET DLEB
RESET
September 1999
EV3038
SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD
Figure shows schematic S3038 evaluation board.
Figure Board Schematic
POCLKCP POCLKCN POUTC7 POUTC6 POUTC5 POUTC4 POUTC3 POUTC2 POUTC1 POUTC0
POCLKAP POCLKAN POUTA7 POUTA6 POUTA5 POUTA4 POUTA3 POUTA2 POUTA1 POUTA0
POCLKBP POCLKBN POUTB7 POUTB6 POUTB5 POUTB4 POUTB3 POUTB2 POUTB1 POUTB0
RESET REFCLK
POCLKDP POCLKDN POUTD7 POUTD6 POUTD5 POUTD4 POUTD3 POUTD2 POUTD1 POUTD0
CAP1 CAP2
22nF
DLEB DVDD DVSS TMODE CLKSEL
TSDA0P TSDA0N 1.5k TSDA1P TSDA1N 1.5k TSDB0P TSDB0N 1.5k TSDB1P TSDB1N 1.5k TSDC0P TSDC0N 1.5k TSDC1P TSDC1N 1.5k 1.5k 1.5k
0.1uF 1.5k 0.1uF 0.1uF
0.1uF 0.1uF 0.1uF
RSDDSEL RSDCSEL RSDBSEL RSDASEL DVDD DVDD CH_LOCK
1.5k 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1.5k 0.1uF 0.1uF 0.1uF 0.1uF 1.5k 0.1uF
RSDA0P RSDA0N RSDA1P RSDA1N RSDB0P RSDB0N RSDB1P RSDB1N RSDC0P RSDC0N RSDC1P RSDC1N RSDD0P RSDD0N
1.5k
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
S3038
1.5k
1.5k
TSDD0P TSDD0N
TSDD1P TSDD1N 1.5k PCLK
SDTTLC OOFC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PICLKC
SDTTLA OOFA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PICLKA
RSDD1P RSDD1N
SDTTLD OOFD PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PICLKD
SDTTLB OOFB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PICLKB
September 1999
SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD
EV3038
Figure shows power ground schematic, using alias signal names S3038 evaluation board.
Figure Power Ground Schematic
TTL_VDD
TTLPWR 10uF 10uF 0.1uF 100pF 0.1uF 100pF 10uF 0.1uF 100pF 0.1uF 100pF 10uF 0.1uF 100pF 0.1uF 100pF 0.1uF 100pF 0.1uF 100pF
TTLPWR
TTL_VDD
10uF 10uF 0.1uF 100pF 0.1uF 100pF 10uF 0.1uF 100pF 0.1uF 100pF 10uF 0.1uF 100pF 0.1uF 100pF DIGPWR
PECL_VDD
TX_VDD
RX_VDD
10uF 10uF 0.1uF 100pF
10uF 10uF 0.1uF 100pF VDD5 VDDA5
10uF 10uF 0.1uF 100pF VDD1 VDD2 VDD3 VDD4
PECLPWR
RX_VDDA
10uF 10uF 10uF 0.1uF 100pF 0.1uF 100pF 0.1uF 100pF 0.1uF 100pF
VDDA1
VDDA2
VDDA3
VDDA4
VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSS1-5 VSSSUB1-5 A11, B10, C13, A14,
DIGGND DIGGND1 DIGGNDS C3,R3, J15, H16,
PECLGND
September 1999
EV3038
SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD
connections high speed parallel inputs/outputs, clocks, control lines S3038 transceiver shown Figure power ground connections shown Figure high speed inputs (RSDXxP/N) terminated with line-to-line resistance, which assumes characteristic line impedance. lines line-to-line termination should high speed outputs (TSDXxP/N) have pull down resistors which current output. Characterization testing without these pull down resistors shows that removing them will slightly reduce output swing will affect performance. Both inputs outputs shown with decoupling capacitors. value this capacitor critical 0.01µF would work just well. parallel (PINx, POUTx) require external source/termination resistors. parallel outputs internally terminated with series resistors.
Layout Guidelines
Board design with Ball Grid Array (BGA) parts impose limitations pinout density part. Components should mounted both sides board with internal power, ground, signal planes. highest priority should given high speed signals. Vias should kept minimum high speed signals. used, they should kept close possible transmitting receiving part order minimize reflections. Since high speed signals form differential LVPECL pairs, trace lengths should kept minimal equal length maintain constant characteristic impedance. Right angles should avoided since they also source reflections. Passive components should placed close possible source/termination minimize stub lengths maximize signal integrity: pull down resistors should placed from transmit outputs, terminations should placed from receive inputs. There schools thought placement coupling capacitors: they placed close transmit outputs avoid reflections from slight impedance mismatch that pads will introduce into trace, they placed next receiver. Either both implemented. Transmit data jitter generated through main factors: power supply noise reference clock jitter. Careful layout reference clock traces will minimize jitter this line. reference clock trace should short possible. Segmentation power plane (isolation around BGA) provide insurance against power supply noise, introduce ground loops signals adjacent planes cross slot. addition, slots power/ground planes cause issues creating antennas. power plane segmented ground plane should remain solid should placed between power plane signal traces. This will ensure that current return paths remain ground plane, preventing large ground loops current return paths power plane. Alternatives power/ground segmentation separate analog planes, plane-lets signal layer.
September 1999
SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD
Loop Filter
EV3038
Figure below depicts recommended layout minimize jitter transmit data path. Extra care must taken with regard isolating connecting loop filter components CAP1 CAP2 pins. recommended capacitors good quality, 0603 size ceramic capacitors. small size recommended simplify layout, which could become quite congested with terminations other bypass devices. These devices must placed close proximity pins function effectively, recommended that they placed bottom side board depicted below. loop filter should isolated with ground ring (connected AVSS B15) order minimize noise analog section chip.
Figure Loop Filter Connection
CAP1 CAP2
BOTTOM VIEW
September 1999
EV3038
SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD
Power/Ground Information
power ground pins mixed signal devices supply individual functional elements within part. These signals grouped into analog digital supplies, digital supplies further divided into core I/O. AMCC's circuits have specific requirements isolation decoupling. best performance each power ground should decoupled described Table However, there physical constraints imposed density package. minimum power ground PLANES should decoupled points around package. Beyond this, individual pins should decoupled, board space permits, following order: Analog power pins, LVPECL power pins, power pins, then Core power pins.
Table Power Ground Application Information
Function Alias Names Instructions Connect noise filtered 3.3V supply through ferrite bead (600 MHz: Murata BLM31B601S equivalent). Provide local bypassing VSSA inductance resistance (0.1 Vishay VJ0612 equivalent, inductance1 Connect ferrite ground plane. Provide impedance connection 3.3V. Provide local bypassing plane (0.1 Vishay VJ0612 capacitor equivalent, inductance1) Connect ground plane. Provide impedance connection 3.3V. Provide local bypassing plane (0.1 Vishay VJ0612 capacitor, inductance1). Connect ground plane. Provide impedance connection 3.3V. Provide local bypassing plane (0.1 Vishay VJ0612 capacitor, inductance1). Connect ground plane.
VDDA ANALOG VSSA PECLPWR LVPECL PECLGND TTLPWR TTLGND DIGPWR CORE DIGGND DIGGND1 DIGGNDS
caps parallel also used inductance, resistance path, though this takes more board space than single inductance capacitor solution.
September 1999
SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD
EV3038
Figure depicts S3038 evaluation board connected measurements, shows switch settings power supply requirements with test equipment that utilizes ground termination. this configuration S3038 configured with internal S3038 Clock Recovery Unit (CRU), using 77.76 reference operating STS-12.
Figure S3038 Quad Transceiver Test Setup
BERT (622 MHz)
DATA
BERT
DATA CLOCK DATA CLOCK
CLOCK
S3038
RSDA0P RSDA0N TSDA0P TSDA0N
Switch setting normal operation
RESET DLEB TMODE REFCLK CLKSEL (77.76 REFCLK)
HP8133 PULSE GENERATOR DIVIDER
RSDASEL RSDBSEL
(DIV 77.76
RSDCSEL
RSDDSEL
September 1999
EV3038
SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD
Figure depicts S3038 evaluation board connected jitter generation measurements.
Figure S3038 Jitter Generation Test Setup
BERT (622 MHz)
Data Data Clock Clock
S3038
RSDA0P RSDA0N TSDA0P
SJ300
Data
TSDA0N REFCLK
Switch setting normal operation
RESET DLEB TMODE
HP8133 Pulse Generator IN/8
CLKSEL (77.76 REFCLK)
RSDASEL RSDBSEL RSDCSEL RSDDSEL
September 1999
SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD
Figure depicts S3038 evaluation board connected jitter tolerance measurements.
EV3038
Figure S3038 Jitter Tolerance Test Setup
BERT (622 MHz)
DATA DATA CLOCK CLOCK
SJ300
THRU DATA DATA CLOCK
S3038
TSDA0P RSDA0P RSDA0N TSDA0N REFCLK
BERT
DATA
CLOCK
Switch setting normal operation
RESET DLEB TMODE CLKSEL (77.76 REFCLK)
Couple
HP8133 Pulse Generator Power Divider IN/8
RSDASEL RSDBSEL RSDCSEL RSDDSEL
September 1999
EV3038
SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD
Table Power Connections Test Equipment Interface
Power Supply Nominal Input Voltage +3.3V Type Signal LVPECL Couple
Connectors
connectors provided differential serial data input/output signals input clock. Receive Serial Data [RSDA,B,C,DP/N] Differential LVPECL inputs. Serial data inputs S3038. Transmit Serial Data [TSDA,B,C,DP/N] Differential LVPECL outputs. serial output data stream from transmitter section S3038. These outputs coupled. Reference Clock [REFCLK] input. This input must provided with (swing levels dependent power supply voltages) clock 38.88 77.76 MHz.
Parallel Header Terminals
parallel input (PINA,B,C,D[7:0]) output (POUTA,B,C,D[7:0]) data from S3038 transceiver available header arrays evaluation board. Ground columns also provided allow connection with 0.1" grid shielded ribbon cable parallel data sources data analyzers. User selectable jumpers also allow parallel output data (POUTA,B,C,D[7:0]) output byte clock (POCLKA,B,C,DP/N) directly connected transmitter parallel data inputs (PINA,B,C,D[7:0]) parallel input clock (PICLKA,B,C,D). Note: board must supplied with external reference REFCLK proper operation. Parallel Clock [PCLK] output. word rate output reference from transmitter PLL. This output used coordinate byte-wide transfers parallel data bus. Frame Pulse [FPA,B,C,D] output. Indicates frame boundaries incoming data stream (RSDA,B,C,DP/N). Frame [OOFA,B,C,D] LVTTL input. Used enable framing pattern detection logic S3038. Signal Detect [SDTTLA,B,C,D] LVTTL input. Active High. When SDTTL inactive, data RSDA,B,C,DP/N pins will forced constant zero. When active, data will processed normally.
Switches
evaluation board equipped with switches, control static control functions board device. both arrays (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts logic high. Figures through show particular switch settings that needed particular test case. RESET Pushbutton Switch This momentary contact switch controls master reset S3038. Please refer S3038 data sheet details specific control functions. Normal mode this master reset input high. Depressing switch connects this input logic zero resets S3038.
September 1999
SONET/SDH/AOC-12 QUAD TRANSCEIVER EVALUATION BOARD
Ordering Information
PREFIX DEVICE PACKAGE
EV3038
Evaluation Board
3038
Tape
Prefix
XXXX Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
September 1999

EV3038 EV3038 S3038 evaluation board provides flexible platform v

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