EV3037QF EV3037QF S3037 Evaluation Board provides flexible platfo
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SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD DESCRIPTION
EV3037QF EV3037QF
S3037 Evaluation Board provides flexible platform verifying operation S3037 transceiver interface circuit. This data sheet provides information board contents. should used conjunction with S3037 data sheet, which contains full technical details chip operation. Figure shows outline S3037 Evaluation Board, Figure shows block diagram S3037 Evaluation Board should connected test equipment testing. this configuration S3037 configured with internal S3037 Clock Recovery Unit (CRU), using 19.44 77.76 reference operating STS-12.
Figure
REFCLKP
REFCLKN
TTLREF
TSDP
6290 SEQUENCE DRIVE DIEGO, 92121 S3037 SONET/SDH/AOC-12 Transceiver
AMCC
POCLK
TSDN
PCLK PICLK PIN7 AMCC S3037 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
PIN7:0 POUT7:0
RSDP
RSDN
TESTEN
LLEB DLEB
MODE1 MODE0 SLPTIME
SDPECL
RSTB
July 1999
EV3037QF
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure depicts S3037 Evaluation Board connected measurements, shows switch settings LVPECL power supply requirements with test equipment that utilizes ohms ground termination.
Figure
11801A
S3037 NORMAL OPERATION CLK=622.08Mhz, REFCLK=19.44Mhz
TRIG CH.1 TERM. CH.2
70842B
ERROR DETECTOR
DATA CLOCK
DUTVCC
REFCLK
DUTVEE
REFCLKN
70841B
TSDP TSDN
TTLREF
PCLK PICLK PIN7 PIN6 POCLK POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
PATTERN GENERATOR
CLOCKP
622.08Mhz
RSDP RSDN
S3037
PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
CLOCKN DATAP DATAN
TRIG (PATTERN)
RSTB
DIPSWITCH
SWITCH SETTINGS LLEB=1 DLEB=1 SDPECL=1 OOF=0 TESTEN=0 MODE1=0 MODE0=0 SLPTIME=0 -3.3V
PULSE GENERATOR
8133A
HIGH -800mV -1.6V OUTP OUTN
July 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
EV3037QF
Figure depicts S3037 Evaluation boards connected jitter generation testing, shows switch settings power supply requirements with test equipment that utilizes ohms termination. These settings STS-12 testing.
Figure
MICROWAVE LOGIC SJ-300
70842B
ERROR DETECTOR
DATA CLOCK
DATAIN
S3037 JITTER GENERATION CLK=622.08Mhz, REFCLK=19.44Mhz
DUTVCC
REFCLK
DUTVEE
REFCLKN
70841B
TSDP TSDN
TTLREF
PCLK PICLK POCLK PIN7 PIN6 POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
PATTERN GENERATOR
CLOCKP
622.08Mhz
RSDP RSDN
S3037
CLOCKN DATAP DATAN
TRIG (PATTERN)
RSTB
DIPSWITCH
PULSE GENERATOR
8133A
SWITCH SETTINGS LLEB=1 DLEB=1 SDPECL=1 OOF=0 TESTEN=0 MODE1=0 MODE0=0 SLPTIME=0 -3.3V
HIGH -800mV -1.6V OUTP OUTN
July 1999
EV3037QF
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure depicts S3037 Evaluation boards connected jitter transfer testing, shows switch settings power supply requirements with test equipment that utilizes ohms termination. These settings STS-12 testing.
Figure
MICROWAVE LOGIC SJ-300
DATA
RefCLK
70842B
BOARD
ERROR DETECTOR
DATA CLOCK
DATAIN
THRU DATA
S3037 JITTER TRANSFER/TOLERANCE CLK=622.08Mhz, REFCLK=19.44Mhz
DUTVCC
REFCLK
DUTVEE
REFCLKN
70841B
TSDP TSDN
TTLREF
PCLK PICLK PIN7 PIN6 POCLK POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
PATTERN GENERATOR
CLOCKP
622.08Mhz
RSDP RSDN
S3037
PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
CLOCKN DATAP DATAN
TRIG (PATTERN)
RSTB
DIPSWITCH
PULSE GENERATOR
8133A
SWITCH SETTINGS LLEB=1 DLEB=1 SDPECL=1 OOF=0 TESTEN=0 MODE1=0 MODE0=0 SLPTIME=0 -3.3V
HIGH -800mV -1.6V OUTP OUTN
July 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD ELECTRICAL CONNECTIONS
Power Connections
EV3037QF
Terminal posts provided edge board VEE. S3037 Evaluation Board configured with PECL Level Shifted (LSECL) board configured operate with different types standard test equipment. Figures through demonstrate different types input output waveforms that S3037 Evaluation Board output with different voltage settings Table Note I/O's voltage level will change non-standard levels when S3037 Evaluation Board powered different voltage.
Figure
LVPECL +3.3V 2.5V 1.5V Termination Ohms (VCC -2V)
Figure
LVECL -0.8V -1.3V -1.8V 3.3V Termination Ohms
Figure
LSECL +1.2V +0.7V +0.2V -1.3V Termination Ohms
July 1999
EV3037QF
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
vided allow connection with 0.1" grid shielded ribbon cable parallel data sources data analyzers. User selectable jumpers also allow parallel output data (POUT[7:0]) output byte clock (POCLK) directly connected transmitter parallel data inputs (PIN[7:0]) Parallel Input Clock (PICLK). Note: board must supplied with external reference REFCLKP/N proper operation. (See Figure Parallel Clock [PCLK] output. word rate output reference from transmitter PLL. This output used coordinate byte-wide transfers parallel data bus. separate 1-pin header also provided control Connect (NC) MODE[1:0] switch setting. This allows S3037 Evaluation Board STS-3 mode with different reference voltages outlined S3037 data sheet. connect (NC) obtained removing header shorting jumper. There these jumpers, each MODE[1:0] signal. separate 2-pin header provided additional signal identified below: Frame Pulse [FP] output. Indicates frame boundaries incoming data stream (RSDP/N).
external test equipment environment other standard PECL and/or +3.3V Referenced systems interface S3037 Evaluation Board. board shown Figures through powered allow easy connection ground inputs high performance oscilloscopes spectrum analyzers well standard serial Error Rate Testers (BERT testers) Jitter Analyzers. Table illustrates nominal input voltages voltage levels shown Figures through that voltages track with VCC. Connectors connectors provided differential serial data input/output signals output clock. Additional connectors provided optional differential serial input clock, external reference clock optional external Parallel Input clock. Receive Serial Data [RSDP/N] Differential inputs. Serial data inputs S3037. Transmit Serial Data [TSDP/N] Differential outputs. serial output data stream from transmitter section S3037. These outputs drive LVPECL terminated instrument inputs. Reference Clock [REFCLKP/N] Differential inputs. These inputs must provided with differential level (depending power supply voltages) clock 19.44 77.76 selected MODE[1:0] switches switch. These must connected logic state (REFCLKP "1", REFCLKN TTLREF used. Reference Clock [TTLREF] input. These inputs must provided with (swing levels dependent power supply voltages) clock 19.44 77.76 selected MODE[1:0] switches switch. These must tied High REFCLKP/N used. Parallel Header Terminals parallel input (PIN[7:0]) output (POUT[7:0]) data from S3037 transceiver available header array right edge Evaluation Board. Ground columns also pro-
SWITCHES
Evaluation Board equipped with switch, control static control functions on-board devices. (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts logic high. Figures through show particular switch setting that needed particular test case. RSTB Pushbutton Switch This momentary contact switch controls master reset S3037. Please refer S3037 data sheet details specific control functions. Normal mode this master reset input normally high. Depressing switch connects this input logic zero resets S3037.
July 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Table Power Connections Test Equipment Interface
Power Supply Nominal Input Voltage +3.3V -3.3V -1.3V Type Signal LVPECL
EV3037QF
Output Termination Ohms Ohms
LVECL
LSECL
Ohms
July 1999
Figure Schematic
AGND0 3037VCC AGND1 RXAGND0 RXAGND1
3037VEE
LLEB DLEB SDPECL TESTEN MODE1 MODE0 SLPTIME RSTB AGND0 AVCC0 AGND1 AVCC1 RXAGND0 RXAVCC0 RXAGND1 RXAVCC1
AGND0
AGND1
100pF 0.1uF S3037TXVR 100pF 0.1uF
3037VEE
1N4148
1N4148
1N4148
10uF
10uF
2.2uF
TSDN
REFCLKP REFCLKN TTLREF
RSDP
.01uF TSDP
EV3037QF
RSDN
RSDP RSDN RXCAP1 RXCAP2 TSDP TSDN TXCAP1 TXCAP2
REFCLKP REFCLKN
TTLREF
3037VCC
PCLK PICLK PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 POCLK POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RSTB
3037VEE
0.1uF 0.1uF
0.1uF 100pF 0.1uF 100pF 0.1uF 100pF
PCLKGND TXCOREVCC TXCOREGND TXOUTVCC TXOUTGND RSCLKVCC RSCLKGND RXCOREVCC TTLVCC RXCOREGND TTLVCC TTLGND TTLINVCC TTLGND PCLKVCC TTLINGND
0.1uF 100pF
RXAGND0
3037VCC
RXAGND1
0.1uF 100pF 0.1uF 0.1uF 100pF 0.1uF 0.1uF 100pF 0.1uF 0.1uF 100pF
0.1uF 100pF 0.1uF 0.1uF 100pF 0.1uF 0.1uF 100pF 0.1uF 0.1uF
3037VEE
100pF
0.1uF 100pF
3037VCC
3037VCC
100pF
0.1uF 100pF
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
July 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure
EV3037QF
July 1999
EV3037QF
Figure
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
July 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure
EV3037QF
July 1999
EV3037QF
Figure
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
July 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure
EV3037QF
July 1999
EV3037QF
Figure
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
July 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure
EV3037QF
July 1999
EV3037QF
Ordering Information
PREFIX
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
DEVICE
PACKAGE
Evaluation Board
3037
PQFP
Prefix
XXXX Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
July 1999
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