EV3035 EV3035 S3035 evaluation board provides flexible platform v

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EV3035 EV3035 S3035 evaluation board provides flexible platform v

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SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD DESCRIPTION
EV3035 EV3035
S3035 evaluation board provides flexible platform verifying operation S3035 transceiver interface circuit. This document provides information board contents. should used conjunction with S3035 data sheet, which contains full technical details chips operation. Figure shows outline S3035 evaluation board. Figure shows block diagram S3035 evaluation board should connected test equipment Error Rate (BER) testing.
Figure S3035 Evaluation Board View
(TSD0P) TSDP REFCLKP REFCLKN TTLREF 1(51MHZCLK) T51MCLK 1(38MHZCLK) T38MCLK 1(19MHZCLK) T19MCLK 1(Not Used) PARERR POCLK PCLK (TSD0N) TSDN PICLK PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 (TSD1N) TSCLKN PIN1 PIN0
S3035
POUT7:0
PIN7:0
APPLIED MICRO CIRCUITS CORPORATION S3035 SONET/SDH/A0C-3/12 TRANSCEIVER WITH
SQUELCH (RSDSEL)1
(TSD1P) TSCLKP (MODE JUMPERS)
OPEN
RXLOCKDET 1(Not Used) PAROUT
RLPTIME (OE1)1
BYPASS (TESTEN)
PARIN (OE0)1
(RSD0P) RSDP
(RSD0N) RSDN
(RSD1P) RSCLKP
(RSD1N) RSCLKN
Note: Signal names parenthesis names S3035 transceiver. signal names parenthesis signal names actual evaluation board.
RSTB
SLPTIME
SDPECL
TSTRST
MODE1
MODE0
SDTTL
DLEB
LLEB
6290 SEQUENCE DIEGO, 92121
September 1999
EV3035
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure depicts S3035 evaluation board connected measurements, shows switch settings. addition, shows Level Shifted (LSECL) power supply requirements with test equipment that utilizes ground termination. this configuration S3035 configured with internal S3035 Clock Recovery Unit (CRU), using 19.44 reference operating STS-12.
Figure S3035 Error Rate (BER) Test Setup
S3035 TEST
BERT (622MHz)
DATA CLOCK DATA DATA DATA DATA DATA DATA DATA
BERT
S3035
RSD0P 622MHz RSD0N RSD1P RSD1N TSD0N TSD1P TSD1N TSD0P
+1.2V +0.7V +0.2V
LSECL CONFIGURATION
POWER SUPPLY -1.3V SWITCH SETTINGS: TSTRST LLEB RSDSEL SDTTL SDPECL DLEB MODE1 Example MODE0 19.44 operation TESTEN SLPTIME
HP8133 PULSE GENERATOR DIVIDER
REFCLKP
REFCLKN
TTLREF
(DIV 19.44MHz
September 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD ELECTRICAL CONNECTIONS
Power Connections
EV3035
Terminal posts provided edge board VEE. S3035 evaluation board configured with ECL, PECL Level Shifted (LSECL) I/O, board configured operate with different types standard test equipment. Figures through demonstrate different types input output waveforms that S3035 evaluation board operate with different voltage settings Table Note I/O's voltage level will change non-standard levels when S3035 evaluation board powered different voltage. external test equipment environment other standard and/or +3.3V referenced systems interface S3035 evaluation board. board shown Figures powered allow easy connection ground inputs high performance oscilloscopes spectrum analyzers well standard serial Error Rate Testers (BERT) jitter analyzers. Table illustrates nominal input voltages voltage levels shown Figures through Figures show that voltages track with VEE, Figure shows that voltages track with VCC.
Table Power Connections Test Equipment Interface
Power Supply Nominal Input Voltage +3.3V -3.3V -1.3V Type Signal LVPECL Output Termination
LVECL
LSECL
Figure LVECL Signal Waveform
LVECL -0.8V -1.3V -1.8V -3.3V Termination
September 1999
EV3035
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure LVPECL Signal Waveform
LVPECL
+1.2V +0.7V +0.2V -1.3V Termination
Figure LSECL Signal Waveform
LSECL
+3.3V 2.5V 1.5V Termination (VCC -2V)
Connectors connectors provided differential serial data input/output signals. Additional connectors provided optional differential serial input clock, external reference clock optional external parallel input clock. Receive Serial Data [RSD0P/N] Differential LVPECL inputs. Serial data inputs S3035. Labeled RSDP/N evaluation board. Receive Serial Data [RSD1P/N] Differential LVPECL inputs. Serial data inputs S3035. Labeled RSCLKP/N evaluation board. Transmit Serial Data [TSD0P/N] Differential LVPECL outputs. serial output data stream from transmitter section S3035. These outputs drive PECL, ECL, ground terminated instrument inputs depending power supply voltages applied S3035 evaluation board. These connectors labeled TSDP/N evaluation board. Transmit Serial Data [TSD1P/N] Differential LVPECL outputs. serial output data stream from transmitter section S3035. These outputs drive PECL, ECL, ground terminated instrument inputs depending power supply voltages applied S3035 evaluation board. These connectors labeled TSCLKP/N evaluation board Reference Clock [REFCLKP/N] Differential LVPECL inputs. These inputs must provided with
differential level (depending power supply voltages) clock 19.44 MHz, 38.8 MHz, 51.84 77.76 selected MODE[1:0] switches switch. These inputs must connected logic state (REFCLKP "1", REFCLKN TTLREF used. Reference Clock [TTLREF] LVTTL input. These inputs must provided with (swing levels dependent power supply voltages) clock 19.44 MHz, 38.88 MHz, 51.84 77.76 selected MODE[1:0] switches switch. These inputs must tied high REFCLKP/N used. Parallel Header Terminals parallel input (PIN[7:0]) output (POUT[7:0]) data from S3035 transceiver available header array right edge evaluation board. Ground columns also provided allow connection with 0.1" grid shielded ribbon cable parallel data sources data analyzers. User selectable jumpers also allow parallel output data (POUT[7:0]) output byte clock (POCLK) directly connected transmitter parallel data inputs (PIN[7:0]) Parallel Input Clock (PICLK). Note: board must supplied with external reference REFCLKP/N proper operation. (See Figure Parallel Clock [PCLK] LVTTL output. word rate output reference from transmitter PLL. This output used coordinate byte-wide transfers parallel data bus.
September 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
separate 5-pin header also provided three additional signals. three signals identified below: Clock Output [19MHZCLK] LVTTL output. 19.44 output derived from S3035 available header monitoring. This labled T19MCLK evaluation board. Clock Output [38MHZCLK] LVTTL output. 38.88 output derived from S3035 available header monitoring. This labled T38MCLK evaluation board. Clock Output [51MHZCLK] LVTTL output. 51.84 output derived from S3035 available header monitoring. This labled T51MCLK evaluation board. separate 4-pin header also provided control Connect (NC) MODE[1:0] switch setting. This allows S3035 evaluation board STS-3 mode with different reference voltages outlined S3035 data sheet. Connect (NC) obtained removing header shorting jumper. There these jumpers, each MODE[1:0] signal. proper operation least these jumpers must remain connected. separate 4-pin header provided additional signals identified below: Frame Pulse [FP] LVTTL output. Indicates frame boundaries incoming data stream (RSDP/N). Lock Detect [RXLOCKDET] LVTTL output. Indicates that locked onto incoming data stream. This signal High when locked.
EV3035
SWITCHES
evaluation board equipped with switches, control static control functions on-board device. both arrays (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts logic high. Figure shows particular switch settings that needed particular test case. RSTB Pushbutton Switch This momentary contact switch controls master reset S3035. Please refer S3035 data sheet details specific control functions. Normal mode this master reset input High. Depressing switch connects this input logic zero resets S3035.
September 1999
EV3035
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure S3035 Evaluation Board Schematic
T51MCKL
T38MCLK 10µF 10µF T19MCLK used
REFCLKP
REFCLKN
TTLREF
38MHZCLK
51MHZCLK
19MHZCLK
POCLK PCLK PICLK PIN7 PIN6
TSD0P TSD0N
TSD1N TSD1P CAP2 CAP1
PIN5 PIN4 PIN3 PIN2
0.01µF
S3035
PIN1 PIN0
RSD0P RSD0N
TSTRST LLEB RSDSEL SDTTL SDPECL DLEB
RSD1P
TESTEN MODE MODE SLPTIME
RXLOCKDET RSTB
POUT
RSD1N
RXLOCKDET
used
Diodes: 4002 9711
September 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Ordering Information
PREFIX DEVICE PACKAGE
EV3035
Evaluation Board
PQFP
Prefix
XXXX Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
September 1999

EV3035 EV3035 S3035 evaluation board provides flexible platform v

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