EV3033 EV3033 S3033 evaluation board provides flexible platform v

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EV3033 EV3033 S3033 evaluation board provides flexible platform v

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SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD DESCRIPTION
EV3033 EV3033
S3033 evaluation board provides flexible platform verifying operation S3033 transceiver interface circuit. This document provides information board contents. should used conjunction with S3033 data sheet, which contains full technical details chips operation. Figure shows outline S3033 evaluation board. Figure shows block diagram S3033 evaluation board should connected test equipment Error Rate (BER) testing.
Figure S3033 Evaluation Board
TSDN
TSDP
REFCLKP
REFCLKN
TSCLKN
APPLIED MICRO CIRCUITS CORPORATION S3033 SONET/SDH/A0C-3/12 TRANSCEIVER WITH
POCLK 19MHZCLK PCLK TSCLKP PICLK PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 RSDP PIN1 PIN0
POUT7:0 PIN7:0
AMCC
S3033
6290 SEQUENCE DIEGO, 92121
TTLREF
RSDN
MODE1
(MODE JUMPERS)
RLPTIME TSTRST SDPECL
MODE0
RSCLKP
RSTB
SLPTIME
SDTTL
LLEB
DLEB
RSCLKN
September 1999
SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD
EV3033
Figure depicts S3033 evaluation board connected measurements, shows switch settings Level Shifted (LSECL) power supply requirements with test equipment that utilizes ground termination. this configuration S3033 configured using 19.44 reference operating STS-12.
Figure S3033 Test
BERT (622MHz)
DATA DATA CLOCK CLOCK
BERT
DATA CLOCK DATA
+1.2V +0.7V
S3033
RSDP 622MHz RSDN RSCLKP RSCLKN TSDP TSDN TSCLKP TSCLKN POWER SUPPLY
+0.2V
LSECL CONFIGURATION
-1.3V SWITCH SETTINGS: LLEB SDPECL DLEB REFCLKP REFCLKN TTLREF connected (DIV 19.44MHz MODE1 MODE0 SLPTIME SDTTL RLPTIME TSTRST example 19.44MHz operation
HP8133 PULSE GENERATOR DIVIDER
September 1999
SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD
EV3033
Figure depicts S3033 evaluation boards connected measurements jitter testing, shows switch settings power supply requirements with test equipment that utilizes termination. switch settings STS-12 testing.
Figure Error Rate (BER) Measurement Jitter Testing Setup
TEKTRONIX JITTER ANALYZER SJ300 (622.08MHz) THRU DATA REFCLK MEASURE JITTER GENERATION CLOCK DATA INPUT CLOCK JITTERED OUTPUT CLOCK CLOCK -3.3V S3033 DUT(TX) TSCLKN TSDP TSCLKP BERT TX(622.08MHz) RSDP RSDN TSDN REFCLKN CLOCK/CLOCK FF00 PRBS PATTERN DATA DATA HP8133 DIVIDER (DIVIDE Provides Asynchronous Data POWER DIVIDERS NOTE: frequency (10-30Hz) reference clock must Jittered Scope CASCADE MICROTECH TERMINATOR VTT=-2.45V (155.52MHz) -0.8 INPUT LEVEL -1.8
PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 POUT0 POUT1 POUT2 POUT3 POUT4 POUT5 POUT6 POUT7
BERT RX(622.08MHz) PRBS
BERT (622.08MHz) DATA CLOCK 27-1 PRBS DATA PATTERN
DATA OUTPUT CLOCK/CLOCK
S3033 DUT(RX)
RSCLKP/N
-3.3V
-3.3V LVECL BUFFER
RSDP RSDN
PICLK REFCLKP
POCLK REFCLKP REFCLKN
SWITCH SETTING
-3.3V LLEB SDPECL DLEB MODE1 19.44MHz MODE0 OPERATION SLPTIME SDTTL RLPTIME TSTRST
MEASURE DATA Trigger
September 1999
SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD
ELECTRICAL CONNECTIONS Power Connections
EV3033
Terminal posts provided edge board VEE. S3033 evaluation board configured with ECL, PECL Level Shifted (LSECL) board configured operate with different types standard test equipment. Figures through demonstrate different types input output waveforms that S3033 evaluation board output with different voltage settings Table Note I/O's voltage level will change non-standard levels when S3033 evaluation board powered different voltages. external test equipment environment other standard and/or +3.3V referenced systems interface S3033 evaluation board. board shown Figures through powered allow easy connection ground inputs high performance oscilloscopes spectrum analyzers well standard serial Error Rate Testers (BERT) jitter analyzers. Table illustrates nominal input voltages voltage levels shown Figures through Figures show that voltages track with VEE. Figure shows that voltages track with VCC.
Table Power Connections Test Equipment Interface Nominal Power Output Input Type Signal Supply Termination Voltage
+3.3 -3.3 -1.3 LVPECL VCC-2V
LVECL
LSECL
September 1999
SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD
Figure LVECL Signal Waveform
EV3033
LVECL -0.8V -1.3V -1.8V -3.3V Termination
Figure LSECL Signal Waveform
LSECL +1.2V +0.7V +0.2V -1.3V Termination
Figure LVPECL Signal Waveform
LVPECL +3.3V 2.5V 1.5V Termination (VCC -2V)
September 1999
SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD Connectors
EV3033
connectors provided differential serial data clock input/output signals. Additional connectors provided reference clock, external reference clock Receive Serial Data [RSDP/N] Differential LVPECL inputs. Serial data inputs S3033. Receive Serial Clock [RSCLKP/N] Differential LVPECL inputs. These inputs used supply clock input RSDP/N. Transmit Serial Data [TSDP/N] Differential LVPECL outputs. serial output data stream from transmitter section S3033. outputs drive PECL, ECL, ground terminated instrument inputs depending power supply voltages applied S3033 evaluation board. Transmit Clock Output [TSCLKP/N] Differential LVPECL outputs. transmit serial clock that used re-time TSDP/N signal. outputs drive PECL, ECL, ground terminated instrument inputs depending power supply voltages applied S3033 evaluation board. This clock will 622.08 155.52 MHz, depending operating mode. Reference Clock [REFCLKP/N] Differential LVPECL inputs. These inputs must provided with differential level (depending power supply voltages) clock 19.44, 38.88, 51.84, 77.76 selected MODE[1:0] switches switch. These inputs must connected logic state (REFCLKP "1", REFCLKN TTLREF used. Reference Clock [TTLREF] LVTTL input. These inputs must provided with (swing levels dependent power supply voltages) clock 19.44, 38.88, 51.84, 77.76 selected MODE[1:0] switches switch. These inputs must tied high REFCLKP/N used. Parallel Header Terminals parallel input PIN[7:0] output POUT[7:0] data from S3033 transceiver available header array right edge evaluation board. Ground columns also provided allow connection with 0.1" grid shielded ribbon cable parallel data sources data analyzers. User selectable jumpers also allow parallel output data POUT[7:0] output byte clock (POCLK) directly connected transmitter parallel data inputs PIN[7:0] parallel input clock (PICLK). Note: board must supplied with external reference REFCLKP/N proper operation. (See Figure Parallel Clock [PCLK] LVTTL output. 8-bit parallel rate output reference from transmitter PLL. This output used coordinate byte-wide transfers parallel data bus. separate 4-pin header also provided control Connect (NC) MODE[1:0] switch setting. This allows S3033 evaluation board STS-3 mode with different reference voltages outlined S3033 data sheet. Connect (NC) obtained removing header shorting jumper. There these jumpers, each MODE[1:0] signal. proper operation least these jumpers must connected. separate 2-pin header provided additional signal identified below: Frame Pulse [FP] LVTTL output. Indicates frame boundaries incoming data stream (RSDP/N). SWITCHES evaluation board equipped with switches, control static control functions on-board device. both arrays (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts logic high. Figures show particular switch settings that needed particular test case. RSTB Pushbutton Switch This momentary contact switch controls master reset S3033 Please refer S3033 data sheet details specific control functions. Normal mode this master reset input High. Depressing switch connects this input logic zero resets S3033
September 1999
PCLK PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 PICLK SLPTIME MODE0 MODE1
RSDN TSDN
19MHZCLK
RSCLKP
AVCC1
19MHZCLK TTLINGND PCLK TTLINVCC PICLK PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 SLPTIME MODE0 MODE1
RSCLKN POCLK
AVCC0
TSCLKN POUT7 POUT6 POUT5 TSCLKP POUT4 POUT3 POUT2
REFCLKN
TSDP TSDN TXOUTGND TSCLKN TSCLKP SDTTL SDPECL RSDP RSDN RSCLKGND RSCLKVCC RSCLKP RSCLKN RXCOREVCC RXCOREGND DLEB
MODE0 SLPTIME
TSDP TSDN RSDP TSCLKN TSCLKP SDTTL SDPECL RSDN RSCLKP RSCLKN DLEB
19MHZCLK PCLK
PICLK PIN7
TSTRST
LLEB
September 1999
RSDP TSDP
S3033
TTLREF REFCLKN REFCLKP REFCLKP AVCC1
0.01µF
AVCC0 TSTRST TTLREF RLPTIME LLEB POUT0 POUT1
S3033
Figure S3033 Evaluation Board Schematic
RLPTIME SDTTL SDPECL DLEB
TXCOREGND TXCOREVCC TTLREF REFCLKN REFCLKP AVCC1 AGND1 CAP2 CAP1 AGND0 AVCC0 TSTRST LLEB RLPTIME TXOUTVCC POCLK TTLVCC POUT7 POUT6 POUT5 TTLGND POUT4 POUT3 POUT2 TTLVCC POUT1 POUT0 TTLGND RSTB
MODE1
POCLK POUT7 POUT6 POUT5 POUT4 POUT3 POUT2
PIN6
PIN5 PIN4 PIN3 PIN2
SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD
PIN1 PIN0
POUT1 POUT0
EV3033
SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD
Figure S3033 Evaluation Board Schematic
PWR1X3
EV3033
100pF
0.1uF
100pF
0.1uF
100pF
0.1uF
100pF
0.1uF
100pF
0.1uF
0.1uF 100pF
0.1uF 100pF
100pF
0.1uF
100pF
0.1uF
100pF
0.1uF
100pF
0.1uF
0.1uF 100pF
0.1uF 100pF
0.1uF 100pF
September 1999
SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD
Table S3033 Evaluation Board Bill Materials
Count Component Pattern CAP100 Value (opt) 0.01
EV3033
CAP100
CAP100 CAP100
0.01
CC0805 DIODE
0805 DO-35
(opt) 1n4002
HDR9X4 JP1X2
IND400 JP1X2
header9x4 ferrite bead
JP1X3 PWR1X3
JP1X3
September 1999
SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD
Table S3033 Evaluation Board Bill Materials (Continued)
Count Component RC0805 RC0805 Pattern 0805 0805 RES300 Value
EV3033
RES300 RES300
RES8SIPB RES8SIPB RES400 RES400
SIP8 SIP8 RES400 RES400
S3033
s3033
SW-NO SWITCH2DIP
SW-NO SW-DIP2T
dip2
September 1999
SONET/SDH/AOC-12 TRANSCEIVER EVALUATION BOARD
Ordering Information
PREFIX DEVICE PACKAGE
EV3033
Evaluation Board
3033
PQFP/TEP
Prefix
XXXX Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
September 1999

EV3033 EV3033 S3033 evaluation board provides flexible platform v

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