EV3031B EV3031B S3031B Evaluation Board provides flexible platfor
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E4/STM-1/OC-3 AEVALUATION BOARD E4/STM-1/OC-3 AEVALUATION BOARD DESCRIPTION
EV3031B EV3031B
S3031B Evaluation Board provides flexible platform verifying operation S3031B transceiver interface circuit. This data sheet provides information board contents. should used conjunction with S3031B data sheet, which contains full technical details chip operation. Figure shows outline S3031B Evaluation Board Figure shows block diagram S3031B Evaluation Board should connected test equipment testing. this configuration S3031B configured with internal S3031B Clock Recovery Unit (CRU), using 19.44 38.88 reference operating STS-3.
Figure Evaluation Board View
RINVTT TINVTT
DGND
AGND
AVCC
DGND
DVCC
AGND4
DVCC
AGND3
RSDATIN
TSDATIN
XFMR AGND1 TSDATIP RXCABI TESTCLK
RSDATIP
AGND2
RSDATON
TSDATON
AMCC
TXRSTB
RSDATOP
E4/STM-1/ OC-3
TREFCLKOUT
XFRMSTATB
XFRMSTATA
S3031B
TSDATOP
RSCLKON
LOSOUT (LED) RXRSTB
TSCLKON
RSCLKOP XFMR TXMONO
LOSOPT REFSEL LLEB DLEB SERDSEL EQUALSEL
TSCLKOP XFMR RXCBLO
TSTCLKEN DLCV CMISEL XFRMENB XFRMENA SERDATEN
REFCLK
SWITCH1
SWITCH2
LVTTL XTAL OSCILATOR
Header
POCLK POUT0 POUT1 POUT2 POUT3
PIN0 PIN1 PIN2 PIN3
October 1999
EV3031B
E4/STM-1/OC-3 AEVALUATION BOARD
Figure depicts S3031B Evaluation board connected measurements, shows switch settings level shifted (LSECL) power supply requirements with test equipment that utilizes ground termination.
Figure Test Setup
S3031B RECEIVER TEST SETUP
BERT TEKTRONIX ANALYZER
SWITCH SETTINGS EQUALSEL(OPTICAL INPUT) SERDSEL DLEB LLEB REFSEL LOSOPT SERDATEN XFRMENA XFRMENB CMISEL DLCV TSTCLKEN ('1' cable input) ('0' 38.8MHz Refclk) ('1' mode)
DATA DATA
CLOCK CLOCK
RSCLKOP RSCLKON RSDATOP RSDATON RXCABI
(Needed test decoding RXCABI data)
TSCLKOP TSCLKON TSDATOP TSDATON TSDATIP TSDATIN
RXCBLO RSDATIN RSDATIP
SF-60 PDH/SDH ERROR JITTER ANALYZER DATA (CMI ENCODED) CLOCK(155MHz)
S3031B DEMO BOARD
REFCLK BIAS LSECL
DVCC(+5V) DVCC(+5V) +V(+2V) DGND(0V) -V(-3V) DGND(0V) TINVTT(0V) RINVTT(0V) AVCC(+5V) AGND(0V)
BERT
TEKTRONIX GENERATOR
HP8133A
INPUT (155MHz)
INPUT CLOCK CLOCK DATA DATA
TRIGGER CLOCK/8
19MHz
October 1999
BOARD POWER TERMINAL
E4/STM-1/OC-3 AEVALUATION BOARD
EV3031B
Figure depicts S3031B receiver section evaluation board connected measurements jitter testing, shows switch settings power supply requirements with test equipment that utilizes termination.
Figure Receiver Jitter Test Setup
S3031B OPENING TEST SETUP
BIAS LSECL
DVCC(+5V) DVCC(+5V) +V(0V) DGND(0V) -V(-5V) DGND(0V) TINVTT(-2V) RINVTT(-2V) AVCC(+5V) AGND(0V)
BOARD POWER TERMINAL
BERT TX(155.52 MHz)
2^7-1 PRBS DATA PATTERN
DATA DATA CLOCK
S3031B EVALUATION BOARD
RSDATIN
SCOPE
RSDATIP RSDATON TRIGGER RSDATOP RSCLKON
CASCADE MICROTECH TERMINATOR VTT= -2.45V
MEASURE DATA RSCLKOP
2^7-1 PRBS DATA PATTERN
DATA CLOCK CLOCK SWITCH SWITCH SERDATEN XFRMENA XFRMENB CMISEL DLCV TSTCLKEN
DIPSWITCH SETTINGS
BERT (155.52 MHz)
EQUALSEL(OPTICAL INPUT) SERDSEL DLEB LLEB REFSEL LOSOPT
October 1999
EV3031B
E4/STM-1/OC-3 AEVALUATION BOARD
Figure depicts S3031B Transmitter section Evaluation board connected measurements Jitter testing, shows switch settings power supply requirements with test equipment that utilizes ground termination.
Figure Transmitter Jitter Test Setup
S3031B OPENING TEST SETUP
BIAS LSECL
DVCC(+5V) DVCC(+5V) +V(0V) DGND(0V) -V(-5V) DGND(0V) TINVTT(-2V) RINVTT(-2V) AVCC(+5V) AGND(0V)
BERT TX(155.52 MHz)
2^7-1 PRBS DATA PATTERN
DATA DATA CLOCK
S3031B EVALUATION BOARD
TSDATIN
SCOPE
TSDATIP TSDATON TRIGGER TSDATOP TSCLKON
CASCADE MICROTECH TERMINATOR VTT= -2.45V
MEASURE DATA TSCLKOP
2^7-1 PRBS DATA PATTERN
DATA CLOCK CLOCK
DIPSWITCH SETTINGS
SWITCH EQUALSEL(OPTICAL INPUT) SERDSEL DLEB LLEB REFSEL LOSOPT SWITCH SERDATEN XFRMENA XFRMENB CMISEL DLCV TSTCLKEN
BERT (155.52 MHz)
October 1999
BOARD POWER TERMINAL
E4/STM-1/OC-3 AEVALUATION BOARD ELECTRICAL CONNECTIONS
Power Connections
EV3031B
Terminal posts provided edge board VEE. S3031B Evaluation Board configured with ECL, PECL level shifted (LSECL) that board configured operate with different types standard test equipment. Figures through demonstrate different types input output waveforms that S3031B Evaluation Board output with different voltage settings Table Note that I/O's voltage level will change non-standard levels when S3031B Evaluation Board powered different voltage.
Figure
LVECL -0.8V -1.3V -1.8V Termination
Figure
LSECL +1.2V +0.7V +0.2V Termination
October 1999
EV3031B
E4/STM-1/OC-3 AEVALUATION BOARD
external test equipment environment other standard and/or Referenced systems interface S3031B Evaluation Board. board shown Figures through powered allow easy connection ground inputs high performance oscilloscopes spectrum analyzers well standard serial Error Rate Testers (BERT) Jitter Analyzers. Table illustrates nominal input voltages voltage levels shown Figures through Figures show voltages that track with VEE, Figure shows voltages that track with VCC.
Figure
PECL 4.3V 3.9V 3.5V Termination (VCC -2V)
Table Power Connections Test Equipment Interface
Power Supply RINVTT/TINVTT RINVTT/TINVTT RINVTT/TINVTT Nominal Input Voltage +V-2V +V-2V Type Signal PECL Output Termination VCC-2V
LSECL
October 1999
E4/STM-1/OC-3 AEVALUATION BOARD
Connectors
connectors provided differential serial data input/output signals output clock. Additional connectors provided optional differential serial input clock, external reference clock optional external parallel input clock. Receive Serial Data [RSDATIP/N] Differential PECL inputs. Serial Data Inputs S3031B. Clock recovered from transitions these inputs when selected EQUALSEL. Receive Serial Clock [RSCLKOP/N] Differential PECL outputs. This signal phase-aligned with Serial Data (RSDATOP). Receive Serial Data [RSDATOP/N] Differential PECL outputs. This signal data output. either delayed version data input (NRZ mode) decoded data (CMI mode). RSDATOP/N updated falling edge RSCLKOP/N. Transmit Serial Data [TSDATOP/N] Differential PECL outputs. serial output data stream from transmitter section S3031B. outputs drive PECL, ECL, ground terminated instrument inputs depending power supply voltages applied S3031B evaluation board. mode, this signal delayed version incoming data stream (TSDATIP/N). Updated falling edge Serial Clock (TSCLKOP). mode, this signal CMI-encoded version TSDATIP/N. Transmit Serial Clock Output [TSCLKOP/N] Differential PECL outputs. transmit serial clock that used re-time TSDATOP/N signal. outputs drive PECL, ECL, ground terminated instrument inputs depending power supply voltages applied S3031B evaluation board. This signal 155.52 clock that phase aligned with Transmit Serial Data mode. mode, TSCLKOP/N used. Transmit Serial Data [TSDATIP/N] Differential PECL inputs. transmit clock derived from transistions these inputs when SERDSEL high. phase relationship REFCLK required. Either 19.44 38.88 reference operation selected. SERDSEL must logic High transmitter operation with serial data input.
EV3031B
Reference Clock [REFCLK] input. Input used reference receiver absence received serial data. parallel transmit interface mode, REFCLK used reference internal clock frequency synthesizer parallel load clock PIN[3:0] data. Cable [RXCABI] Connected BUFINB BUFINA. Cable [RXCABO] Connected Transformer Driver [XFRMDRVA] used drive transformer electrical interface. Monitor [TXMONO] Connected Transformer Driver [XFRMDRVB]. Used drive monitor transformer electrical interface.
Parallel Header Terminals
parallel input data (PIN[3:0]) parallel output data (POUT[3:0]) Clock (POCLK) available header array lower left edge S3031B Evaluation Board. header containing Transformer Drive Status (XFRMSTATA), Transformer Drive Status (XFRMSTAB), Transmit Reference Clockout (TREFCLKOUT), Transmit Reset (TXRSTB) also supplied board. addition, there access Line Code Violation (LCV), Receiver Reset (RXRSTB), Test Clock (TESTCLK). Ground columns also provided allow connection with 0.1" grid shielded ribbon cable parallel data sources data analyzers.
SWITCHES
Evaluation Board equipped with switches, control static control functions on-board devices. both arrays (open "0") condition switch asserts Logic assigned signal, (closed "1") condition asserts Logic High. Figures show particular switch settings that needed particular test case. Light Emitting Diode (LED) provided clock recovery indicator. This will indicate when locked REFCLK.
October 1999
DVCC
100pf
POUT3
TSTCLKEN
DLCV
PIN3
PIN3
PIN1
PIN2
PIN0
SERDSEL
XFRMDRVA
XFRMDRVB
DLCV
XFRMENA
POUT0
XFRMENB
POUT1
POUT2
POUT0
EQUALSEL SERDSEL
POUT3
POCLK DLEB LLEB REFSEL LOSOPT
DLEB
LLEB
Figure EV3031B Schematic
PIN2 PIN1 PIN0 TXRSTB SERDSEL TREFCLKOUT XFRMENB XFRMSTATA XFRMENA XFRMSTATB TXIOVEE XFRMDRVA XFRMDRVB TXIOVCC DLCV DLEB LLEB POUT0 POUT1
100pf
DVCC DVCC
POCLK
100pf
100pf
100pf
TSDATIP TSDATIN
RSDATIP RSDATIN
BLM32A
100pf
AVCC
TSTCLKEN
BLM32A
DVCC
AVCC
100pf
PIN3 TXINVEE TXINVCC TXCRVCC TXCRVEE REFCLK REFGND SERDATEN TSCLKOP TSCLKON TSVCC TSDATOP TSDATON TSVEE TSDATIP TSDATIN AVCC1 AVEE1 CGND CAP1 CAP2 CGND AVEE0 AVCC0 TSTCLKEN CMISEL TESTCLK AVCC4 BUFINA
POUT2 POUT3 POCLK RXIOVCC RXIOVEEE RXRSTB LOSOUT RSCLKOP RSCLKON RSDATOP RSDATON RSVCC RSDATIP RSDATIN RSVEE AVCC3 AVEE3 CGND CAP3 CAP4 CGND AVEE2 AVCC2 RXCRVCC RXCRVEE REFSEL LOSOPT EQUALSEL
RXRSTB LOSOUT
REFSEL
BUFINB AVEE4 BUFOUT AVCC5 AVCC5 AVEE5 AVEE5 AVEE6 AVCC6 GOUT ANDATIN AVCC7 LOSIN LOSREF AVEE7
BLM32A
BUFIN
GOUT
LOSIN
BUFOUT
ANDATIN
100pf BLM32A AVCC BLM32A AVCC AVCC
100pf
100pf BLM32A GVCC LVCC
LOSREF
DIPSWITCH SETTING:
DVCC DVCC
SERDATEN XFRMENA XFRMENB
EV3031B
DVCC
BLM32A
CMISEL
JP10
POUT2
POUT1
PIN2
DVCC
PIN1
PIN0
BLM32A
BLM32A
DVCC
BLM32A
REFCLK/P REFGND/N SERDATEN
DVCC RVCC BLM32A DVCC DVCC
S3031B
RSCLKOP RSCLKON RSDATOP RSDATON
TSCLKOP TSCLKON TSDATOP TSDATON
TVCC
DVCC
AVCC BLM32A BLM32A
DVCC
CMISEL
BLM32A
EQUALSEL
2.7K 5.0K
LOSOPT
AVCC
AVCC
TINVTT
E4/STM-1/OC-3 AEVALUATION BOARD
October 1999
RINVTT
TSDATIP TSCLKON
MC100EL16
TSDATIP DVCC TSCLKOP
TSCLKON
MC100EL16
TSDATIN TSCLKOP
TINVTT
100K DVCC
MC100EL16
100K
RSDATIN RSDATIP TSDATOP TSDATON
Figure EV3031B Schematic (Continued)
BUFOUT
.01uF
.01uF
BUFIN
GOUT
LOSIN
ANDATIN
LOSREF
GVCC
75pf
.01uF
24pf
.01uF
12pf
2.2K
2.2K
100pF
.01uF
.01uF
100pF
5.6pF(OPT)
October 1999
100K
RSCLKOP RSCLKON
TSDATIN
RSDATIN
MC100EL16
RINVTT
TSDATON
100K
RSDATIP
TSDATOP
MC100EL16
RSCLKOP RSCLKON
E4/STM-1/OC-3 AEVALUATION BOARD
100K
RSDATOP
MC100EL16
RSDATOP 100K RSDATON
MMBD352
RSDATON
CABLE
XFRMDRVA
CABLE
DVCC BLM32A
100pf
AGND1
OSCTTL
AGND2 JP11
AGND3
OUTP
MONITOR
AGND4
REFCLK/P
XFRMDRVB
(see note)
EV3031B
NOTE: ONLY INSTALL WHEN USING EXT. GENERATOR W/50 DRIVE.
REFGND/N
EV3031B
Ordering Information
PREFIX
E4/STM-1/OC-3 AEVALUATION BOARD
DEVICE
PACKAGE
Evaluation Board
3031
PQFP/TEP
Prefix
XXXX Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
October 1999
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