EV3028 SONET/SDH/AOC-12 Transceiver S3028 evaluation board p

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EV3028 SONET/SDH/AOC-12 Transceiver S3028 evaluation board p

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Part Number EV3028 September 1999
EV3028
SONET/SDH/AOC-12 Transceiver
S3028 evaluation board provides flexible platorm verifying operation S3028 transceiver interface circuit. This document provides information board contents layout. should used conjuction with S3028 data sheet, which contains full technical details chips operation.
EVALUATION BOARD
Figure shows placement principle components user accessible interface control points. On-board isolation buffers terminations represented schematically. evaluation board configured operation with either S3026 Clock Recovery Unit (CRU) with buffered access serial data clock inputs S3028. S3026 turn operated using on-board 19MCK output S3028 TTLREF reference, external reference supplied S3026 EXTCLK input.
Figure Board Layout
EV3028 SONET/SDH/AOC-12 Transceiver
September 1999
EVALUATION BOARD
Electrical Connections
Power Connections Terminal posts provided edge board allowing separate control voltage levels input signal termination, S3028 S3026, S3028 output terminations, coupled output buffers. buffers couple translate between external test equipment environment other standard and/or referenced systems supply correct referenced device. separately powered output buffers allow easy connection ground inputs high performance oscilloscopes spectrum analyzers well standard serial Error Rate Testers (BERT) jitter analyzers. Table illustrates nominal input voltages VTT. options paired vertically.
Receive Serial Clock [RSCLKP/N] Buffered differential coupled PECL inputs. These inputs used S3026 serving clock recovery device. stated above, jumper options connect buffered output directly RSCLKP/N inputs S3028 S3026 used. Transmit Serial Data [TSDP/N] Buffered differential PECL outputs. serial output data stream from transmitter section S3028. buffered outputs drive PECL, ECL, ground terminated instrument inputs. Driven inputs must provide termination respective reference. Transmit Clock [TSCLKP/N] Buffered differential PECL outputs. transmit serial clock that used re-time TSDP/N signal. buffered outputs drive PECL, ECL, ground terminated instrument inputs. Driven inputs must provide termination respective reference. External PICLK [EXT PICLK] input. User selectable source jumper parallel input clock transmitter section. Used when external data source driving PIN[7:0] parallel data inputs. S3026 External Reference [S3026 CLK] input. Selectable source jumper reference clock S3026 Clock Recovery Unit (CRU). Jumpers select between this input 19MCK reference provided S3028. Reference Clock [REFCLKP/N] Buffered differential coupled PECL inputs. These inputs must provided with differential ECL/PECL clock 19.44, 38.88, 51.84, 77.76 selected REFSEL[1:0] switches section switch. Parallel Headers parallel input output data from S3028 transceiver available header array right edge evaluation board. Figure identifies columns signal pairs. Ground columns also provided allow connection with 0.1" grid shielded ribbon cable parallel data sources data analyzers. User selectable jumpers also allow receiver parallel data output (POUT[7:0]) parallel word clock output (POCLK) directly connected transmitter parallel data inputs (PIN[7:0]) parallel input clock (PICLK). this mode, POCLK should connected REFCLKN input on-board jumper, when S3026 installed, S3026 must used S3026 reference. Note: board must supplied with external reference REFCLKP/N, S3026 RSCLKP/N proper operation.
Table Power Connections Test Equipment Interface
Power Supply Nominal Input Voltage 5.0V 0.0V 3.0V -3.0V 0.0V -5.0V 2.0V 5.0V 0.0V
Connectors coaxial connectors provided different serial data input/output signals output clock. Additional connectors provided optional differential serial input clock, external reference clock optional External Parallel Input Clock (EXT PICLK). Figure locations. Receive Serial Data [RSDP/N] Buffered differential coupled PECL inputs. Jumper options connect buffered signal on-board S3026 where serial clock recovered from transitions these inputs. These inputs also directly connected RSDP/N inputs S3028 alternate jumper options. this mode RSCLKP/N inputs must provided with correctly aligned serial clock. Onboard termination provided.
EV3028 SONET/SDH/AOC-12 Transceiver
September 1999
EVALUATION BOARD
separate header also provided four additional signals. four signals identified Figure Parallel Clock [PCLK] output. word rate output reference from transmitter PLL. This output used coordinate byte-wide transfers parallel data bus. Frame Pulse [FP] output. Indicates detection SONET/SDH framing pattern. Lock Detect [LOCKDET] output. Indicates that transmitter properly locked reference clock input. Clock [19MCK] output. 19.44 output derived from S3028 available header monitoring, jumper connectable internally reference S3026. Note: This reference mode recommended when operating parallel loopback mode. Ground pins provided adjacent PCLK 19MCK pins allow shielded twisted pair connection these clocking signals. four section switch allows control static inputs S3026. switch, when allows S3026 recover clock from serial data stream. will force S3026 lock reference clock. BYPASS should normal operation. LCKREFN when OFF, will also force S3026 lock reference clock. This switch should clock recovery operation. MODE switch, when allows operation 622.08 Mbit/s. selects 155.52 Mbit/s. twelve section switch controls operating modes S3028. Please note that generally advisable operate S3028 S3026 similar least compatible modes. POCLK from receiver being used reference clock transmitter, REFSEL[1:0] switches must same frequency word rate determined BUSWIDTH MODE switches S3028 MODE switch S3026. RSTB Pushbutton Switch This momentary contact switch controls master reset S3028. Please refer S3028 data sheet details specific control functions.
Switches
evaluation board equipped with switch arrays, four station array twelve station array, control static control functions onboard devices. both arrays, (open) condition switch asserts logic assigned signal, condition asserts logic high.
EV3028 SONET/SDH/AOC-12 Transceiver
September 1999
EVALUATION BOARD
Ordering Information
Prefix Evaluation Board Device 3028 3026 Package PQFP TSSOP
Prefix
XXXX
Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation.

EV3028 SONET/SDH/AOC-12 Transceiver S3028 evaluation board p

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