EV3019 EV3019 S3019 evaluation board provides flexible platform v

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

EV3019 EV3019 S3019 evaluation board provides flexible platform v

Datasheet Thumbnail

Top Searches for this datasheet

SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD DESCRIPTION
EV3019 EV3019
S3019 evaluation board provides flexible platform verifying operation S3019 transceiver interface circuit. This document provides information board contents. should used conjunction with S3019 data sheet, which contains full technical details chips operation. Figure shows outline S3019 evaluation board. Figure shows block diagram S3019 evaluation board should connected test equipment Error Rate (BER) testing. Figure shows test setup measurements jitter testing.
Figure S3019 Evaluation Board View
TSDP REFCLKP REFCLKN TTLREF T51MCLK T38MCLK T19MCLK PARERR POCLK PCLK TSDN
S3019
PICLK PIN7 PIN6 PIN5 PIN4 PIN3 PIN2
TSCLKN
PIN1
POUT7:0
PIN7:0
OPEN
APPLIED MICRO CIRCUITS CORPORATION S3019 SONET/SDH/A0C-3/12 TRANSCEIVER WITH
TSCLKP (MODE JUMPERS)
RXLOCKDET PAROUT
SQUELCH
SLPTIME BYPASS SDPECL MODE1 MODE0 SDTTL PARIN DLEB
RSDP RSDN RSCLKP RSCLKN
September 1999
RSTB
RLPTIME
TSTRST
LLEB
6290 SEQUENCE DIEGO, 92121
PIN0
EV3019
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure depicts S3019 evaluation board connected measurements, shows switch settings. addition, shows Level Shifted (LSECL) power supply requirements with test equipment that utilizes ground termination. this configuration S3019 configured with internal S3019 Clock Recovery Unit (CRU), using 19.44 reference operating STS-12.
Figure S3019 Error Rate (BER) Test Setup
S3019 TEST
BERT (622MHz)
DATA CLOCK DATA CLOCK CLOCK DATA DATA CLOCK CLOCK
BERT
S3019
RSDP 622MHz RSDN RSCLKP RSCLKN TSDN TSCLKP TSCLKN TSDP
+1.2V +0.7V +0.2V
LSECL CONFIGURATION
POWER SUPPLY -1.3V SWITCH SETTINGS: TSTRST LLEB TIME SQUELCH SDTTL SDPECL DLEB MODE1 Example MODE0 19.44 operation BYPASS SLPTIME PARIN
HP8133 PULSE GENERATOR DIVIDER
REFCLKP
REFCLKN
TTLREF connected
(DIV 19.44MHz
Note: When using internal CRU, CLOCK CLOCK does need connected RSCLKP RSCLKN.
September 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
EV3019
Figure depicts S3019 evaluation boards connected measurements jitter testing, shows switch settings. addition, shows power supply requirements with test equipment that utilizes termination. These settings STS-12 testing.
Figure S3019 Evaluation Board Measurement Jitter Testing Setup
BERT RX(622.08MHz) 27-1 PRBS TEKTRONIX JITTER ANALYZER SJ300(622.08MHz) THRU DATA REFCLK MEASURE JITTER GENERATION CLOCK DATA INPUT CLOCK JITTERED DATA OUTPUT OUTPUT CLOCK CLOCK DATA CLOCK BERT TX(622.08MHz) 27-1 PRBS DATA PATTERN
-3.3V
S3019 DUT(TX)
S3019 DUT(RX)
POUT POUT POUT POUT POUT POUT POUT POUT7
-3.3V -3.3V LVECL BUFFER RSDP RSDN
BERT TX(622.08MHz)
TSCLKN TSDP TSDN TSCLKP RSDP RSDN TSDN
PICLK
POCLK REFCLKPREFCLKN
REFCLKN REFCLKP FF00 (HEX) PRBS PATTERN DATA DATA
HP8133 DIVIDER (DIVIDE PROVIDES ASYNCRONOUS DATA POWER DIVIDERS *Note: frequency (10-30Hz), reference clock must jittered. Scope CASCADE MICROTECH TERMINATOR VTT=-2.45V (155.52MHz)
-0.8 INPUT LEVEL -1.8
SWITCH SETTING
TSTRST LLEB RLPTIME SQUELCH SDTTL SDPECL DLEB BYPASS MODE1 19.44MHz MODE0 OPERATION SLPTIME PARIN
MEASURE DATA Trigger
September 1999
EV3019
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
ELECTRICAL CONNECTIONS
Power Connections
Terminal posts provided edge board VEE. S3019 evaluation board configured with ECL, PECL Level Shifted (LSECL) I/O, board configured operate with different types standard test equipment. Figures through demonstrate different types input output waveforms that S3019 evaluation board operate with different voltage settings Table Note I/O's voltage level will change non-standard levels when S3019 evaluation board powered different voltage. external test equipment environment other standard and/or +3.3V referenced systems interface S3019 evaluation board. board shown Figures through powered allow easy connection ground inputs high performance oscilloscopes spectrum analyzers well standard serial Error Rate Testers (BERT) jitter analyzers. Table illustrates nominal input voltages voltage levels shown Figures through Figures show that voltages track with VEE, Figure shows that voltages track with VCC.
Table Power Connections Test Equipment Interface
Power Supply Nominal Input Voltage +3.3V -3.3V -1.3V Type Signal LVPECL Output Termination
LVECL
LSECL
Figure LVECL Signal Waveform
LVECL -0.8V -1.3V -1.8V -3.3V Termination
September 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure LSECL Signal Waveform
LSECL +1.2V +0.7V +0.2V -1.3V Termination
EV3019
Figure LVPECL Signal Waveform
LVPECL +3.3V 2.5V 1.5V Termination (VCC -2V)
Connectors connectors provided differential serial data input/output signals output clocks. Additional connectors provided optional differential serial input clock, external reference clock optional external parallel input clock. Receive Serial Data [RSDP/N] Differential LVPECL inputs. Serial data inputs S3019. Receive Serial Clock [RSCLKP/N] Differential LVPECL inputs. These inputs used bypass mode supply clock input RSDP/N. This should tied logic zero when bypass mode. Transmit Serial Data [TSDP/N] Differential LVPECL outputs. serial output data stream from transmitter section S3019. outputs drive PECL, ECL, ground terminated instrument inputs depending power supply voltages applied S3019 evaluation board. Transmit Clock Output [TSCLKP/N] Differential LVPECL outputs. transmit serial clock that used re-time TSDP/N signal. outputs drive PECL, ECL, ground terminated instrument inputs depending power supply voltages applied S3019 evaluation board. This clock will 622.08 155.52 MHz, depending operating mode. Reference Clock [REFCLKP/N] Differential LVPECL inputs. These inputs must provided with differential level (depending power supply voltages) clock 19.44 MHz, 38.8 MHz, 51.84 77.76 selected MODE[1:0] switches switch. These inputs must connected logic state (REFCLKP "1", REFCLKN TTLREF used. Reference Clock [TTLREF] LVTTL input. These inputs must provided with (swing levels dependent power supply voltages) clock 19.44 MHz, 38.88 MHz, 51.84 77.76 selected MODE[1:0] switches switch. These inputs must tied high REFCLKP/N used. Parallel Header Terminals parallel input (PIN[7:0]) output (POUT[7:0]) data from S3019 transceiver available header array right edge evaluation board. Ground columns also provided allow connection with 0.1" grid shielded ribbon cable parallel data sources data analyzers. User selectable jumpers also allow parallel output data (POUT[7:0]) output byte clock (POCLK) directly connected transmitter parallel data inputs (PIN[7:0]) Parallel Input Clock (PICLK). Note: board must supplied with external reference REFCLKP/N proper operation. (See Figure Parallel Clock [PCLK] LVTTL output. word rate output reference from transmitter PLL. This output used coordinate byte-wide transfers parallel data bus. separate 5-pin header also provided four additional signals. four signals identified below: Clock Output [T19MCLK] LVTTL output. 19.44 output derived from S3019 available header monitoring. Clock Output [T38MCLK] LVTTL output. 38.88 output derived from S3019 available header monitoring.
September 1999
EV3019
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD SWITCHES
evaluation board equipped with switches, control static control functions on-board device. both arrays (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts logic high. Figures show particular switch settings that needed particular test case. RSTB Pushbutton Switch This momentary contact switch controls master reset S3019. Please refer S3019 data sheet details specific control functions. Normal mode this master reset input High. Depressing switch connects this input logic zero resets S3019.
Clock Output [T51MCLK] LVTTL output. 51.84 output derived from S3019 available header monitoring. Parity Error [PARERR] LVTTL output. Indicates that parity error been detected PIN[7:0] data Parity Input (PARIN) previous data bus. separate 4-pin header also provided control Connect (NC) MODE[1:0] switch setting. This allows S3019 evaluation board STS-3 mode with different reference voltages outlined S3019 data sheet. Connect (NC) obtained removing header shorting jumper. There these jumpers, each MODE[1:0] signal. proper operation least these jumpers must remain connected. separate 4-pin header provided three additional signals identified below: Frame Pulse [FP] LVTTL output. Indicates frame boundaries incoming data stream (RSDP/N). Parity Output [PAROUT] LVTTL output. parity calculated POUT[7:0] output. Lock Detect [RXLOCKDET] LVTTL output. Indicates that locked onto incoming data stream. This signal high when locked.
September 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure S3019 Evaluation Board Schematic
EV3019
T51MCKL
T38MCLK 10µF 10µF T19MCLK PARERR
51MHZCLK
38MHZCLK
19MHZCLK
REFCLKP
REFCLKN
PARERR
TTLREF
TSDP TSDN
POCLK PCLK PICLK PIN7 PIN6 PIN5
TSCLKN TSCLKP CAP2 CAP1
PIN4 PIN3 PIN2 PIN1
0.01µF
S3019
PIN0
RSDP RSDN
TSTRST LLEB RLPTIME SQUELCH SDTTL SDPECL DLEB
BYPASS MODE MODE SLPTIME PARIN
RSCLKP RSCLKN
RXLOCKDET PAROUT RSTB
POUT
RXLOCKDET
PAROUT
Diodes: 4002 9711
September 1999
EV3019
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure Evaluation Board Layout View
September 1999
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
Figure Evaluation Board Layout Bottom View
EV3019
September 1999
EV3019
Ordering Information
PREFIX
SONET/SDH/ASTS-12 TRANSCEIVER EVALUATION BOARD
DEVICE
PACKAGE
Evaluation Board
3019
PQFP
Prefix
XXXX Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
September 1999

EV3019 EV3019 S3019 evaluation board provides flexible platform v

Top Searches for this datasheet

Other recent searches