EV2065 Quad Serial Backplane Device with Dual EVALUATION BOA
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Part Number EV2065 Revision November 1999
EV2065
Quad Serial Backplane Device with Dual
EVALUATION BOARD
S2065 evaluation board provides flexible platform verifying operation S2065 Quad Serial Backplane Device with Dual I/O. This document provides information evaluation board's contents. should used conjunction with S2065 product data sheet. Contact your local AMCC field applications engineer regional sales manager discuss questions concerns have. EV2065 Contents S2065 evaluation board EV2065 Device Specification (This document) Four minicoax cables loop back clock parallel loopback configuration) Board Description view EV2065 evaluation board shown Figure high speed differential LVPECL receive RXxP/N, transmit TXxP/N, where through brought connectors, shown left side board.
Figure S2065 Evaluation Board
VDDA PECL
REFCLK
S2065 Evaluation Board
AMCC
OUTPUT INPUT RCCP RCCN ERRC KFLAGC DOUTC7 DOUTC6 DOUTC5 DOUTC4 DOUTC3 DOUTC2 DOUTC1 DOUTC0 EOFC RCBP RCBN ERRB KFLAGB DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 EOFB RCAP RCAN ERRA KFLAGA DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 EOFA CH_LOCK RESET SOFC KGENC DINC7 DINC6 DINC5 DINC4 DINC3 DINC2 DINC1 DINC0 TCLKC SOFB KGENB DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TCLKB SOFA KGENA DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TCLKA TCLK0
TX1CN
TX1CP
TX1DN
TX2BP
TX2CN
TX2DP
TX2AN
TX2AP
TX1DP
TX2BN
TX2CP
TX2DN
RCDP RCDN ERRD KFLAGD DOUTD7 DOUTD6 DOUTD5 DOUTD4 DOUTD3 DOUTD2 DOUTD1 DOUTD0 EOFD
TX1BP
TX1BN
TX1AN
TX1AP
RX2DP RX2DN
AMCC
RX1BP RX1AN RX2AN
RX1DP RX1DN
RX1CN RX1CP
RX2CP RX2CN
RX2BP
RESET LPEN RATE MODE-10 TMODE CLKSEL
S2065
RX2BN
RX1BN
RX1AP
RX2AP
AMCC Confidential Proprietary
RXSELD RXSELC RXSELB RXSELA CMODE
SOFD KGEND DIND7 DIND6 DIND5 DIND4 DIND3 DIND2 DIND1 DIND0 TCLKD
EV2065 Quad Serial Backplane Device with Dual
Revision November 1999
EVALUATION BOARD
reference clock brought through connector labeled REFCLK. Power ground brought through connector board. S2065 voltage specified 3.3V Parallel Inputs/Outputs brought connector banks right side board; there connector bank each channel through Input output static control signals controlled with switches bottom board. switch settings outlined Tables Moving switch position creates logic (High), moving away from setting creates logic (Low). addition switches, control signals brought headers. jumpers must installed (between middle bottom pins) switches utilized. header ground, labeled. Several component sites board intentionally populated, including lower left corner (labled Hewlett Packard). These designed into board factory testing, required demonstration purposes.
Table Switch Settings
Name RESET LPEN Description When Low, S2065 held reset. When High, S2065 operates normally. Loopback Enable. When Low, device performs normal transceiver operation. When High, serial output each channel looped back input. serial outputs squelched when LPEN High. When Low, S2065 operates with serial output rate equal frequency. When High, S2065 operates with internally divided functions. Test signal. connected. Transmit Mode Control. When TMODE Low, REFCLK used clock data DINx[7:0], SOFx, KGENx into S2065. When TMODE High, TCLKx used clock data into S2065. Channel Lock mode (CH_LOCK HIGH), four channels clocked TCLKA. independent mode (CH_LOCK LOW) each channel clocked respective TCLK. REFCLK Select input. This signal configures appropriate REFCLK frequency. When CLKSEL REFCLK frequency should equal parallel word rate. When CLKSEL REFCLK frequency should parallel word rate (and internally multiplied).
RATE MODE-10 TMODE
CLKSEL
AMCC Confidential Proprietary
EV2065 Quad Serial Backplane Device with Dual
Table Switch Settings
Name RXSELD RXSELC RXSELB RXSELA LC_BYP CMODE
Revision November 1999
EVALUATION BOARD
Description Channel Input Select Control. selects input RX1D, High selects RX2D. (Internal pull-up when connected). Channel Input Select Control. selects input RX1C, High selects RX2C. (Internal pull-up when connected). Channel Input Select Control. selects input RX1B, High selects RX2B. (Internal pull-up when connected). Channel Input Select Control. selects input RX1A, High selects RX2A. (Internal pull-up when connected). Test signal. connected. Clock Mode Control receiver data stream. When Low, rate parallel output clock (RCxP/N) data rate, ping/pong clocking. When High, rate parallel output clock (RCxP/N) equal data rate. Channel Lock Mode Control. Parallel input mode control. When High, locks four channels together. (See S2065 data sheet). When Low, provides independent channel operation.
CH_LOCK
Test Setups
Typical tests performed with S2065 evaluation board Error Rate Testing (BERT) jitter testing. each case easiest configure evaluation board serial input/output, looping back parallel input/output with jumpers. serial input/output (parallel loopback) configuration shown Figure described below. switch settings parallel loopback: RESET LPEN RATE MODE-10 TMODE CLKSEL RXSELD RXSELC RXSELB RXSELA LC_BYP CMODE CH_LOCK HIGH HIGH (determined desired serial data rate) connect HIGH HIGH (determined desired reference clock rate) HIGH (determined desired input) HIGH (determined desired input) HIGH (determined desired input) HIGH (determined desired input) connect HIGH
AMCC Confidential Proprietary
EV2065 Quad Serial Backplane Device with Dual
Revision November 1999
EVALUATION BOARD
order configure board parallel loopback, parallel input data must clocked into device with TCLKx input clocks shown Figure This clock provided looping RCxP output clock back into respective TCLKx input with minicoax cables provided EV2065 Kit. These cables need only connected channel(s) under test.
Figure Parallel Loopback Configuration
VDDA PECL
REFCLK
S2065 Evaluation Board
SOFD KGEND DIND7 DIND6 DIND5 DIND4 DIND3 DIND2 DIND1 DIND0 TCLKD
AMCC
OUTPUT INPUT RCCP RCCN ERRC KFLAGC DOUTC7 DOUTC6 DOUTC5 DOUTC4 DOUTC3 DOUTC2 DOUTC1 DOUTC0 EOFC RCBP RCBN ERRB KFLAGB DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 EOFB RCAP RCAN ERRA KFLAGA DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 EOFA CH_LOCK RESET SOFC KGENC DINC7 DINC6 DINC5 DINC4 DINC3 DINC2 DINC1 DINC0 TCLKC SOFB KGENB DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TCLKB SOFA KGENA DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TCLKA TCLK0
TX1CN
TX1CP
TX1DN
TX2BP
TX2CN
TX2DP
TX2AN
TX2AP
TX1DP
TX2BN
TX2CP
TX2DN
RCDP RCDN ERRD KFLAGD DOUTD7 DOUTD6 DOUTD5 DOUTD4 DOUTD3 DOUTD2 DOUTD1 DOUTD0 EOFD
TX1BP
TX1BN
TX1AN
TX1AP
RX2DP RX2DN
AMCC
RX1BP RX1AN RX2AN
RX1DP RX1DN
RX1CN RX1CP
RX2CP RX2CN
RX2BP
RESET LPEN RATE MODE-10 TMODE CLKSEL
S2065
RX2BN
RX1BN
RX1AP
RX2AP
RXSELD RXSELC RXSELB RXSELA CMODE
AMCC Confidential Proprietary
EV2065 Quad Serial Backplane Device with Dual Schematic Bill Materials
Revision November 1999
EVALUATION BOARD
Figures provide schematic representation EV2065 evaluation board. bill materials outlined Tables
Figure EV2065 Schematic
AMCC Confidential Proprietary
EV2065 Quad Serial Backplane Device with Dual
Figure EV2065 Power Ground Connections
Revision November 1999
EVALUATION BOARD
AMCC Confidential Proprietary
EV2065 Quad Serial Backplane Device with Dual
Table S2065 Evaluation Board Bill Materials
Quantity Component Value 0.022 HD12D HD22 HD26 S2065
Revision November 1999
EVALUATION BOARD
Designators SMA1 SMA2 SMA3 SMA4 SMA5 SMA6 SMA7 SMA8 SMA9 SMA10 SMA11 SMA12 SMA13 SMA14 SMA15 SMA16 SMA17 SMA18 SMA19 SMA20 SMA21 SMA22 SMA23 SMA24 SMA25 SMA26 SMA27 SMA28 SMA29 SMA30 SMA31 SMA32 SMA33
SW-DIP7
Table S2065 Power Ground Bill Materials
Quantity Component Value Designators
BLM11A60 S2065_PWR TB-8
AMCC Confidential Proprietary
EV2065 Quad Serial Backplane Device with Dual
Ordering Information
Prefix Evaluation Board Device 2065
Revision November 1999
EVALUATION BOARD
Package TBGA
Prefix
XXXX
Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation. AMCC Confidential Proprietary
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