EV2064 Quad Serial Backplane Device EVALUATION BOARD S2

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EV2064 Quad Serial Backplane Device EVALUATION BOARD S2

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Part Number EV2064 Revision November 1999
EV2064
Quad Serial Backplane Device
EVALUATION BOARD
S2064 evaluation board provides flexible platform verifying operation S2064 Quad Serial Backplane device. This document provides information evaluation board's contents. should used conjunction with S2064 product data sheet. Contact your local AMCC field applications engineer regional sales manager discuss questions concerns have. EV2064 Contents S2064 evaluation board EV2064 Device Specification (This document) Four minicoax cables loop back clock parallel loopback configuration) Board Description view EV2064 evaluation board shown Figure high speed differential LVPECL receive RXxP/N, transmit TXxP/N, where through brought connectors shown left side board.
Figure S2064 Evaluation Board
SOFD KGEND DIND7 DIND6 DIND5 DIND4 DIND3 DIND2 DIND1 DIND0 TCLKD
PECL VDDA
S2064 Evaluation Board
AMCC
RCCP RCCN ERRC KFLAGC DOUTC7 DOUTC6 DOUTC5 DOUTC4 DOUTC3 DOUTC2 DOUTC1 DOUTC0 EOFC RCBP RCBN ERRB KFLAGB DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 EOFB RCAP RCAN ERRA KFLAGA DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 EOFA
TX1CN TX1CP RCDP RCDN ERRD KFLAGD DOUTD7 DOUTD6 DOUTD5 DOUTD4 DOUTD3 DOUTD2 DOUTD1 DOUTD0 EOFD
SOFC KGENC DINC7 DINC6 DINC5 DINC4 DINC3 DINC2 DINC1 DINC0 TCLKC SOFB KGENB DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TCLKB SOFA KGENA DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TCLKA TCLK0
TX1BP
TX1BN
TX1AN
TX1AP
RX1DP
RX1DN
AMCC
RX1CP
RX1CN
RX1BP RX1BN
RX1AN
RX1AP
RESET
RESET LPEN RATE TMODE CLKSEL CMODE CH-LOCK/TESTMODE
DIPSWITCH
S2064
AMCC Confidential Proprietary
INPUT
TX1DP
TX1DN
REFCLK
OUTPUT
EV2064 Quad Serial Backplane Device
Revision November 1999
EVALUATION BOARD
reference clock brought through connector labeled REFCLK. Power ground brought through connector board. S2064 voltage specified 3.3V Parallel brought connector banks right side board; there connector bank each channel through Input output static control signals controlled with switch bottom board. switch settings outlined Table Moving switch position creates logic (High), moving away from setting creates logic (Low).
Table Switch Settings
Name RESET LPEN Description When Low, S2064 held reset, When High, S2064 operates normally. Loopback Enable. When Low, device performs normal transceiver operation. When High serial output each channel looped back input. serial outputs squelched when LPEN High. When S2064 operates with serial output rate equal frequency. When High S2064 operates with internally divided functions. Transmit Mode Control. When TMODE Low, REFCLK used clock data DINx[7:0], SOFx, KGENx into S2064. When TMODE High, TCLKx used clock data into S2064. Channel Lock mode (CH_LOCK HIGH), four channels clocked TCLKA. independent mode (CH_LOCK LOW) each channel clocked respective TCLK. REFCLK Select input. This signal configures appropriate REFCLK frequency. When CLKSEL REFCLK frequency should equal parallel word rate. When CLKSEL REFCLK frequency should parallel word rate (and internally multiplied). Clock Mode Control receiver data stream. When Low, rate parallel output clock (RCxP/N) data rate, ping/pong clocking. When High, rate parallel output clock (RCxP/N) equal data rate. Parallel input mode control. Channel Lock High locks four channels together. (see Device Specification). Channel Lock provides independent channel operation.
RATE TMODE
CLKSEL
CMODE
CH_LOCK/TESTMODE
Test Setups typical test performed with S2064 evaluation board jitter testing. each case easiest configure evaluation board serial I/O, looping back parallel with jumpers. Serial (parallel loopback) configuration shown Figure described below. switch settings parallel loopback: RESET LPEN RATE TMODE CLKSEL CMODE CH-LOCK/TEST MODE HIGH HIGH (determined desired serial data rate) HIGH HIGH (determined desired reference clock rate) HIGH
order configure board parallel loopback, parallel input data must clocked into device with TCLKx input clocks shown Figure This clock provided looping RCxP output clock back into respective TCLKx input with minicoax cables provided EV2064 Kit. These cables need only connected channel(s) under test.
AMCC Confidential Proprietary
EV2064 Quad Serial Backplane Device
Revision November 1999
EVALUATION BOARD
Figure Parallel Loopback Configuration
SOFD KGEND DIND7 DIND6 DIND5 DIND4 DIND3 DIND2 DIND1 DIND0 TCLKD
PECL VDDA
S2064 Evaluation Board
AMCC
RCCP RCCN ERRC KFLAGC DOUTC7 DOUTC6 DOUTC5 DOUTC4 DOUTC3 DOUTC2 DOUTC1 DOUTC0 EOFC RCBP RCBN ERRB KFLAGB DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 EOFB RCAP RCAN ERRA KFLAGA DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 EOFA
TX1CN TX1CP RCDP RCDN ERRD KFLAGD DOUTD7 DOUTD6 DOUTD5 DOUTD4 DOUTD3 DOUTD2 DOUTD1 DOUTD0 EOFD
SOFC KGENC DINC7 DINC6 DINC5 DINC4 DINC3 DINC2 DINC1 DINC0 TCLKC SOFB KGENB DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TCLKB SOFA KGENA DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TCLKA TCLK0
TX1BP
TX1BN
TX1AN
TX1AP
RX1DP
RX1DN
AMCC
RX1CP
RX1CN
RX1BP RX1BN
RX1AN
RX1AP
RESET
RESET LPEN RATE TMODE CLKSEL CMODE CH_LOCK/TESTMODE
DIPSWITCH
S2064
Note: following names S2064 data sheet labeled differently board: NAMES DOUTx8 DOUTx9 DINx8 DINx9 RBC1x RBC0x COM_DETx BOARD LABEL KFLAGx ERRx KGENx SOFx TCLKx RCxP RCxN EOFx
AMCC Confidential Proprietary
INPUT
TX1DP
TX1DN
REFCLK
OUTPUT
EV2064 Quad Serial Backplane Device
Revision November 1999
EVALUATION BOARD
Schematic/Bill Materials
Figures provide schematic representation S2064 evaluation board. bill materials outlined Tables
Figure EV2064 Schematic
AMCC Confidential Proprietary
EV2064 Quad Serial Backplane Device
Revision November 1999
EVALUATION BOARD
Figure EV2064 Power Ground Connections
AMCC Confidential Proprietary
EV2064 Quad Serial Backplane Device
Revision November 1999
EVALUATION BOARD
Table S2064 Evaluation Board Bill Materials
Quantity Component Value 0.022 HD1T HD11D HD12D HD13D S2064 SW-DIP7 Designators SMA1 SMA2 SMA3 SMA4 SMA5 SMA6 SMA7 SMA8 SMA9 SMA10 SMA11 SMA12 SMA13 SMA14 SMA15 SMA16 SMA17
Table S2064 Power Ground Bill Materials
Quantity Component Value Designators
BLM11A60 S2064_PWR TB-8
AMCC Confidential Proprietary
EV2064 Quad Serial Backplane Device
Revision November 1999
EVALUATION BOARD
Ordering Information
Prefix Evaluation Board Device 2064 Package TBGA
Prefix
XXXX
Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation. AMCC Confidential Proprietary

EV2064 Quad Serial Backplane Device EVALUATION BOARD S2

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