GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS GIGABIT ETHERNET TRANSC

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GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS GIGABIT ETHERNET TRANSC

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GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
EV2060 EV2060
EVALUATION BOARD OVERVIEW
This document describes operation usage S2060 evaluation boards. evaluation boards allow users become familiar with functionality S2060 Gigabit Ethernet Transceiver. Specifically, Error Rate (BER), jitter, basic performance tested using evaluation boards. This document provides complete board description, explains various test configurations, contains bill materials with corresponding schematic. This document should used conjunction with S2060 data sheet application note. Figure shows outline S2060A evaluation board.
Figure S2060 Evaluation Board
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REVISION
EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
EVALUATION BOARD DESCRIPTION
This section describes functionality connectors settings recommended S2060 evaluation boards. Brief descriptions connectors board, switch descriptions settings, power grounds, output levels, header settings, probes presented. letters "A", "B", "C", correspond specific parts evaluation board shown Figure described following section according their letter designation Figure
Connectors
connectors provided differential serial data input/output signals output clock. Additional connectors provided optional differential serial input clock, external reference clock optional external parallel input clock. Table gives description connectors.
Table Connectors
Connectors Receive Serial Data (RXP/RXN) Transmit Serial Data Output (TXP/TXN) Reference Clock (REFCLK) Description Differential inputs. Serial data inputs S2060 Differential outputs. Serial data output data. Reference clocking.
Switches
evaluation board equipped with switch control static control functions on-board devices. both arrays (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts logic high. Note that printed evaluation board. Table shows functional switch descriptions. Table shows switch settings corresponding tests described this document.
Table Switch Functional Description
Name RATEN
Description Rate Select. Active Low. This signal configures PLL's appropriate frequency. When inactive, operating range MHz. When active, operating range 1.25 GHz. Enable Wrap. Active High. When active, transmitter serial data outputs internally routed receiver serial data inputs. TXP/N static (logic this state. When inactive, RXP/N serial inputs selected (normal operation). Enable Comma Detect. Active High. When active, enables detection comma sync pattern word frame boundary data follow. When inactive, data treated unframed. Lock Reference Input. Active Low. When inactive open, receive will lock incoming data (normal operation). When active, receive forced lock input.
EWRAP
EN_CDET
-LCK_REF
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GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
Table Switch Settings Test Evaluation Configurations
(Not Labeled) TEST JITTER TEST RATEN EWRAP EN_CDET -LCK_REF
EV2060
Power/Ground
Three terminal outputs provided edge board Vee. S2060 specified
Table S2060 Power Ground Values
Terminal Post Terminal Post -1.3 LVPECL Output Termination -2.0 (GND)
Figure Single-Ended LVPECL Output Swing
-1.3 (internal bias point) Termination (VCC-2V)
TXP/N single-ended LVPECL output swing shown Figure bias point internally volts below rail. discussed both S2060 data sheet application note, pulldown resistors recommended positive negative outputs full output voltage swing. Test equipment inputs, however, typically provide loads. When interfacing test equipment input levels shifted -1.3 respectively order maintain full voltage swing with smaller load. Table summarizes voltage rail settings associated output loading.
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Probes (Headers)
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
RCB1, RCB0, COM_DET probe points. output levels RCB1, RCB0, COM_DET pins probed during testing. These pins must left unjumpered. RX[0:9], TX[0:9] either jumpered, utilized probe points, utilized active I/O. RX[0:9] TX[0:9] jumpered such that parallel output (RX[0:9] bridged directly parallel input (TX[0:9]). Selected RX[0:9] TX[0:9] pins also jumpered ground static input configuration. probe descriptions given Table input output signals typically routed from evaluation board through serial I/O. Providing evaluation board through parallel connectors would require user construct cable harness.
Table Evaluation Board Header Descriptions
Header RBC1 RBC0
Description Complementary Receive Byte Clocks. full rate mode, parallel receive data valid rising edges RBC0 RBC1. half rate, output data valid rising edge RBC1. Comma Detect. Active High. When EN_CDET active, COM_DET indicates that sync character present parallel bits RX[0:9]. Upon detection comma sync character (0011111xxx, positive polarity) this output data valid rising edge RBC1 remains high RBC1 clock period. When EN_CDET inactive, COM_DET held (logic Upon change state EN_CDET input, COM_DET output response will delayed maximum byte times. Receive Data Outputs. full rate output, parallel data this valid rising edges RBC0 RBC1. RX[0] first received. Transmit Data. Parallel data this clocked rising edge TBC. TX[0] transmitted first. Ground.
COM_DET
RX[0:9] TX[0:9]
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GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS SCHEMATIC/BILL MATERIALS
EV2060
Figures provide schematic representation evaluation boards. Table lists Bill Materials evaluation boards.
Figure Signal Connections
RBC0 REFCLKP
S2060
RBC1 COM-DET
EN_CDET
LCK_REF
EWRAP
RATEN
Figure Power Ground Connections
Power Terminal (1x2)
S2060
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EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
Table Evaluation Board Bill Materials
Part Number S2060 Evaluation Board S2060 J502-ND A5405-ND 151-8010 S1011-02-ND 277-1236-ND GRM39Y5Y104Z025AD GRM39COG101J50500 PCS3106TR-ND P50GCT-ND P100GCT-ND P150GCT-ND P1.0KGCT-ND BLM11A601SPTM00-03 Description board platform used house S2060 testing applications. Gigabit Ethernet Transceiver (edge mount) Switch Switch Prong Header Jumpers (Manufacturer: Mouser) Prong Male Header Terminal Power Connector Surface Mount (Allied part code: 2311242) Surface Mount Surface Mount Surface Mount Surface Mount Surface Mount Surface Mount Ferrite Bead Surface Mount Quantity
Part Number Postfix Prefix Prefix
Manufacturer Digikey Allied Allied
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GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS TEST CONFIGURATIONS
EV2060
This section deals with testing S2060, various test setups used ensure verify that S2060 meets required IEEE specifications. following will discuss BER, jitter, full operation test setups.
Testing
(Bit Error Rate) test provides evaluate number errors accumulated transmission data through S2060. This allows user keep track number bits that were unsuccessfully transmitted. number errors accumulated during transmission needs fall below 10-12 error ratio with input opening ~24% (IEEE 802.3z specification requirement) order S2060 pass test.
Figure Test Setup
Divider Board (divide
HP8133 PULSE GENERATOR
70841A PATTERN GENERATOR
DATA CLOCK DATA CLOCK
RBC1 RBC0 (Bridge) REFCLKP
S2060 EVAL BOARD
TEKTRONIX 11801A DIGITAL SAMPLING OSCILLOSCOPE
TRIGGER
RX[9:0] TX[9:0]
TRIGGER
S2060
70842A ERROR DETECTOR
DATA CLOCK
switch
(VISUAL OUTPUT VERIFICATION)
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EV2060
Test Setup
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
Figure shows S2060 evaluation board test setup. letters through following data path description correspond letter designations (A-F) shown Figure pattern generator outputs desired signal that user chosen. this test signal transmitted rate 1.25GHz. output pattern generator goes RXP/RXN inputs evaluation board. data then sent TXP/TXN terminals evaluation board, into error detector. error detector receives signal directly from pattern generator well from S2060 evaluation board. error detector compares signal coming from TXP/TXN terminals evaluation board signal from pattern generator. signal error free signals identical. pulse generator provides reference clocking S2060. oscilloscope used visual output verification. Table describes equipment list test
Table Test Setup Equipment List
Part Number S2060 Eval Board 70841A 70842A Tektronix 11801A 8133
Description
Quantity
Pattern Generator. Generates user input pattern send through device under test. Error Detector. Oscilloscope. Used visual output verification signals under testing. Pulse Generator/Divider. This device supplies reference clocking S2060 retimer chip. Cables
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Jitter Generation Testing
EV2060
Jitter generation measure variation position signal's logic transitions relative clock that extracted from signal.
Figure Jitter Generation Test Setup
70841A PATTERN GENERATOR
DATA DATA TRIGGER
S2060 EVAL BOARD
RBC1 RBC0 (Bridge) REFCLKP
Divider Board (divide
RX[9:0] TX[9:0]
S2060
switch
HP8133 PULSE GENERATOR
TEKTRONICS 11801A OSCILLOSCOPE
70842A ERROR DETECTOR
PROBE PROBE (VISUAL OUTPUT VERIFICATION) TRIGGER
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EV2060
Jitter Generation Test Setup
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
following description data path jitter tolerance test setup shown Figure letters through following data path description correspond letter designations (A-F) shown Figure /CLK output used input RXP/RXN inputs S2060 evaluation board. (DATA pattern generator used this test setup) output signal routed 70842A Error Detector. inverted output signal sent oscilloscope visual output verification. output pattern generator routed 70842A Error Detector comparison output. pulse generator output, divided provides reference clocking S2060. trigger input high speed oscilloscope taken from inverted clock output patter generator. This allows resulting data seen oscilloscope. Table describes equipment list jitter testing.
Table Jitter Test Setup Equipment List
Part Number S2060 Eval Board 70841A Tektronix 11801A 8133 8657B 3325B Pattern Generator. Oscilloscope. Used visual output verification signals under testing. Pulse Generator/Divider. This device supplies reference clocking S2060 retimer chip. Frequency Synthesizer. Squares sign wave look like clock signal. Synthesizer/Function Generator. This device adds jitter output pattern generator. Error Detector. Used calibrate clock setting test. During testing this device controls frequency which test performed. Attenuator. Cables. Description Quantity
70842A 3T-6
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Jitter Tolerance Testing
EV2060
Jitter tolerance amount jitter that device endure without incurring errors. More specifically measurement amplitude frequency dependent, random, deterministic jitter that causes clock recovery violate IEEE 802.3z specifications. There setups shown below jitter tolerance testing: asynchronous (Figure synchronous (Figure synchronous setup transmitter receiver running same reference clock. This emulates loopback configuration, where transmitter corresponding receiver same board. Asynchronous refers case where serial data stream recovered clock reference clock phase/frequency locked. Parts running real world asynchronously, since transmitting receiving parts different boards. S2060 devices required asynchronous test setup because possible supply separate reference clocks transmitter receiver within single part. Users wish test jitter tolerance either test setup; jitter tolerance values measured with setups will same. factory, AMCC performs tests with asynchronous setup order verify that locking recovered data clock addition testing jitter tolerance). Most users wish evaluate jitter tolerance elect test using synchronous setup because requires less equipment easier implement.
Figure Jitter Tolerance Test Setup (Asynchronous)
8657B FREQUENCY SYNTHESIZER
MAIN SIGNAL
HP8133 PULSE GENERATOR
MODULATION INPUT
3325B SYNTHESIZER/ FUNCTION GENERATOR
Random Jitter
RBC1 RBC0 REFCLKP MAIN SIGNAL
70841A PATTERN GENERATOR
MODULATION INPUT
RBC1 RBC0 REFCLKP
RX[9:0] TX[9:0]
S2060
switch
RX[9:0] TX[9:0]
DATA DATA TRIGGER
Deterministic Jitter
S2060
S2060 EVAL BOARD
switch
(stage
S2060 EVAL BOARD
(stage
70842A ERROR DETECTOR
DATA
TEKTRONICS 11801A OSCILLOSCOPE
TRIGGER (VISUAL OUTPUT VERIFICATION)
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EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
Jitter Tolerance Test Setup (Asynchronous)
following description data path jitter tolerance test setup shown Figure above. letters through following data path description correspond letter designations (A-F) shown Figure DATA /DATA outputs provide user determined output pattern. Random jitter added output signal. Deterministic jitter added signal, outputs received RXP/RXN inputs S2060 evaluation board. received serial data then deserialized output parallel RX[0:9] outputs. 10-bit parallel output signal (RX[0:9]) sent second S2060 evaluation board where received TX[0:9] parallel input. data then serialized sent TXP/TXN outputs S2060 evaluation board. output sent DATA error detector compared with transmitted data pattern. signals different, errors have occurred. Jitter increased 3325B function generator specified signal frequency (determined 70820A microwave transition analyzer) until errors seen. Results plotted microwave transition analyzer, signal frequency chosen jitter tolerance test repeats frequency. oscilloscope used visual output verification output. trigger output from pattern generator used trigger oscilloscope. pulse generator provides reference clocking S2060 (stage RBC1 output stage evaluation board provides reference clocking S2060 (stage
Figure Jitter Tolerance Test Setup (Synchronous)
8657B FREQUENCY SYNTHESIZER
MAIN SIGNAL
3325B SYNTHESIZER/ FUNCTION GENERATOR
Random Jitter
HP8133 PULSE GENERATOR
MODULATION INPUT
MAIN SIGNAL
RBC1 RBC0
RX[9:0] TX[9:0]
70841A PATTERN GENERATOR
MODULATION INPUT DATA DATA TRIGGER
REFCLKP (Bridge)
Deterministic Jitter
S2060
TEKTRONICS 11801A OSCILLOSCOPE
TRIGGER (VISUAL OUTPUT VERIFICATION)
switch
S2060 EVAL BOARD 70842A ERROR DETECTOR
DATA
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Jitter Tolerance Test Setup (Synchronous)
EV2060
following description data path jitter tolerance test setup shown Figure letters through following data path description correspond letter designations (A-F) shown Figure DATA /DATA outputs provide user determined output pattern. Random jitter then added output signal. Deterministic jitter added signal, outputs received RXP/RXN outputs S2060 evaluation board. received serial data then deserialized output parallel RX[0:9] outputs. 10-bit parallel output signal (RX[0:9]) bridged TX[0:9] parallel input header jumper covers. data then serialized S2060 sent TXP/TXN outputs S2060 evaluation board. output sent DATA error detector. signal from compared with original signal. signals different, errors have occurred. Jitter increased 3325B function generator specified signal frequency (determined 70820A microwave transition analyzer) until errors seen. results plotted microwave transition analyzer, signal frequency chosen jitter tolerance test repeats frequency. oscilloscope used visual output verification output. clock output from pattern generator sent trigger input oscilloscope data seen oscilloscope. pulse generator provides reference clocking S2060.
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EV2060
EVALUATION BOARD LAYOUT
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
This section provides layer layer design layout S2060 evaluation board. S2060B/D Figure S2060A/C
Figure S2060A/C
S2060B/D
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GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
Figure S2060A/C S2060B/D
EV2060
Figure S2060A/C
S2060B/D
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EV2060
GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS
S2060B/D
Figure S2060A/C
Figure S2060A/C
S2060B/D
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Ordering Information
PREFIX DEVICE PACKAGE
EV2060
Evaluation Board
2060
PQFP Commercial Temp Range PQFP Commercial Temp Range TQFP Commercial Temp Range, Loop filter pins option PQFP Industrial Temp Range
Prefix
XXXX Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 2000 Applied Micro Circuits Corporation
2000

GIGABIT ETHERNET TRANSCEIVER EVALUATION BOARDS GIGABIT ETHERNET TRANSC

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