EV3083/S3044 EV3083/S3044 S3083/S3044 Evaluation Board provides f
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SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD DESCRIPTION
EV3083/S3044 EV3083/S3044
S3083/S3044 Evaluation Board provides flexible platform verifying operation S3083/S3044 transceiver interface circuit. This document provides information board contents. should used conjunction with S3083 S3044 data sheets, which contains full technical details chips operation. Figure shows outline S3083/S3044 Evaluation Board, Figure shows block diagram S3083/S3044 Evaluation Board should connected test equipment Error Rate (BER) testing. this configuration S3083/S3044 configured with internal VCO, using 155.52 reference operating STS-48/STM-16 rate. Figure shows block diagram jitter generation testing S3083/S3044 Evaluation Board with jitter analyzer test equipment. Figure shows block diagram Line Loopback (LLEB) mode. Figure shows block diagram Diagnostic Loopback (DLEB) mode.
Figure Evaluation Board View
-3.3V -5.2V -3.3V
TSCLKN
TSCLKP
REFCLKN REFCLKP LSCLKP
TSDN
TSDP
RSCLKN LSCLKN S3083 LSDP RSDN LSDN RSDP S3044 RSCLKP
RSTB
LSCLKN
Note: Switch
LSCLKP
LLCLKN
LLCLKN
LLCLKP
LLCLKP
LSDN
LSDP
LLDN
LLDN
LLDP
LLDP
August 1999
EV3083/S3044
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure Schematic S3083 Evaluation Board
-3.3V Input Termination PINxx AVCC AVEE Inductor 0603, Ohms Ferrite Bead: BLM11A601SPTM00-03 AVCC 10uF 10uF -5.2V
EXTERNAL REFCLK 155MHz 2.4GHz 0.001uF -5.2V
HEL33 DIVIDE
0805 jumper: P0.0GCT-ND
AVCC
TSCLKN
TSCLKP
TSDP
TSDN
REFCLKN REFCLKP
LOCKDET PHINIT PHERR 155MCK PIN15 PIN14 PIN13 PIN12 PIN11 PIN10 PIN9 PIN8 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 PICLKP PICLKN PCLKP PCLKN
-5.2V
HEL33 DIVIDE
0.1uF/100pF
-5.2V
-5.2V 0.1uF/100pF
LSCLKP
S3083
LSCLKN
LSDP
LSDN
TESTEN
RSTB
LLCLKP LLCLKN
CAP1
DLEB
LLEB
CAP1
2.2uF
RSTB -3.3V
With 155MHz clock, position used switch closed. With 2.4GHz clock, position used switch open
LLDP LLDN
August 1999
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure Schematic S3044 Evaluation Board
-3.3V RSTB Diodes: 4002 9711
EV3083/S3044
-3.3V 10uF
LLCKKN LLCLKP
LSCLKN
LSCLKP
OVREF SEARCH RX155MCKP RX155MCKN POUT15 POUT14 POUT13 POUT12 POUT11 POUT10 POUT9 POUT8 POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 POCLKP POCLKN
RSTB DLEB LLEB SDPECL KILLRXCLK FRAMEN
S3044
RSCLKN
RSCLKP
RSDN RSDP
LSDN LSDP
LLDN LLDP
OUTPUT TERMINATION POUTxx
August 1999
EV3083/S3044
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure Power Ground Connections
S3083 Power Ground Connections
100pF
0.1µF
Ground (VCC)
100pF 0.1µF
VCO_GND
100pF 0.1µF
Capacitors 0603 Inductors 0603, Ohms Ferrite Bead: BLM11A601SPTM00-03
VCO_POW
100pF
0.1µF
S3044 Power Ground Connections
Pins tied
Ground (VCC)
0.1µF
100pF
100pF 0.1µF
100pF 0.1µF 100pF 0.1µF
0603 Capacitors
August 1999
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
EV3083/S3044
Figure depicts S3083/S3044 Evaluation board connected measurements, shows switch settings power supply requirements with test equipment that utilizes ohms ground termination.
Figure Test Setup (S3083/S3044 Setup Normal Operation Serial Serial Out)
803A
TRIG
ANRITSU MP1653A ERROR DETECTOR DATA
ANRITSU MP1650A PULSE GENERATOR CLK/
Pattern
DATA DATA
/DATA
OUT1
/CLK OUT1
TSCLKN
TSCLKP
REFCLKN
REFCLKP
TSDN
TSDP
-5.2V -3.3V
-3.3V
RSCLKN
LSCLKP DIVIDE INPUT LSDP S3083 S3044
RSCLKP
LSCLKN
RSDN
RSDP SWITCH SETTING: DS1: LLEB=1 DLEB=1 RSTB=1 TESTN= DS2: RSTB=1 DLEB=1 LLEB=1 SDPECL=1 KILLRXCLK=1 FRAME=0 OOF=1 NC=1
LSDN
LSCLKN
LSCLKP
LLCLKN
LLCLKN
LLCLKP
LLCLKP
LSDN
LLDP
LSDP
LLDN
LLDN
LLDP
August 1999
EV3083/S3044
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure depicts S3083/S3044 Evaluation board setup Jitter Generation measurements, shows switch settings power supply requirements with test equipment that utilizes ohms ground termination.
Figure Jitter Generation Test Setup (Setup Jitter Generation Measurement)
HP70820A INPUT
803A
TRIG OUT1
TRIG
708418 PATTERN GENERATOR 2.48832GHZ /CLK /DATA DATA
TSCLKN TSCLKP
-3.3V -5.2V -3.3V
REFCLKN
REFCLKP
TSDN
TSDP
RSCLKN
LSCLKP LSCLKN
INPUT
RSCLKP S3083 S3044 RSDN
LSDP
RSDP SWITCH SETTING: DS1: LLEB=1 DLEB=1 RSTB=1 TESTN= DS2: RSTB=1 DLEB=1 LLEB=1 SDPECL=1 KILLRXCLK=1 FRAME=0 OOF=1 NC=1
LSDN
LSCLKN
LLCLKN
LSCLKP
LLCLKN
LLCLKP
LLCLKP
LSDN
LLDN
LLDN
LSDP
LLDP
LLDP
August 1999
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
EV3083/S3044
Figure depicts S3083/S3044 Evaluation board setup Line Loop Back mode, shows switch settings power supply requirements with test equipment that utilizes ohms ground termination.
Figure Line Loopback (LLEB) Test Setup
ANRITSU MP1650A PULSE GENERATOR 803A TRIG ANRITSU MP1653A ERROR DETECTOR
Pattern
DATA
OUT2 DATA /DATA OUT1 /CLK OUT1
TSCLKN
TSCLKP
-5.2V -3.3V
REFCLKN
REFCLKP
TSDN
TSDP
-3.3V
RSCLKN
LSCLKP LSCLKN INPUT S3083 S3044
RSCLKP
RSDN
LSDP
RSDP SWITCH SETTING: DS1: LLEB=0 DLEB=1 RSTB=1 TESTN= DS2: RSTB=1 DLEB=1 LLEB=0 SDPECL=1 KILLRXCLK=1 FRAME=0 OOF=1 NC=1
LSDN
LSCLKN
LLCLKP
LLCLKN
LLCLKN
LLCLKP
LINE LOOP BACK
LSCLKP
LSDN
LLDN
LLDP
LSDP
LLDP
LLDN
August 1999
EV3083/S3044
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure depicts S3083/S3044 Evaluation board setup Diagnostic Loop Back mode, shows switch settings power supply requirements with test equipment that utilizes ohms ground termination.
Figure Diagnostic Loopback (DLEB) Test Setup
TRIG
ANRITSU MP1653A ERROR DETECTOR
DATA
Pattern
ANRITSU MP1650A PULSE GENERATOR
803A
OUT2 DATA /DATA OUT1 /CLK OUT1
TSCLKN
TSCLKP
REFCLKN REFCLKP
TSDN
TSDP
-3.3V -5.2V
-3.3V
RSCLKN
LSCLKP INPUT LSDP S3083 S3044
RSCLKP
LSCLKN
RSDN
RSDP SWITCH SETTING: DS1: LLEB=1 DLEB=0 RSTB=1 TESTN= DS2: RSTB=1 DLEB=0 LLEB=1 SDPECL=1 KILLRXCLK=1 FRAME=0 OOF=1 NC=1
LSDN
LSCLKN
LSCLKP
LLCLKN
LLCLKN
LLCLKP
LLCLKP
LSDN
LSDP
LLDN
LLDN
LLDP
LLDP
August 1999
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Table Power Connections Test Equipment Interface
Power Supply Nominal Input Voltage -3.3V Type Signal LVECL
EV3083/S3044
Output Termination Ohms
Figure LVPECL Signal Waveform
LVECL -0.8V -1.3V -1.8V -3.3V Termination Ohms
August 1999
EV3083/S3044 ELECTRICAL CONNECTIONS
Power Connections
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Terminal posts provided edge board VEE. S3083/S3044 Evaluation Board been configured with I/O. Figure demonstrates type input that S3083/S3044 Evaluation Board requires.
Connectors
connectors provided differential serial data input/output signals output clock. Additional connectors provided optional differential serial input clock, external reference clock optional external Parallel Input clock.
S3044 Connectors
Loopback Serial Clock [LSCLKP/N] LVPECL Differential inputs. Clock input from transmitter that synchronous with inputs. This clock used during local loopback testing perform framing deserialization functions. Loopback Serial Data [LSDP/N] LVPECL Differential inputs. Serial data stream connected transmitter loopback testing. These inputs clocked LSCLK inputs. Line Loopback Clock [LLCLKP/N] swing Differential outputs. buffered version RSCLK LSCLK input. Line Loopback Data [LLDP/N] swing Differential outputs. retimed version incoming data stream [RSD]. Receive Serial Data [RSDP/N] LVPECL Differential inputs. Serial data inputs S3044. Receive Serial Clock [RSCLKP/N] LVPECL Differential inputs. These inputs used supply clock input RSDP/N.
S3083 Connectors
Loopback Serial Clock [LSCLKP/N] swing Differential outputs. Serial clock signals connected companion S3044 device diagnostic loopback purposes. outputs updated falling edge LSCLK. Loopback Serial Data [LSDP/N] swing Differential outputs. Serial data stream connected companion S3044 device diagnostic loopback purposes. outputs updated falling edge LSCLK. Line Loopback Clock [LLCLKP/N] LVPECL Differential inputs. Inputs provided from companion S3044 device. Used implement line loopback function which receive serial data clock signals regenerated passed through S3083 transmitter. Line Loopback Data [LLDP/N] LVPECL Differential inputs. Inputs provided from companion S3044 device. Used implement line loopback function which receive serial data clock signals regenerated passed through S3083 transmitter. Transmit Serial Data [TSDP/N] Differential outputs. serial output data stream from transmitter section S3083. outputs drive ohms ground terminated instrument inputs. Transmit Clock Output [TSCLKP/N] Differential outputs. Transmit serial clock that used retime TSDP/N signal. outputs drive ohms ground terminated instrument inputs. This clock will 2.488MHz. Reference Clock [REFCLKP/N] LVPECL Differential inputs. These inputs must provided with differential level clock 155.52 MHz.
August 1999
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Parallel Header Terminals
EV3083/S3044
parallel input (PIN[15:0]) output (POUT[15:0]) data from S3083/S3044 transceiver available header array center Evaluation board. Ground columns also provided allow connection with 0.1" grid shielded ribbon cable parallel data sources data analyzers. User selectable jumpers also allow parallel output data (POUT[7:0]) output byte clock (POCLK) directly connected transmitter parallel data inputs (PIN[7:0]) parallel input clock (PICLK). Note: board must supplied with external reference REFCLKP/N proper operation.
S3044 Outputs
Parallel Clock [PCLK] LVPECL output. word rate output reference from transmitter PLL. This output used coordinate byte-wide transfers parallel data bus. Clock Output [155MCK] LVPECL output. 155.52 output derived from S3083 available header monitoring. Frame Pulse [FP] LVPECL output. Indicates frame boundaries incoming data stream (RSDP/N). Lock Detect [LOCKDET] LVTTL output. Indicates that locked onto incoming data stream. This signal when locked.
Switches
Evaluation Board equipped with switches, control static control functions on-board devices. both arrays (open "0") condition switch asserts logic assigned signal, (closed "1") condition asserts logic high. Figures show particular switch settings that needed particular test case. RSTB Pushbutton Switch This momentary contact switch controls master reset S3083/S3044. Please refer S3083/S3044 data sheet details specific control functions. Normal mode this master reset input normally high. Depressing switch connects this input logic zero resets S3083/S3044.
August 1999
EV3083/S3044
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figures through show layout S3083/S3044 Evaluation Board.
Figure
Figure
August 1999
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure
EV3083/S3044
Figure
August 1999
EV3083/S3044
Figure
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Figure
August 1999
SONET/SDH OC-48 TRANSCEIVER EVALUATION BOARD
Ordering Information
PREFIX DEVICE
EV3083/S3044
PACKAGE
Evaluation Board
3083 3044
PQFP/TEP PQFP/TEP
Prefix
XXXX Device
Package
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
August 1999
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