November 1997 Revised 2003 High-Speed CMOS Logic Octal-Bus Transc

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November 1997 Revised 2003 High-Speed CMOS Logic Octal-Bus Transc

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CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
November 1997 Revised 2003
High-Speed CMOS Logic Octal-Bus Transceiver, Three-State, Non-Inverting
Description
CD54HC245, CD54HCT245, CD74HC245, CD74HCT245 high-speed octal three-state bidirectional transceivers intended two-way asynchronous communication between data buses. They have high drive current outputs which enable high-speed operation while driving large capacitances. They provide power consumption standard CMOS circuits with speeds drive capabilities comparable that LSTTL circuits. CD54HC245, CD54HCT245, CD74HC245 CD74HCT245 allow data transmission from bus. logic level direction input (DIR) determines direction. output enable input (OE), when high, puts ports high-impedance state. HC/HCT245 similar operation HC/HCT640 HC/HCT643.
Features
Buffered Inputs
/Title (CD54 HC245 CD54 HCT24 CD74 HC245 CD74 HCT24 /Subject (High Speed
Three-State Outputs Line Driving Capability Typical Propagation Delay 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Ordering Information
PART NUMBER CD54HC245F3A CD54HCT245F3A CD74HC245E CD74HC245M TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC SOIC PDIP SOIC SOIC
Pinout
CD54HC245, CD54HCT245 (CERDIP) CD74HC245, CD74HCT245 (PDIP, SOIC) VIEW
CD74HC245M96 CD74HCT245E CD74HCT245M CD74HCT245M96
NOTE: When ordering, entire part number. suffix denotes tape reel.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 Functional Diagram
TRUTH TABLE CONTROL INPUTS OPERATION Data Data Isolation
High Level, Level, Irrelevant prevent excess currents High-Z (Isolation) modes terminals should terminated with resistors.
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. .±35mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, .±50mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (PDIP) Package (SOIC) Package. Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Three-State Leakage Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Three-State Leakage Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. -0.02 SYMBOL (mA) 25oC ±0.5 -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1 ±0.5
(Note
-2.1
Input Loading Table
INPUT UNIT LOADS
NOTE: Unit Load limit specified Electrical Table, e.g., 360µA 25oC.
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245
Switching Specifications
50pF, Input 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay Data Output
SYMBOL
TEST CONDITIONS
tPHL, tPLH
50pF 15pF 50pF 15pF 50pF 15pF 50pF
Output Disable Output
tPHL, tPLH
50pF
Output Enable Output
tPHL, tPLH
50pF
Output Transition Time
tTHL, tTLH
50pF
Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes TYPES Propagation Delay Data Output
50pF
tPHL, tPLH
50pF 15pF
Output Disable Output
tPHL, tPLH
50pF 15pF
Output Enable Output
tPHL, tPLH
50pF 15pF
Output Transition Time Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes NOTES:
tTHL, tTLH
50pF 50pF
used determine dynamic power consumption, channel. VCC2 (CPD where Input Frequency, Output Load Capacitance, Supply Voltage.
CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 Test Circuits Waveforms
INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V
tTHL
INVERTING OUTPUT
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
OUTPUT DISABLE
tPZL tPHZ tPZH OUTPUTS DISABLED OUTPUTS ENABLED
OUTPUT DISABLE
tPZL
tPLZ OUTPUT
tPLZ OUTPUT tPHZ OUTPUT HIGH OUTPUTS ENABLED
tPZH
1.3V
OUTPUT HIGH OUTPUTS ENABLED
1.3V OUTPUTS DISABLED OUTPUTS ENABLED
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM
OTHER INPUTS TIED HIGH OUTPUT DISABLE
WITH THREESTATE OUTPUT
OUTPUT 50pF
tPLZ tPZL tPHZ tPZH
NOTE: Open drain waveforms tPLZ tPZL same those three-state shown left. test circuit Output VCC, 50pF. FIGURE THREE-STATE PROPAGATION DELAY TEST CIRCUIT
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
0.775 (19,69) 0.745 (18,92)
0.775 (19,69) 0.745 (18,92)
0.920 (23,37) 0.850 (21,59)
1.060 (26,92) 0.940 (23,88)
0.260 (6,60) 0.240 (6,10)
MS-100 VARIATION
0.070 (1,78) 0.045 (1,14)
0.045 (1,14) 0.030 (0,76)
0.020 (0,51)
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
0.430 (10,92)
14/18 ONLY vendor option
4040049/E 12/2002
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width.
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI003E JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.020 (0,51) 0.014 (0,35)
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27)
0.010 (0,25)
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.291 (7,39) 0.010 (0,25)
Gage Plane 0.010 (0,25) 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) 0.012 (0,30) 0.004 (0,10) PINS 0.004 (0,10)
0.410 (10,41) 0.400 (10,16)
0.462 (11,73) 0.453 (11,51)
0.510 (12,95) 0.500 (12,70)
0.610 (15,49) 0.600 (15,24)
0.710 (18,03) 0.700 (17,78) 4040000/E 08/01
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0.006 (0,15). Falls within JEDEC MS-013
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements.
Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated

November 1997 Revised 2003 High-Speed CMOS Logic Octal-Bus Transc

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