(Digital Signal Processor System Memory) Analog Devices ADSP-2191 DSPs
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DSM2190F4V
(Digital Signal Processor System Memory) Analog Devices ADSP-2191 DSPs (3.3V Supply)
FEATURES SUMMARY Glueless Connection Easily memory, logic, External Port ADSP-2191 Dual Flash Memories independent Flash memory arrays storing code data. access arrays concurrently (read from while erasing writing other) 256K Main Flash memory divided into sectors (32KByte each) Ample storage booting code/data upon reset subsequent code swaps Large capacity data recording Secondary Flash memory divided into sectors KByte each). Multiple uses: Small sector size ideal small data sets, calibration configuration constants Store custom start-up code more sectors configure from external memory upon reset boot) Concatenate Secondary Flash with Main Flash total KBytes Each Flash sector write protected. Built-in programmable address decoding logic allows mapping individual Flash sectors address boundary Multifunction Pins Increase total system capability controlled software logic General purpose Over 3,000 Gates with macro cells peripheral glue logic keypads, control panel, displays, LCDs, other devices Eliminate PLDs external logic devices Create state machines, chip selects, simple shifters counters, clock dividers, delays Simple PSDsoft Expresssoftware.Free Operating Range VCC: 3.3V±10%; Temperature: -40oC +85oC
Figure Package
PQFP52
PLCC52
In-System Programming (ISP) with JTAG
Program entire chip 10-25 seconds with involvement Links with ADSP-2191 JTAG debug port Eliminate sockets pre-programmed memory logic devices allows efficient manufacturing product testing supporting Just-In-Time inventory low-cost FlashLINKcable with Content Security Programmable Security blocks access device programmers readers Zero-Power Technology 25µA standby current Packaging 52-pin PQFP 52-pin PLCC Flash Memory Speed, Endurance, Retention 100K cycles, year retention
September 2002
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TABLE CONTENTS Summary Description Architectural Overview Address/Data/Control Interface Main Flash Memory Secondary Flash Memory Programmable Logic (PLDs) Runtime Control Registers Memory Page Register Ports JTAG Port Power Management Security Sector Protection Assignments Typical connections Typical Memory Specifying Memory with PSDsoft Express. Runtime control register definition Detailed Operation Flash Memories Instruction Sequences Reading Flash Memory Programming Flash Memory Erasing Flash Memory. Flash Memory Sector Protect. Security Reset Flash Page Register PLDs Decode (DPLD).
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Complex (CPLD) Interface Ports Port Operating Modes Port Functionality Structure Port Functionality Structure Port Functionality Structure Power Management Power Management Chip Select Input (CSI, PD2) Power Reset, Warm Reset, Power-down Programming In-Circuit using JTAG AC/DC Parameters Table: Absolute Maximum Ratings Table: Operating Conditions Table: Characteristics Table: CPLD Combinatorial Timing Table: CPLD Macrocell Synchronous Clock Mode Timing Table: CPLD Macrocell Asynchronous Clock Mode Timing Table: Input Macrocell Timing Table: Read Timing Table: Write Timing Table: Flash Memory Program, Write Erase Times Table: Reset (Reset) Timing Table: Timing Package Mechanical Table: PLCC52 lead Plastic Leaded Chip Carrier, rectangular Table: Assignments PLCC52 Table: PQFP52 lead Plastic Quad Flatpack Table: Assignments PQFP52 Table: Ordering Information Scheme
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SUMMARY DESCRIPTION DSM2190F4 system memory device with Analog Devices ADSP-2191 DSP. means Digital signal processor System Memory. device brings In-System Programmable (ISP) Flash memory, parameter storage, programmable logic, additional systems. result simple flexible two-chip solution designs. devices provide flexibility Flash memory smart JTAG programming techniques both manufacturing field. On-chip integrated memory decode logic makes easy dual banks Flash memory ADSP-2191 variety ways bootloading, code execution, data recording, code swapping, parameter storage. JTAG reduces development time, simplifies manufacturing flow, lowers cost field upgrades. JTAG interface eliminates need sockets pre-programmed memory logic devices. manufacturing, products assembled with blank device soldered circuit board programmed manufacturing line seconds with involvement DSP. This allows efficient means test product manage inventory rapidly programming test code, then appli-
cation code determined inventory requirements (Just-In Time inventory). Additionally, JTAG reduces development time turning fast iterations code lab. Code updates field require disassembly product. FlashLINKJTAG programming cable costs plugs into notebook parallel port. addition Flash memory, devices programmable logic (PLD) configurable pins system. state each driven software logic. configuration programmable JTAG ISP, just like Flash memory. consists more than 3000 gates macro cell registers. Common uses include chip selects external devices, state-machines, simple shifters counters, keypad control panel interfaces, clock dividers, handshake delay, multiplexers, etc. This eliminates need small external PLDs logic devices. Configuration PLD, I/O, Flash memory mapping easily entered pointand-click environment using software development tool, PSDsoft ExpressTM. This software available charge from www.st.com/psm.
Figure System Block Diagram, Two-Chip Solution
DSM2190F4 SYSTEM MEMORY
FLAGS
ADDR DECODE LOGIC
TIMER/ CAPTURE SERIAL DEVICE SERIAL DEVICE SERIAL DEVICE UART DEVICE HOST
ADDRESS
BMS, MSx, IOMS
PRIMARY FLASH MEMORY 256K PORTS SECONDARY FLASH MEMORY I/O, PLD, CHIP SELECTS
ADSP-2191
MACROCELL CONTROL POWER MANAGEMENT CONTENT SECURITY
ANALOG DEVICES
DATA
PORTS
JTAG AREAS
I/O, PLD, CHIP
JTAG
JTAG DEBUG
AI04959B
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two-chip combination device ideal systems which have limitations size, levels, power consumption. memory logic "zero-power", meaning they automatically standby between memory accesses logic input changes, producing active standby current consumption, which ideal battery powered products. programmable security protects contents from unauthorized viewing copying. When set, security will block access programming devices (JTAG others) Flash memories configuration. only defeat security erase entire device, after which device blank used again. will always have access Flash memory contents through 8-bit data port even while security set.
Table DSM2190F4V Memory System DevicePart Number Main Flash Memory 256KBytes sectors 32KByte 256KBytes sectors 32KByte Secondary Flash Memory 32KBytes sectors 8KByte 32KBytes sectors 8KByte macro -cells macro -cells Ports Operating Package Speed Temp 52-pin PQFP 52-pin PLCC -40oC +85oC -40oC +85oC
DSM2190F4VV15T6 DSM2190F4VV15K6
3.3V ±10%
3.3V ±10%
Table Compatible Analog Devices
Part Number ADSP-2191M Operating Voltage, 2.5V Capability 3.6V
Figure PLCC ConnectionCNTL2 RESET CNTL1 CNTL0
Figure PQFP Connection
AD15 AD14 AD13 AD12 AD11 AD10
AD15 AD14 AD13 AD12 AD11 AD10
CNTLO
RESET
CNTL1
CNTL2
AI02858
AI02857
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ARCHITECTURAL OVERVIEW Major functional blocks shown Figure Address/Data/Control Interface These signals attach directly glueless connection. 8-bit data connection formed address lines decoded well memory strobes; BMS, IOMS, MSx. There many different ways DSM2190F4 configured used depending system requirements. convenient combine function signals into signal. Doing this allows core access memory runtime even after boot process complete using only signal. Combining consumes less pin(s) device. Analog Devices ADSP-2191 Hardware Reference Manual, Chapter Code Example: Runtime Access. Alternatively, signals also used decode sectors Main Flash Secondary flash memories. Main Flash Memory (256K Flash memory divided into eight equally-sized byte sectors that individually selectable through Decode PLD. Each Flash memory sector located address defined user with PSDsoft Express. code data easily placed flash memory using PSDsoft Express software development tool. Secondary Flash Memory 256K (32K Flash memory divided into eight equally-sized byte sectors that individually selectable through Decode PLD. Each Flash memory sector located address defined user with PSDsoft Express. code data also placed Secondary Flash memory using PSDsoft Express development tool. Secondary flash memory good storing data because small sectors. Additionally, software EEPROM emulation techniques used small data sets that change frequently byteby-byte basis. Secondary flash also used store custom start-up code applications that "boot" using DMA, instead start executing code from external memory upon reset. Storing code here keep entire Main Flash free initialization code clean software partitioning. only more byte sectors needed start-up code, remaining sectors Secondary Flash used data storage.
Secondary Flash also used extension Main Flash memory producing total 288K bytes Miscellaneous: Main Secondary Flash memories totally independent, allowing concurrent operation needed. read from memory while erasing programming other. erase Flash memories individual sectors entire Flash memory array erased time. Each sector either Flash memory individually write protected, blocking writes from (good boot start-up code protection). Flash memories automatically standby between read write accesses conserve power. Maximum access times include sector decoding time. Maximum erase cycles 100K data retention years minimum. Flash memory, well entire device programmed with JTAG interface with involvement. Programmable Logic (PLDs) family contains PLDS that optionally Turbo Non-Turbo mode. PLDs operate faster (less propagation delay) while Turbo mode consume more power than NonTurbo mode. Non-Turbo mode allows PLDs automatically standby when inputs change conserve power. Turbo mode setting controlled runtime software. Decode (DPLD). This programmable logic used select eight individual Main Flash memory segments, four individual Secondary Flash memory segments, group control registers within device. DPLD also optionally drive external chip select signals Port pins. DPLD input signals include: address control signals, Page Register outputs, Port Pins, CPLD logic feedback. Complex (CPLD). This programmable logic used create both combinatorial sequential general purpose logic. CPLD contains Output Macrocells (OMCs) Input Macrocells (IMCs). Macrocell registers unique that that have direct connection data allowing them loaded read directly runtime. This direct access good making small peripheral devices (shifters, counters, state machines, etc.) that accessed directly with little overhead. DPLD inputs include address control signals, Page Register outputs, Port Pins, CPLD feedback.
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Figure Block Diagram
INTERNAL ADDR, DATA, CONTROL LINKED SECURITY LOCK PAGE
MAIN FLASH MEMORY
DSM2190F4 SYSTEM MEMORY
DATA
ADDR AD10 AD11 AD12 AD13 AD14 AD15
DECODE (DPLD)
FS0-7
SEGMENTS, KBytes TOTAL FLASH MEMORY
csboot3
CSBOOT0-3
csboot0
SEGMENTS, KBytes TOTAL RUNTIME CONTROL CSIOP REGISTER FILE POWER MANAGEMENT EXTERNAL CHIP SELECTS COMPLEX (CPLD) ARRAY
CSIOP INPUT
PORT EXTERNAL CHIP SELECTS, ESC0-2
Output
Macrocells
ALLOCATOR
CONTROL CNTL0 CNTL1 CNTL2 RST\ FEEDBACK NODE FEEDBACK
PORT
Input Macrocell
JTAG-ISP AREAS CHIP
AI04960B
OMCs: general structure CPLD similar nature 22V10 device with familiar sum-of-products (AND-OR) construct. True compliment versions input signals available large array. array outputs feed into multiple product-term gate within each product-terms each OMC). Logic output gate passed combinatorial logic combined with flipflop within each realize sequential logic. OMCs used buried nodes with feedback array output routed pins Port PortC. IMCs: Inputs from pins Port Port routed IMCs conditioning (clocking latching) they enter chip, which good sampling debouncing inputs. Alternatively, IMCs pass Port input signals directly inputs without clocking latching. read IMCs time.
Runtime Control Registers block bytes decoded inside device control status registers. registers used block locations control output state pins, read pins, control power management, read/write macrocells, other functions runtime. Table description. base address these locations referred this data sheet csiop (Chip Select Port). Individual registers within this block accessed with offset from base address. accesses csiop registers using memory with IOMS strobe. csiop registers accessed bytes. Memory Page Register This 8-bit register loaded read runtime csiop registers. outputs feed directly into PLDs. page register used special memory mapping requirements also general logic.
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Ports individually configurable pins distributed over three ports (Ports Each individually configured different functions such standard ports basis. (MCU means that each pin, output state controlled input value read runtime using csiop registers like would do.) Port hosts JTAG signals. Since JTAGISP does occur frequently during life product, those Port pins under-utilized. applications that need every pin, JTAG signals multiplexed with general signals them when performing ISP. section titled "Programming In-Circuit using JTAG ISP" page muxing JTAG pins Port Application Note AN1153. static configuration Port pins defined with PSDsoft Expresssoftware development tool. dynamic action Ports pins controlled runtime software. JTAG Port In-System Programming (ISP) performed through JTAG signals Port This serial interface allows programming entire device subsections (that only Flash memory PLDs) without participation DSP. blank device soldered circuit board completely programmed seconds. basic JTAG signals; TMS, TCK, TDI, form IEEE-1149.1 interface. device does implement IEEE-1149.1 Boundary Scan functions. uses JTAG interface only. However, device reside standard JTAG chain with other JTAG devices (including ADSP-2191) will remain BYPASS mode while other devices perform Boundary Scan. programming time reduced much using more signals Port TSTAT TERR addition TMS, TCK, TDO. FlashLINK JTAG programming cable available from STMicroelectronics $59USD PSDsoft Express software available charge from www.st.com/psm. That that needed program device using parallel port note-book. section titled "Programming In-Circuit using JTAG ISP" page Power Management bits csiop control registers that configured run-time reduce power consumption CPLD. Turbo PMMR0 register logic CPLD will Non-Turbo mode, meaning will latch outputs sleep until next transition inputs. There slight penalty performance (longer propagation delay), significant power savings realized. Additionally, bits csiop registers selectively block signals from entering CPLD which reduces power consumption. section titled "Power Management" page Security Sector Protection programmable security protects contents from unauthorized viewing copying. When set, security will block access programming devices (JTAG others) Flash memory configuration. only defeat security erase entire device, after which device blank used again. Additionally, contents each individual Flash memory sector write protected (sector protection) configuration with PSDsoft ExpressTM. This typically used protect boot code from being corrupted inadvertent writes Flash memory from DSP. Assignments assignment shown 52-pin PLCC package Figure 52-pin PQFP package Figure
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Table Description
Name ADIO0-15 CNTL0 CNTL1 CNTL2 Reset PA0-7 Type Sixteen address inputs from DSP. Active write strobe input (WR) from Active read strobe input (RD) from DSP. Active Byte Memory Select (BMS) signal from DSP. Active reset input from system. Resets Ports, Page Register contents, other configuration registers. Must logic Power-up. Eight data signals connected pins D15. Eight configurable Port signals with following functions: write read pins directly runtime with csiop registers. CPLD Output Macrocell (McellAB0-7 McellBC0-7) outputs. Inputs PLDs (Input Macrocells). Note: Each four Port signals PB0-PB3 configured run-time either standard CMOS high slew rate. Each four Port signals PB3-PB7 configured run-time either standard CMOS Open Drain Outputs. Eight configurable Port signals with following functions: write read pins directly runtime with csiop registers. CPLD Output Macrocell (McellBC0-7) output. Input PLDs (Input Macrocells). Pins PC0, PC1, PC5, optionally form JTAG IEEE-1149.1 serial interface signals TMS, TCK, TDI, respectively. Pins optionally form enhanced JTAG signals TSTAT TERR respectively. Reduces programming time when used addition standard four JTAG signals: TDI, TDO, TMS, TCK. optionally configured Ready/Busy output indicate Flash memory programming status during parallel programming. polled used interrupt indicate when Flash memory byte programming erase operations complete. Note Port input input pin) connected IOMS output. Figure Note When used general I/O, each eight Port signals configured run-time either standard CMOS Open Drain Outputs. Note JTAG pins multiplexed with other functions. Three configurable Port signals with following functions: write read pins directly runtime with csiop registers. Input PLDs associated Input Macrocells, routes directly into PLDs). CPLD output (External Chip Select). Does consume Output Macrocells. optionally configured CLKIN, common clock input PLD. optionally configured CSI, active Chip Select Input select Flash memory. Flash memory disabled conserve more power when logic high. connect ADSP-218X PWDACK output signal. Note Port input pin) connected output. Figure Note Port input pin) connected output. Figure Note Port input pin) connected output. Figure Supply Voltage Ground pins Description
PB0-7
PC0-7
PD0-2
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TYPICAL CONNECTIONS Figure shows typical connection scheme. Many connection possibilities exist since many pins multipurpose. This scheme illustrates combined function signal (functions MSx), many pins. also illustrates chain devices together JTAG bus. JTAG connector definition depends development production environment requirements. specially defined connector devised combine signals FlashLINK Analog Devices emulator. Alternatively, separate JTAG connectors used, matching pinout FlashLINK other matching emulator pinout. Keep mind that signals BMS, IOMS, MSx, ADDR16, ADDR17, ADDR18 connected that input. pins Port Port more capable (more functions) than Port pins. recommended Port pins primarily decode inputs first, leaving pins Port Port available general
logic. Figure illustrates common make connections. Following connection options consider: Port JTAG: Figure shows four JTAG signals (TMS, TCK, TDI, TDO) connected DSM. Alternatively, using six-pin JTAG (two more signals, TSTAT TERR) reduce time much compared four-pin JTAG. Other JTAG options include multiplexing JTAG pins with general (see "Programming In-Circuit using JTAG ISP" page Application Note AN1153), using JTAG all. JTAG used, device programmed conventional programmer before installed circuit board. Using JTAG makes more available. Pins PD2. 288K address locations need decoded DSM, then ADDR18 needed. this case, IOMS signal connected PD2, freeing general usage.
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BUS_REQUEST BUS_GRANT GRANT_HUNG
_BGH
ADSP-2191
DSM2190F4
BYPASS CLOCK
BYPASS CLKOUT CLKIN XTAL
_BMS _IOMS _MSx CNTL0 CNTL1 CNTL2 WRITE READ BOOT SELECT SELECT
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
Figure Typical Connection
CLOCK XTAL
optional TSTAT optional _TERR
PF10 PF11 PF12 PF13 PF14 PF15 SPORT0 SERIAL SPORT1 SERIAL _RESET
_RESET ADDR16 ADDR17 ADDR18
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
SERIAL DEVICE SPORT1 SERIAL _RESET
RESET
SERIAL DEVICE RxD,
UART DEVICE TMR2-0
_TRST _EMU BMODE0 BMODE1 OPMODE JTAG JTAG JTAG JTAG
HOST PORT
JTAG _TRST EMULATOR STATUS
JTAG_TRST EMULATOR STATUS
DSM2190F4
AI04961B
JTAG CONNECTOR
JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TMS
TIMER/ CAPTURE
JTAG CONNECTOR
SERIAL DEVICE
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15
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TYPICAL MEMORY There many different ways place map) addresses memory depending system requirements. DPLD allows complete mapping flexibility. Figure shows possible system memory map. this case, will bootload (via DMA) contents Main Flash memory upon reset. Secondary Flash memory used parameter storage additional code storage. configured combined into signal, allowing access both Flash memories runtime (after boot). execute code
directly from well erase write code data Flash. nomenclature fs0.fs7 designators individual sectors Main Flash memory, bytes each. csboot0.csboot3 designators individual Secondary Flash memory segments, bytes each. csiop designates control register block. designer easily specify memory mapping point-and-click software environment using PSDsoft ExpressTM.
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Figure Typical System Memory
Boot Memory Space (BMS)
56000-57FFF 54000-55FFF 52000-53FFF 50000-51FFF 4FFFF
bytes Main Flash csboot, csboot, csboot, csboot, Flash Flash Flash Flash
Memory Space (IOMS)
csiop
CONTROL REGS
02000-020FF
48000 47FFF
bytes Main Flash
40000 3FFFF
bytes Main Flash
38000 37FFF
bytes Main Flash
30000 2FFFF
bytes Main Flash
28000 27FFF
bytes Main Flash
20000 1FFFF
bytes Main Flash
18000 17FFF
bytes Main Flash
10000
AI04962
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SPECIFYING MEMORY WITH PSDSOFT EXPRESSThe memory shown Figure easily statements ABEL language. Figure shows implemented using PSDsoft Expressin pointthe resulting equations generated PSDsoft Exand-click environment. PSDsoft Expresswill pressTM. generate Hardware Definition Language (HDL) Figure Statements Generated from PSDsoft Express Implement Memory csiop ((address ^h2000) (address ^h20FF) (!_ioms)); ((address ^h10000) (address ^h17FFF) (!_bms)); ((address ^h18000) (address ^h1FFFF) (!_bms)); ((address ^h20000) (address ^h27FFF) (!_bms)); ((address ^h28000) (address ^h2FFFF) (!_bms)); ((address ^h30000) (address ^h37FFF) (!_bms)); ((address ^h38000) (address ^h3FFFF) (!_bms)); ((address ^h40000) (address ^h47FFF) (!_bms)); ((address ^h48000) (address ^h4FFFF) (!_bms)); csboot0 ((address ^h50000) (address ^h51FFF) (!_bms)); csboot1 ((address ^h52000) (address ^h53FFF) (!_bms)); csboot2 ((address ^h54000) (address ^h55FFF) (!_bms)); csboot3 ((address ^h56000) (address ^h57FFF) (!_bms)); Specifying these equations using PSDsoft Expressis very simple. Figure shows specify equation Byte Flash memory segment, fs2. Notice qualified with Figure PSDsoft ExpressMemory Mapping signals BMS. This specification process repeated other Flash memory segments, csiop register block, external chip select signals that needed (ADC, etc.).
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RUNTIME CONTROL REGISTER DEFINITION There addresses decoded inside device control status information. these locations contain registers that access runtime. base address this block locations referred this manual csiop (Chip Select Port). Table lists registers their offsets hexadecimal) from csiop base address needed access individual control status registers. will access these registers memory space using
IOMS strobe. These registers accesses bytes, should ignore upper byte 16-bit access. Note1: csiop registers cleared logic reset. Note2: write unused locations within csiop block registers. They should remain logic zero.
Table CSIOP Registers their Offsets hexadecimal)
Register Name Data Data Port Port Port Other Description MCUI/O input mode. Read obtain current logic level Port pins. writes. output mode. Write logic level Port pins. Read check status. mode. Configures Port input output. Write direction Port pins. Logic out, Logic Read check status. Write configure Port pins either standard CMOS Open Drain some pins, while selecting high slew rate other pins. Read check status. Read obtain state IMCs. writes. Read obtain status output enable logic each Port driver. writes. Read logic state output bank Write load registers bank Read logic state output bank Write load registers bank Write mask loading OMCs bank logic position will block reads/writes corresponding OMC. logic will pass value. Read check status. Write mask loading OMCs bank logic position will block reads/writes corresponding OMC. logic will pass value. Read check status. Read determine Main Flash Sector Protection Setting. writes. Read determine devices Security active. Logic device secured. Also read determine Secondary Flash Protection Setting status. Writes. Write enable JTAG Pins (optional feature). Read check status. Power Management Register Write read. Power Management Register Write read. Memory Page Register. Write read.
Direction
Drive Select Input Macrocells Enable Output Macrocells Output Macrocells
Mask Macrocells
Mask Macrocells
Main Flash Sector Protection Security Secondary Flash Sector Protection JTAG Enable PMMR0 PMMR2 Page
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DETAILED OPERATION Figure shows major functional areas device: Flash Memories
PLDs (DPLD, CPLD, Page Register) Interface (Address, Data, Control) Ports Runtime Control Registers JTAG Interface
following describes these functions more detail. Flash Memories Main Flash memory array divided into eight equal byte sectors. Secondary Flash memory array divided into four equal byte sectors. Each sector selected DPLD separately protected from program erase cycles. This configuration specified using PSDsoft Express Memory Sector Select Signals. DPLD generates Select signals internal memory blocks (see Figure 14). Each twelve sectors Flash memories select signal (FS0-FS7, CSBOOT0-CSBOOT3) which contains three product terms. Having three product terms each select signal allows given sector mapped into multiple areas system memory needed. Ready/Busy (PC3). This signal used output Ready/ Busy status device. output Ready/Busy (Busy) when either Flash memory array being written, when either Flash memory array being erased. output (Ready) when Write Erase cycle
progress. This signal polled used interrupt indicate when erase program cycle complete. Memory Operation. Flash memories accessed through Address, Data, Control Interface. DSPs MCUs cannot write Flash memory would SRAM device. Flash memory must first "unlocked" with special sequence byte write operations invoke internal algorithm, then single data byte written Flash memory array, then programming status checked byte read operation checking Ready/ Busy (PC3). Table lists special instruction sequences program (write) data Flash memory arrays, erase arrays, check different types status from arrays. These instruction sequences different combinations individual byte write byte read operations. IMPORTANT: read execute code from same Flash memory array which directing instruction sequence. more simply stated, read code same Flash array that writing erasing. Instead, must execute code from alternate memory (like internal SRAM different Flash array) while sending instructions given Flash array. Since Flash memory arrays inside device completely independent, read code from array while sending instructions other. After Flash memory array programmed (written) will "Read Array" mode, then read from Flash memory just would from 8-bit SRAM device.
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Table Instruction Sequences1,2,3,4
Instruction Sequence Read Memory Contents5 Read Flash Identifier (Main Flash only)6,7 Read Memory Sector Protection Status6,7,8 Program Flash Byte Flash Bulk Erase9 Flash Sector Erase10 Suspend Sector Erase11 Cycle Read byte from valid Flash memory addr Write XX555h Write XXAAAh Write XX555h Read identifier with addr lines A6,A1,A0 0,0,1 Read identifier with addr lines A6,A1,A0 0,1,0 Write (program) data addr Write XX555h Write XX555h Write XXAAAh Write XXAAAh Write XX555h Write another Sector Write another Sector Cycle Cycle Cycle Cycle Cycle Cycle
Write XX555h
Write XXAAAh
Write XX555h
Write XX555h Write XX555h Write XX555h Write address that activates Write addr that activates Write address that activates
Write XXAAAh Write XXAAAh Write XXAAAh
Write XX555h Write XX555h Write XX555h
Resume Sector Erase12
Reset Flash
Note: values hexadecimal, Don't Care desired internal Flash memory sector select signal (FS0 CSBOOT0 CSBOOT3) must active each write read cycle. Only these sector select signals will active given time depending address presented memory mapping defined PSDsoft Express. CSBOOT0-CSBOOT3 active high logic internally. addresses through Don't Care during instruction sequence decoding. Only address bits A11-A0 used during Flash memory instruction sequence decoding cycles. individual sector select signal (FS0 CSBOOT0CSBOOT3) which active during instruction sequences determines complete address. write operations, addresses latched falling edge Write Strobe (WR, CNTL0), Data latched rising edge Write Strobe (WR, CNTL0) Unlock Instruction cycles required when device Read Array mode. Operation like reading device. Reset Flash instruction required return normal Read Array mode Error Flag (DQ5) goes High, after reading Flash Identifier after reading Sector Protection Status. cannot invoke this instruction sequence while executing code from same Flash memory that which instruction sequence intended. must fetch, example, code from SRAM when reading Flash memory Identifier Sector Protection Status. data unprotected sector, protected sector. fourth cycle, Sector Select active, (A1,A0)=(1,0) Directing this command individual active Flash memory segment (FS0 FS7) will invoke bulk erase eight Flash memory sectors. writes command sequence initial segment erased, then writes byte additional sectors erased. byte must addressed other Flash memory segments (FS0 FS7) each additional segment (write address within desired sector). more than 80uS elapse between subsequent additional sector erase commands. system perform Read Program cycles non-erasing sectors, read Flash read Sector Protect Status, when Suspend Sector Erase mode. Suspend Sector Erase instruction sequence valid only during Sector Erase cycle. Resume Sector Erase instruction sequence valid only during Suspend Sector Erase mode.
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Instruction Sequences instruction sequence consists sequence specific write read operations. Each byte written device received sequentially decoded executed standard write operation memory array. instruction sequence executed when correct number bytes properly received time between consecutive bytes shorter than time-out period. Some instruction sequences structured include read operations after initial write operations. instruction sequence must followed exactly. invalid combination instruction bytes time-out between consecutive bytes while addressing Flash memory resets device logic into Read Array mode (Flash memory read like device). device supports instruction sequences summarized Table Flash memory: Erase memory chip sector
Suspend resume sector erase Program Byte Reset Read Array mode Read primary Flash Identifier value Read Sector Protection Statu
These instruction sequences detailed Table efficient decoding instruction sequences, first bytes instruction sequence coded cycles followed instruction byte confirmation byte. coded cycles consist writing data address XX555h during first cycle data address XXAAAh during second cycle. Address signals A18-A12 Don't Care during instruction sequence Write cycles. However, appropriate internal Sector Select FS0-FS7 CSBOOT0-CSBOOT3) must selected internally (active, which logic
Reading Flash Memory Under typical conditions, read Flash memory using read operations just would device. Alternately, read operations obtain status information about Program Erase cycle that currently progress. Lastly, instruction sequences read special data from these memory blocks. following sections describe these read instruction sequences. Read Memory Contents. Flash memory placed Read Array mode after Power-up, chip reset, Reset Flash memory instruction sequence (see Table read memory contents Flash memory using read operations time read operation part instruction sequence. Read Main Flash Identifier. Main Flash memory identifier read with instruction sequence composed operations: specific write operations read operation (see Table During read operation, address bits must 0,0,1, respectively, appropriate internal Sector Select FS0-FS7) must active. identifier 0xE7. Applicable Secondary Flash. Read Memory Sector Protection Status. Flash memory Sector Protection Status read with instruction sequence composed operations: specific write operations read operation (see Table During read operation, address bits must 0,1,0, respectively, while internal Sector Select (FS0-FS7 CSBOOT0-CSBOOT3) designates Flash memory sector whose protection verified. read operation produces Flash memory sector protected, sector protected. sector protection status also read accessing Flash memory Protection registers csiop space. section entitled "Flash Memory Sector Protect" register definitions.
Table Status Definition
Functional Block FS0-FS7, CSBOOT0-CSBOOT3 Active (the desired segment selected) Data Polling Toggle Flag Error Flag Erase Timeout
Flash Memory
Note: guaranteed value, read either DQ7-DQ0 represent Data bits, D7-D0.
Reading Erase/Program Status Bits. device provides several status bits used confirm completion Erase
Program cycle Flash memory. These status bits minimize time that spends performing these tasks defined Table status bits read many times needed.
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Flash memory, perform read operation obtain these status bits while Erase Program instruction sequence being executed embedded algorithm. section entitled "Programming Flash Memory", page details. Data Polling Flag (DQ7). When erasing programming Flash memory, Data Polling Flag (DQ7) outputs complement being entered programming/writing Data Polling Flag (DQ7) bit. Once Program instruction sequence write operation completed, true logic value read Data Polling Flag (DQ7) read operation). Flash memory instruction features. Data Polling effective after fourth Write pulse (for Program instruction sequence) after sixth Write pulse (for Erase instruction sequence). must performed address being programmed address within Flash memory sector being erased.
byte programmed belongs protected Flash memory sector, instruction sequence ignored. Flash memory sectors selected erasure protected, Toggle Flag (DQ6) toggles about then returns previous addressed byte.
During Erase cycle, Data Polling Flag (DQ7) outputs After completion cycle, Data Polling Flag (DQ7) outputs last programmed after erasing). byte programmed protected Flash memory sector, instruction sequence ignored. Flash memory sectors erased protected, Data Polling Flag (DQ7) reset about then returns previous addressed byte. erasure performed.
Toggle Flag (DQ6). device offers another determining when Flash memory Program cycle completed. During internal write operation when Sector Select FS0-FS7 CSBOOT0-CSBOOT3) true, Toggle Flag (DQ6) toggles from subsequent attempts read byte memory. When internal cycle complete, toggling stops data read Data D0-7 addressed memory byte. device accessible read write operation. cycle finished when successive reads yield same output data. Flash memory specific features: Toggle Flag (DQ6) effective after fourth write operation (for Program instruction sequence) after sixth write operation (for Erase instruction sequence).
Error Flag (DQ5). During normal Program Erase cycle, Error Flag (DQ5) This when there failure during Flash memory Byte Program, Sector Erase, Bulk Erase cycle. case Flash memory programming, Error Flag (DQ5) indicates attempt program Flash memory from programmed state, erased state, which valid. Error Flag (DQ5) also indicate Time-out condition while attempting program byte. case error Flash memory Sector Erase Byte Program cycle, Flash memory sector which error occurred which programmed byte belongs must longer used. Other Flash memory sectors still used. Error Flag (DQ5) reset after Reset Flash instruction sequence. Erase Time-out Flag (DQ3). Erase Timeout Flag (DQ3) reflects time-out period allowed between consecutive Sector Erase instruction sequence bytes. Erase Time-out Flag (DQ3) reset after Sector Erase cycle time period unless additional Sector Erase instruction sequence decoded. After this time period, when additional Sector Erase instruction sequence decoded, Erase Time-out Flag (DQ3) Programming Flash Memory When byte Flash memory programmed, individual bits programmed logic cannot program Flash memory logic once been programmed logic must erased logic programmed logic That means Flash memory must erased prior being programmed. byte Flash memory erased (FFh). erase entire Flash memory array once individual sector-by-sector, byte-by-byte. However, program Flash memory byte-by-byte. Flash memory requires send instruction sequence program byte erase sectors (see Table Once issues Flash memory Program Erase instruction sequence, must check status bits completion. embedded algorithms that invoked inside device provide several ways give status DSP. Status
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checked using three methods: Data Polling, Data Toggle, Ready/Busy (pin PC3). Data Polling. Polling Data Polling Flag (DQ7) method checking whether Program Erase cycle progress completed. Figure shows Data Polling algorithm. When issues Program instruction sequence, embedded algorithm within device begins. then reads location byte programmed Flash memory check status. Data Polling Flag (DQ7) this location becomes compliment original data byte programmed. continues poll this location, comparing Data Polling Flag (DQ7) monitoring Error Flag (DQ5) bit. When Data Polling Flag (DQ7) matches bit7 original data, Error Flag (DQ5) remains then embedded algorithm complete. Error Flag (DQ5) should test Data Polling Flag (DQ7) again since Data Polling Flag (DQ7) have changed simultaneously with Error Flag (DQ5) (see Figure 10). Error Flag (DQ5) either internal time-out occurred while embedded algorithm attempted program byte attempted program that erased (not erased logic suggested with Flash memories) read location again after embedded programming algorithm completed, compare byte that written Flash memory with byte that intended written. When using Data Polling method during Erase cycle, Figure still applies. However, Data Polling Flag (DQ7) until Erase cycle complete. Error Flag (DQ5) indicates time-out condition Erase cycle, indicates error. read location within sector being erased Data Polling Flag (DQ7) Error Flag (DQ5) bit. PSDsoft Express generates ANSI code functions which implement these Data Polling algorithms. Figure Data Polling Flowchart
START
READ VALID ADDRESS
DATA
READ
DATA FAIL
PASS
AI01369B
Data Toggle. Checking Toggle Flag (DQ6) method determining whether Program Erase cycle progress completed. Figure shows Data Toggle algorithm. When issues Program instruction sequence, embedded algorithm within device begins. then reads location byte programmed Flash memory check status. Toggle Flag (DQ6) this location toggles each time reads this location until embedded algorithm complete. continues read this location, checking Toggle Flag (DQ6) monitoring Error Flag (DQ5) bit. When Toggle Flag (DQ6) stops toggling (two consecutive reads yield same value), Error Flag (DQ5) remains then embedded algorithm complete. Error Flag (DQ5) should test Toggle Flag (DQ6) again, since Toggle Flag (DQ6) have changed simultaneously with Error Flag (DQ5) (see Figure 11).
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Figure Data Toggle Flowchart
START
READ
TOGGLE
READ
TOGGLE FAIL
PASS
AI01370B
Error Flag (DQ5) either internal time-out occurred while embedded algorithm attempted program byte, attempted program that erased (not erased logic suggested with Flash memories) read location again after embedded programming algorithm completed, compare byte that written Flash memory with byte that intended written. When using Data Toggle method after Erase cycle, Figure still applies. Toggle Flag (DQ6) toggles until Erase cycle complete. Error Flag (DQ5) indicates time-out condition Erase cycle, indicates error. read location within sector being erased Toggle Flag (DQ6) Error Flag (DQ5) bit. PSDsoft Express generates ANSI code functions which implement these Data Toggling algorithms. Erasing Flash Memory Flash Bulk Erase. Flash Bulk Erase instruction sequence uses write operations followed read operation status register, described Table byte Bulk Erase instruction sequence wrong, Bulk Erase instruction sequence aborts device
Read Flash memory status. Bulk Erase command addresses individual valid Flash memory segment (FS0-FS7 CSBOOT0-CSBOOT3) entire array (all segments array) will erased. During Bulk Erase, memory status checked reading Error Flag (DQ5) bit, Toggle Flag (DQ6) bit, Data Polling Flag (DQ7) bit, detailed section entitled "Programming Flash Memory", page Error Flag (DQ5) returns there been Erase Failure (maximum number Erase cycles have been executed). necessary program memory with because device automatically does this before erasing 0FFh. During execution Bulk Erase instruction sequence, Flash memory does accept instruction sequences. address provided with Flash Bulk Erase command sequence (Table select eight internal Flash memory Sector Select signals four signals CSBOOT0-CSBOOT3. erase that entire Flash memory array will occur even though command sent just Flash memory sector. Flash Sector Erase. Sector Erase instruction sequence uses write operations, described Table Additional Flash Sector Erase codes Flash memory sector addresses written subsequently erase other Flash memory sectors parallel, without further coded cycles, additional bytes transmitted shorter time than time-out period about input Sector Erase code restarts timeout period. status internal timer monitored through level Erase Time-out Flag (DQ3) bit. Erase Time-out Flag (DQ3) Sector Erase instruction sequence been received time-out period counting. Erase Time-out Flag (DQ3) time-out period expired device busy erasing Flash memory sector(s). Before during Erase time-out, instruction sequence other than Suspend Sector Erase Resume Sector Erase instruction sequences abort cycle that currently progress, reset device Read Array mode. necessary program Flash memory sector with device does this automatically before erasing (byte=FFh). During Sector Erase, memory status checked reading Error Flag (DQ5) bit, Toggle Flag (DQ6) bit, Data Polling Flag (DQ7) bit, detailed section entitled "Programming Flash Memory", page
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During execution Erase cycle, Flash memory accepts only Reset Suspend Sector Erase instruction sequences. Erasure Flash memory sector suspended, order read data from another Flash memory sector, then resumed. address provided with initial Flash Sector Erase command sequence (Table must select first desired sector (FS0 CSBOOT0CSBOOT3) erase. Subsequent sector erase commands that appended within timeout period must addressed other desired segments (FS0 CSBOOT0-CSBOOT3). Suspend Sector Erase. When Sector Erase cycle progress, Suspend Sector Erase instruction sequence used suspend cycle writing 0B0h address when appropriate Sector Select (FS0-FS7 CSBOOT0CSBOOT3) selected (See Table This allows reading data from another Flash memory sector after Erase cycle been suspended. Suspend Sector Erase accepted only during Erase cycle defaults Read mode. Suspend Sector Erase instruction sequence executed during Erase time-out period, addition suspending Erase cycle, terminates time period. Toggle Flag (DQ6) stops toggling when device internal logic suspended. status this must monitored address within Flash memory sector being erased. Toggle Flag (DQ6) stops toggling between after Suspend Sector Erase instruction sequence been executed. device then automatically Read mode. Suspend Sector Erase instruction sequence executed, following rules apply: Attempting read from Flash memory sector that being erased outputs invalid data. Reading from Flash memory sector that being erased valid. Flash memory cannot programmed, only responds Resume Sector Erase Reset Flash instruction sequences (Read operation allowed). Reset Flash instruction sequence received, data Flash memory sector that being erased invalid. Resume Sector Erase. Suspend Sector Erase instruction sequence previously executed, erase cycle resumed with this instruction sequence. Resume Sector Erase instruction sequence consists writing 030h address while appropriate Sector Select (FS0-FS7 CSBOOT0-CSBOOT3) active. (See Table Flash Memory Sector Protect. Each Flash memory sector separately protected against Program Erase cycles. Sector Protection provides additional data security because disables Program Erase cycles. This mode activated through JTAG Port Device Programmer. Sector protection selected each sector using PSDsoft Express. This automatically protects selected sectors when device programmed through JTAG Port Device Programmer. Flash memory sectors unprotected allow updating their contents using JTAG Port Device Programmer. read (but cannot change) sector protection bits. attempt program erase protected Flash memory sector ignored device. Verify operation results read protected data. This allows guarantee retention Protection status. sector protection status read through Main Flash memory protection register csiop block) defined Table Secondary Flash memory protection register Table
Table Main Flash Memory Protection Register Definition
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Note: Definitions: Sec<i>_Prot Flash memory sector write protected. Sec<i>_Prot Flash memory sector write protected.
Table Secondary Flash Memory Protection/Security Register Definition
Security_Bit used used used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Note: Security_Bit device secured. Note: Sec<i>_Prot Flash memory sector write protected. Sec<i>_Prot Flash memory sector write protected.
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Security programmable security protects contents from unauthorized viewing copying. When set, security will block access programming devices (JTAG others) Flash memory configuration. only defeat security erase entire device, after which device blank used again. will always have access Flash memory contents through 8-bit data port even while security set. read status security (but cannot change reading Device Security register csiop block defined Table Reset Flash Reset Flash instruction sequence resets internal memory logic state machine puts Flash memory into Read Array mode. consists write cycle (see Table must executed after: Reading Flash Protection Status Flash Error condition occurred (and device Error Flag (DQ5) during Flash memory Program Erase cycle. Reset Flash instruction sequence puts Flash memory back into normal Read Array mode. take Flash memory milliseconds complete Reset cycle. Reset Flash instruction sequence ignored when issued during Program Bulk Erase cycle Flash memory. Reset Flash instruction sequence aborts on-going Sector Erase cycle, returns Flash memory normal Read Array mode within milliseconds. Page Register 8-bit Page Register increases addressing capability factor 256. contents register also read DSP. outputs Page Register (PG0PG7) inputs DPLD decoder included Sector Select FS0-FS7 CSBOOT0-CSBOOT3) equations. Figure memory paging needed, page register bits needed memory paging, then these bits used CPLD general logic. eight flip-flops register connected internal data D0-D7. write read from Page Register. Page Register accessed address location csiop E0h. Page Register outputs cleared logic reset. Figure Page Register
RESET
PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 DPLD CPLD
INTERNAL SELECTS LOGIC
PGR7
PAGE REGISTER
PLDs PLDs bring programmable logic device. After specifying logic PLDs using PSDsoft Express, logic programmed into device available upon Power-up. PLDs have selectable levels performance power consumption. device contains PLDs: Decode (DPLD), Complex (CPLD), shown Figure Table DPLD CPLD InputInput Source Address Bus1 Control Signals2 Reset PortB Input Macrocells PortC Input Macrocells Port Inputs Page Register Macrocell Feedback Macrocell Feedback Flash memory Program Status Input Name A15-A0 CNTL2-CNTL0 PB7-PB0 PC7-PC0 PD2-PD0 PG7-PG0 MCELLAB FB7-0 MCELLBC FB7-0 Ready/Busy Number Signals
Note: address lines A16, A17, others enter device ports Figure recommended connections. Additional control signals enter device Ports Figure recommended connections.
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DPLD performs address decoding, generates select signals internal external components, such memory, registers, ports. DPLD generates External Chip Select (ECS0-ECS2) signals Port CPLD used logic functions, such loadable counters shift registers, state machines, encoding decoding logic. These logic functions constructed using Output Macrocells (OMC), Input Macrocells (IMC), Array. Array used form product terms. These product terms configured from logic definition entered PSDsoft Express. Input consisting signals connected PLDs. Input signals shown Table Figure Diagram Turbo Bit. PLDs device minimize power consumption switching when inputs remain unchanged extended time about Resetting Turbo (Bit PMMR0 register) automatically places PLDs into standby inputs changing. Turning Turbo mode increases propagation delays while reducing power consumption. Additionally, five bits available PMMR registers csiop block control signals from entering PLDs. This reduces power consumption used only when these control signals used logic equations. Each PLDs unique characteristics suited applications. They described following sections.
PAGE REGISTER
Data
DECODE (DPLD)
Main Flash Memory Selects Secondary Flash Memory Select
CSIOP Select External Chip Selects Port JTAG Select
INPUT
Output Macrocell Feedback
Direct Macrocell Access from Data
CPLD
ALLOC.
Output Macrocell
Macrocell Alloc.
MCELLAB PORT
Input Macrocell (PORT B,C)
Direct Macrocell Input Data Input Macrocell Input Port
PORT InputAI04957B
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MCELLBC PORT
DSM2190F4
DECODE (DPLD) DPLD, shown Figure used decoding address internal external components. DPLD used generate following decode signals: Main Flash memory Sector Select (FS0-FS7 signals with three product terms each
internal csiop select device control status registers (csiop base address block byte locations) JTAG Select signal (enables JTAG operations Port when multiplexing JTAG signals with general signals) external chip select output signals Port pins, each with product term.
Secondary Flash memory Sector Select (CSBOOT0-CSBOOT3) signals with three product terms each
Figure DPLD Logic Array
(INPUTS) PORTS (PORT B,C) MCELLAB.FB (Feedback) MCELLBC.FB (Feedback PG0-PG7 A[15:0] PD[2:0] (16) (16) CNTRL[2:0] (Read/Write Control Signals)(3) RESET RD_BSY CSIOP JTAGSEL ECS0 ECS1 ECS2
AI04958
CSBOOT0 CSBOOT1 CSBOOT2 CSBOOT3 Flash Main Memory Sector Selects Secondary Flash Memory Sector Select
Decoder Select JTAG
External Chip Selects PORT
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COMPLEX (CPLD) CPLD used implement system logic functions, such loadable counters shift registers, system mailboxes, handshaking protocols, state machines, random logic. application note AN1171 details specify logic using PSDsoft Express. shown Figure CPLD following blocks: Input Macrocells (IMC)
Ports.
Output Macrocells (OMC) Macrocell Allocator Product Term Allocator Array capable generating product term
Each blocks described sections that follow. Input Macrocells (IMC) Output Macrocells (OMC) connected device internal data directly accessed DSP. This enables software load data into Output Macrocells (OMC) read data from both Input Output Macrocells (IMC OMC). This feature allows efficient implementation system logic eliminates need connect data Array required most standard macro cell architectures.
Figure Macrocell Port
INPUT Product Terms from other MacrocellS ADDRESS DATA OTHER PORTS
CPLD MacrocellPT PRESET PRODUCT TERM ALLOCATOR DATA LOAD DATA LOAD CONTROL
PORTS
LATCHED ADDRESS DATA
ARRAY
PRODUCT TERMS Macrocell CPLD OUTPUT
CLOCK COMB. /REG SELECT CPLD OUTPUT Macrocell Port Alloc. CLEAR INPUT SELECT
INPUT
GLOBAL CLOCK CLOCK SELECT
D/T/JK SELECT
POLARITY SELECT
REG.
Output Enable (OE) Macrocell Feedback Port Input
Input MacrocellMUX
INPUT LATCH GATE/CLOCK
AI04902B
Output Macrocell (OMC). Eight Output Macrocells (OMC) connected Port pins named McellAB0-McellAB7. other eight Macrocells connected Ports pins named McellBC0-McellBC7. OMCs used internal feedback only (buried registers), their outputs routed external Port pins.
Output Macrocell (OMC) architecture shown Figure shown figure, there native product terms available from Array, borrowed product terms available unused) from other Output Macrocells (OMC). polarity product term controlled gate. Output Macrocell (OMC) implement either sequential logic, using flip-flop
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element, combinatorial logic. multiplexer selects between sequential combinatorial logic outputs. multiplexer output drive port feedback path Array inputs. flip-flop Output Macrocell (OMC) block configured type PSDsoft ExpressTM. flip-flop's clock, preset, clear inputs driven from product term Array. Alternatively, CLKIN (PD1) used clock input flip-flop. flip-flop clocked rising edge CLKIN (PD1). preset clear active High inputs. Each clear input product terms. Output Macrocell Allocator. Outputs OMCs routed combination pins Port Port shown Figure output automatically determined choosing functions PSDsoft ExpressTM. Routing occur bit-by-bit basis, spitting assignment between Ports. However, routed Port only, both. Figure Allocator
PORT PINS
PORT PINS
OMCs (MCELLAB)
OMCs (MCELLBC)
AI04915
Table Output Macrocell Port Data AssignmentOutput Macrocell McellAB0 McellAB1 McellAB2 McellAB3 McellAB4 McellAB5 McellAB6 McellAB7 McellBC0 McellBC1 McellBC2 McellBC3 McellBC4 McellBC5 McellBC6 McellBC7 Port Assignment Port Port Port Port Port Port Port Port Port Port Port Port orC3 Port orC4 Port Port orC6 Port orC7 Native Product Terms Maximum Borrowed Product Terms Data Loading Reading
Product Term Allocator. CPLD Product Term Allocator. PSDsoft Expressuses Product Term Allocator borrow place product terms from Macrocell another. This happens automatically PSDsoft ExpressTM, understanding allocation works will help your logic design does "fit", which case selecting different different where allocation resources differ
design will then fit. following list summarizes product terms allocated: McellAB0-McellAB7 have three native product terms borrow more
McellBC0-McellBC3 have four native product terms borrow five more McellBC4-McellBC7 have four native product terms borrow more.
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Each Macrocell only borrow product terms from certain other Macrocells. Product terms already Macrocell available another Macrocell. Product term allocation does propagation delay logic. equation requires more product terms than available through product term allocation, then "external" product terms required, which consumes other Output Macrocells (OMC). This called product term expansion also happens automatically PSDsoft Expressas needed. Product tern expansion causes additional propagation delay because consumed expansion it's output rerouted back) into array. examine fitter report generated PSDsoft Express resulting product term allocation product term expansion. Figure CPLD Output Macrocell Loading Reading Output Macrocells (OMCs). Each blocks OMCs each) occupies memory location address space, defined csiop block MCELLAB0-7 MCELLBC0-7 (see Table flip-flops each OMCs loaded from data DSP. Loading OMCs with data from takes priority over internal functions. such, preset, clear, clock inputs flip-flop overridden DSP. ability load flip-flops read them back useful such applications loadable counters shift registers, mailboxes, handshaking protocols. Data loaded into Output Macrocells (OMC) trailing edge Write Strobe (WR, CNTL0).
MASK REG.
Output Macrocell
INTERNAL DATA
7:0]
Allocator
Direction Register ENABLE (.OE) PRESET(.PR) COMB/REG SELECT
ARRAY
INPUT
POLARITY SELECT CLEAR (.RE) CLKIN Programmable T/JK /SR) Port Driver Macrocell Allocator
Feedback (.FB) Port Input Input Macrocell
AI04903B
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Mask Register. There Mask Register each groups eight Output Macrocells (OMC). Mask Registers used block loading data individual Output Macrocells (OMC). default value Mask Registers 00h, which allows loading Output Macrocells (OMC). When given Mask Register blocked from writing associated Output Macrocells (OMC). example, suppose McellAB0-3 being used state machine. would want write McellAB overwrite state machine registers. Therefore, would want load Mask Register McellAB (Mask Macrocell with value 0Fh. Figure Input Macrocell
INTERNAL DATA
Output Enable OMC. Output Macrocells (OMC) block connected port output. output enable each port driver controlled single product term from Array, ORed with Direction Register output. enabled upon Power-up output enable equation defined declared output PSDsoft Express. Output Macrocell (OMC) output specified internal node port output PSDsoft Express, then port used other functions. internal node feedback routed input Array.
INPUT MACROCELL ENABLE OUTPUT Macrocells Macrocells
DIRECTION REGISTER
ARRAY
INPUT
Port Driver
Feedback LATCH Input Macrocell
AI04904C
Input Macrocells (IMC). CPLD Input Macrocells (IMC), each Ports architecture IMCs shown Figure IMCs individually configurable, used latch, register, pass incoming Port signals prior driving them onto input bus. This useful sampling debouncing inputs array (keypad inputs, etc.). Additionally, outputs IMCs read asynchronously time
through internal data using csiop register block (see Table enable latch clock register driven product term from CPLD. Each product term output used latch clock four IMCs. Port inputs controlled product term another. Configurations IMCs specified equations specified PSDsoft Express. Application note AN1171.
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Interface "no-glue logic" Interface allows direct connection. address, data, control signals connect directly device. Figure typical connections. address, data control signals routed Flash memory, control (csiop), OMCs, IMCs within DMS. address range each these components specified PSDsoft Express Ports There three programmable ports: Ports Each ports eight bits except Port which bits. Each port individually user configurable, thus allowing multiple functions port. ports configured using PSDsoft ExFigure General Port Architecture
DATA REG. PORT OUTPUT Macrocell Outputs INTERNAL DATA READ DATA OUTPUT SELECT
pressor writing on-chip registers csiop block. topics discussed this section are: General Port architecture
Port operating modes Port Configuration Registers (PCR) Port Data Registers Individual Port functionality.
General Port Architecture. general architecture Port block shown Figure Individual Port architectures shown Figure Figure general, once purpose port been defined PSDsoft ExpressTM, that longer available other purposes. Exceptions noted.
DATA
ENABLE
REG. ENABLE PRODUCT TERM (.OE) Input Macrocell CPLD INPUT
AI04905B
shown Figure ports contain output multiplexer whose select signals driven configuration bits determined PSDsoft Express. Inputs multiplexer include following: Output data from Data register (for mode)
External Chip Selects ESC0-2 from DPLD Port pins only.
CPLD Macrocell output (OMC)
Port Data Buffer (PDB) tri-state buffer that allows only source time read DSP. Port Data Buffer (PDB) connected Internal Data feedback read DSP. Data Macrocell out-
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puts, Direction Registers, port input connected Port Data Buffer (PDB). Port pin's tri-state output driver enable controlled input gate whose inputs come from CPLD Array enable product term Direction Register. enable product term Array outputs defined that port defined CPLD output PSDsoft Express then Direction Register sole control buffer that drives port pin. contents these registers altered DSP. Port Data Buffer (PDB) feedback path allows check contents registers. Ports have embedded IMCs. IMCs configured registers (for sampling deTable Port Operating ModePort Mode McellAB Outputs McellBC Outputs Additional External Outputs Inputs JTAG
Note: multiplexed with other functions.
bouncing), transparent latches, direct inputs PLDs. registers latches clocked product term from Array. outputs from IMCs drive input read DSP. section entitled "Input Macrocell", page Port Operating Modes Ports have several modes operation. Modes defined using PSDsoft ExpressTM, then runtime control from occur using registers csiop block. Application Note AN1171 more detail. Table summarizes which modes available each port. Each port operating modes described following sections.
Port
Port Yes1
Port
Mode. mode, uses Ports block expand ports. read pins, direction pins, change state pins accessing registers csiop block. csiop register definition their addresses found Table direction changed writing corresponding Direction Register, output enable product term. When configured output, content Data Register drives pin. When configured input, read port input through Data buffer. Figure Mode. Inputs from Ports either (DPLD CPLD) come through IMCs. Inputs from Port either PLDs routed directly IMCs. Outputs from CPLD Port come from group MCELLAB0-7. Outputs from CPLD Port come from group MCELLBC0-7. Outputs from DPLD Port come from external chip select logic block ECS0-2. outputs tri-stated Port pins with control signal. This output enable control signal defined product term from
PLD, resetting corresponding Direction Register corresponding Direction Register must logic defined input signal PSDsoft Express. mode defined PSDsoft Express specifying equations. JTAG In-System Programming (ISP). Some pins Port based IEEE 1194.1 JTAG specification used In-System Programming (ISP). multiplex function these Port JTAG pins with other functions. performed very frequently life product, multiplexing these pin's functions with general purpose functions gives more utility from Port section entitled "Programming In-Circuit Using JTAG ISP", Application Note AN1153. Port Configuration Registers (PCR). Each Port Port Configuration Registers (PCR) used configuration pins. contents registers accessed through normal read/write cycles csiop registers listed Table pins port individually configurable each register controls respective pin. example, register refers
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port. three Port Configuration Registers (PCR), shown Table Default logic Table Port Configuration Registers (PCR)
Register Name Data Data Direction Drive Select
Table Port Direction Control, Output Enable P.T. Defined
Direction Register Output Enable P.T. Port Mode Input Output Output Output
Port B,C,D B,C,D B,C,D B,C,D
Access Read Write/Read Write/Read Write/Read
Note: Table Drive Register definition.
Table Port Direction Assignment Example
Data Register. read Data registers csiop block time determine logic state Port pin. This will state regardless whether driven source external driven internally from device. Reading logic zero Data register means corresponding Port also logic zero. Reading logic means logic one. Each Data register corresponds individual Port pin. given Port, Data register corresponds Port. Example, Data register Port corresponds Port PB0. Data Register. write read) Data register csiop block time. Writing Data register will change logic state Port only driven controlled CPLD. Writing logic zero Data register will force corresponding Port logic zero. Writing logic will drive logic one. Each Data registers correspond Port pins same Data registers described above. When some pins Port driven CPLD, writing corresponding Data register will have effect CPLD overrides Data register. Direction Register. Direction Register, conjunction with output enable (except Port controls direction data flow Ports. Direction Register causes corresponding output, causes input. default mode port pins input. Table Port Direction Control, Output Enable P.T. Defined
Direction Register Input Output Port Mode
Figure Figure show Port Architecture diagrams Ports respectively. direction data flow Ports controlled only direction register, also output enable product term from Array. output enable product term active, Direction Register sole control given pin's direction. example configuration Port with three least significant bits output remainder input shown Table Since Port only contains three pins (shown Figure 23), Direction Register Port only three least significant bits active. Drive Select Register. Drive Select Register configures driver Open Drain CMOS (standard push/pull) some port pins, controls slew rate other port pins. external pull-up resistor should used pins configured Open Drain. Open Drain outputs diode clamped, thus maximum voltage configured Open Drain 0.7V. configured Open Drain corresponding Drive Select Register default drive CMOS. Note that slew rate measurement rise fall times output. higher slew rate means faster output response create more electrical noise. operates high slew rate when corresponding Drive Register default rate standard slew. Table shows Drive Register Ports summarizes which pins configured Open Drain outputs which pins slew rate for.
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Table Drive Register Assignment
Drive Register Port Port Port Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Slew Rate Open Drain Slew Rate Open Drain Slew Rate Slew Rate Open Drain Slew Rate Slew Rate Open Drain Slew Rate
Note: Applicable.
Figure Port Structure
DATA REG.
DATA
PORT OUTPUT MACROCELL OUTPUTS READ DATA OUTPUT SELECT
INTERNAL DATA
ENABLE
REG. ENABLE PRODUCT TERM (.OE) Input Macrocell
CPLD INPUT
AI04906B
Port Functionality Structure Port configured perform more following functions: Mode
CPLD Input Input Macrocells (IMC). Open Drain/Slew Rate pins PB3-PB0 configured fast slew rate, pins PB7-PB4 configured Open Drain Mode.
CPLD Output Macrocells McellAB7-McellAB0 connected Port McellBC7McellBC0 connected Port Port
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Figure Port Structure
DATA REG. PORT OUTPUT DATA
JTAG
MCELLBC READ
INTERNAL DATA
DATA
OUTPUT SELECT
ENABLE
REG. ENABLE PRODUCT TERM (.OE) INPUT MACROCELL
CPLD INPUT
JTAG
CONFIGURATION
AI04907
Port Functionality Structure Port configured perform more following functions (see Figure 21): Mode
CPLD Output McellBC7-McellBC0 outputs connected Port Port CPLD Input Input Macrocells (IMC)
In-System Programming (ISP) JTAG port enabled programming/erase device. (See section entitled "Programming In-Circuit Using JTAG ISP", Application Note AN1153, more information JTAG programming.) Open Drain Port pins configured Open Drain Mode
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Figure Port Structure
DATA REG. DATA PORT OUTPUT ECS[ 2:0] READ
INTERNAL DATA
DATA
OUTPUT SELECT
REG. CPLD-INPUT
ENABLE PRODUCT TERM (.OE)
AI02889
Port Functionality Structure Port three pins. Figure Figure Port configured perform more following functions: Mode
Chip Select Input (CSI, PD2). Driving this signal logic High disables Flash memory, putting standby mode.
DPLD Output External Chip Selects, ECS0-2 does consume OMCs CPLD Input direct input CPLD, does IMCs Slew rate pins fast slew rate Port pins configured PSDsoft input pins other dedicated functions: CLKIN (PD1) input OMCs Flip-flop
External Chip Select. DPLD also provides three External Chip Select outputs (ESC0-2) Port pins that used select external devices defined PSDsoft Express. Each External Chip Select consists product term that configured active High Low. output enable controlled either output enable product term Direction Register. (See Figure 23.) External Chip Selects Port pins consume OMCs. External chip select outputs also come from CPLD chip select equations specified PSDsoft Express Ports
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Figure Port External Chip Select Signal
ENABLE (.OE)
DIRECTION REGISTER
ECS0 POLARITY ENABLE (.OE) DIRECTION REGISTER
CPLD ARRAY
INPUT
ECS1 POLARITY ENABLE (.OE) DIRECTION REGISTER
ECS2
POLARITY
AI02890
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POWER MANAGEMENT device offers configurable power saving options. These options used individually combinations, follows: memory blocks device built with zero-power management technology. Zeropower technology puts memories into standby mode when address/data inputs changing (zero current). soon transition occurs input, affected memory "wakes up", changes latches outputs, then goes back standby. designer does have anything special achieve memory standby mode when inputs changing-it happens automatically. Both PLDs (DPLD CPLD) also Zeropower, this default operation. must run-time achieve Zeropower described next. PMMR registers written run-time manage power. device Turbo PMMR0 register. This turn Turbo mode (the default with Turbo mode turned on). While Turbo mode off, PLDs achieve standby current when inputs changing (zero current). Even when inputs change, significant power saved lower frequencies current),
compared when Turbo mode When Turbo mode there significant current component component higher. Further significant power savings achieved blocking signals that used DPLD CPLD logic equations. "blocking bits" PMMR registers logic block designated signals from reaching both PLDs. Current consumption PLDs directly related composite frequency changes their inputs (see Figure 25), blocking unused inputs significantly lower operating frequency power consumption. also option blocking certain input when needed, then letting them pass when needed specific logic operations. Table Table define PMMR registers. Chip Select Input (CSI, PD2) used disable internal memories csiop registers, placing them standby mode even inputs changing. This feature does block internal signals disable PLDs. There slight penalty memory access time when Chip Select Input (CSI, PD2) makes initial transition from deselected selected.
Table Power Management Mode Registers PMMR01
Turbo Turbo mode off, saving power. Array CLKIN (PD1) input Array passed onto PLDs. Every change CLKIN (PD1) Powers-up when Turbo used, should zero. used, should zero. used, should zero.
Turbo mode
CLKIN (PD1) input Array blocked, saving power. CLKIN (PD1) input Macrocells passed onto PLDs. MCell CLKIN (PD1) input Macrocells blocked, saving power. used, should zero. used, should zero.
Note: bits this register cleared zero following Power-up. Subsequent Reset (Reset) pulses clear registers.
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Power Management power speed PLDs controlled Turbo (bit PMMR0. setting Turbo mode PLDs consume specified stand-by current when inputs switching extended time (100 devices). propagation delay time increased after Turbo (turned off) when inputs change composite frequency less than devices). When Turbo reset (turned on), PLDs full power speed. Turbo affects PLD's power, power, propagation delay. Blocking control signals with bits PMMR registers further reduce power consumption lowering effective composite frequency inputs PLDs.
Table Power Management Mode Registers PMMR2
Array CNTL0 Array CNTL1 Array CNTL2 Array Array used, should zero. used, should zero.
Cntl0 input Array passed onto PLDs. Cntl0 input Array blocked, saving power. Cntl1 input Array passed onto PLDs. Cntl1 input Array blocked, saving power. Cntl2 input Array passed onto PLDs. Cntl2 input Array blocked, saving power. input Array passed onto PLDs. input Array blocked, saving power. input Array passed onto PLDs. input Array blocked, saving power. used, should zero.
Note: bits this register cleared zero following Power-up. Subsequent Reset (Reset) pulses clear registers.
Chip Select Input (CSI, PD2) Port configured PSDsoft Express Chip Select Input (CSI). When Low, signal selects enables internal Flash memory blocks Read Write operations involving device. High Chip Select Input (CSI, PD2) disables Flash memory reduces device power consumption. However, signals remain operational when Chip Select Input (CSI, PD2) High. There timing penalty when using Chip Select Input CSI, PD2) depending speed grade device that using. timing parameter tSLQV Table Input Clock. device provides option block CLKIN (PD1) from reaching PLDs save power consumption. CLKIN (PD1) input Array OMCs. CLKIN (PD1) being used part logic equation, clock should blocked save power. CLKIN (PD1) disconnected
from Array Macrocells block setting bits PMMR0. Input Control Signals. device provides option block input control signals (CNTL0, CNTL1, CNTL2, PD0, PC7) from reaching PLDs save power consumption. These control signals inputs Array. these being used part logic equation, these control signals should disabled save power. They disconnected from Array setting bits PMMR2 register. Note: CNTL0 CNTL1 (DSP permanently routed Flash memory array cannot blocked from array PMMR registers (that's signals have specified PSDsoft Express Flash memory segment chip-select equations FS7). CNTL0 CNTL1 blocked from PLDs with PMMR registers bits when these signals specifically used logic equations specified PSDsoft Express.
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DSM2190F4
Figure Reset (RESET) Timing
VCC(min) tNLNH tNLNH-A Warm Reset
tNLNH-PO Power-On Reset
tOPR
tOPR
RESET
AI02866b
Power Reset, Warm Reset, Power-down Power Reset. Upon Power-up, device requires Reset RESET) pulse duration tNLNH-PO after steady. During this time period, device loads internal configurations, clears some registers sets Flash memory into Operating mode. After rising edge Reset (RESET), device remains Reset mode additional period, OPR, before first memory access allowed.
Flash memory reset Read Array mode upon Power-up. Sector Select FS0-FS7 must Low, Write Strobe (WR, CNTL0) High, during Power Reset maximum security data contents remove possibility byte being written first edge Write Strobe (WR, CNTL0). Flash memory Write cycle initiation prevented automatically when below VLKO.
Table Status During Power-On Reset, Warm Reset Power-down Mode
Port Configuration Output Power-On Reset Input mode Valid after internal configuration bits loaded Warm Reset Input mode Valid Power-down Mode Unchanged Depends inputs (addresses blocked mode)
Register PMMR0 PMMR2 Flip-flop status other register
Power-On Reset Cleared Cleared internal Power-On Reset Cleared
Warm Reset Unchanged Depends equations Cleared
Power-down Mode Unchanged Depends equations Unchanged
Warm Reset. Once device running, device reset with pulse much shorter duration, tNLNH. same tOPR period needed before device operational after warm reset. Figure shows timing Power-up warm reset. Pin, Register Status Reset. Table shows pin, register status during Power Reset, warm reset Power-
down mode. outputs always valid during warm reset, they valid Power Reset once internal device Configuration bits loaded. This loading device completed typically long before ramps operating level. Once active, state outputs determined PSDsoft Express equations.
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PROGRAMMING IN-CIRCUIT USING JTAG In-System Programming (ISP) performed through JTAG signals Port This serial interface allows programming entire device subsections (i.e. only Flash memory PLDs) without participation DSP. blank device soldered circuit board completely programmed seconds. basic JTAG signals; TMS, TCK, TDI, form IEEE-1149.1 interface. device does implement IEEE-1149.1 Boundary Scan functions. uses JTAG interface only. However, device reside standard JTAG chain with other JTAG devices will remain BYPASS mode while other devices perform Boundary Scan. programming time reduced much using more signals Port TSTAT TERR addition TMS, TCK, TDO. Table FlashLINKJTAG programming cable available from STMicroelectronics $59USD PSDsoft Express software that available charge from www.st.com/psm that needed program device using parallel port laptop. default, four pins Port enabled basic JTAG signals TMS, TCK, TDI, blank device (and shipped from factory) Application Note AN1153 more details JTAG In-System Programming (ISP). Standard JTAG Signals. standard JTAG signals (TMS, TCK, TDI, TDO) enabled three different conditions that logically ORed. following symbolic logic equation specifies conditions enabling four basic JTAG signals (TMS, TCK, TDI, TDO) their respective Port pins. purposes discussion, logic label JTAG_ON used. When JTAG_ON true, four pins enabled JTAG operation. When JTAG_ON false, four pins used general device specified PSDsoft Express. JTAG_ON become true three different ways shown: JTAG_ON PSDsoft Express Configuration -OR2. PSDsoft Express equation -OR3. writes register csiop block Method most common. This when JTAG pins selected PSDsoft Express "dedicated" JTAG pins. They always transmit receive JTAG information because they "fulltime" JTAG pins.
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Method used only when JTAG pins multiplexed with general functions. designs that need every pin, JTAG pins used general when they used ISP. However, when JTAG pins multiplexed with general functions, designer must include pins back into JTAG mode when time JTAG operations again. this case, single input from Ports must dedicated switch Port pins from mode back mode time. recommended physically connect this dedicated input JEN\ output signal from Flashlink cable when multiplexing JTAG signals. Application Note AN1153 details. Method rarely used control JTAG operation. port pins function JTAG setting JTAG Enable register csiop block, soon chip reset, csiop block registers cleared, which turns JTAG-ISP function. Controlling JTAG pins using this method recommended. Table JTAG Port SignalPort JTAG Signals TSTAT TERR Description Mode Select Clock Status Error Flag Serial Data Serial Data
JTAG Extensions. TSTAT TERR JTAG extension signals (must used pair) enabled command received over four standard JTAG signals (TMS, TCK, TDI, TDO) PSDsoft Express. They used speed Program Erase cycles indicating status device pins instead having scan status serially using standard JTAG channel. Application Note AN1153. TERR indicates error occurred when erasing sector programming byte Flash memory. This signal goes (active) when Error condition occurs. TSTAT behaves same Ready/Busy described previously. TSTAT inactive logic when device Read mode (Flash memory contents read). TSTAT logic when Flash memory Program Erase cycles progress. TSTAT TERR configured opendrain type signals with PSDsoft Express. This facilitates wired-OR connection TSTAT signal
DSM2190F4
from multiple DSM2190F4V devices wiredOR connection TERR signals from those same devices. This useful when several devices "chained" together JTAG environment. PSDsoft Express puts TSTAT TERR signals open-drain default. Click 'Properties' JTAG-ISP window PSDsoft Express change standard CMOS push-pull. recommended pull-up resistors JTAGISP signals your circuit board. Initial Delivery State When delivered from device bits memory PLDs erased logic Configuration Register bits code, configuration, logic loaded using programming procedure. four basic JTAG signals (TCK, TMS, TDI, TDO) ready function.
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AC/DC PARAMETERS These tables describe parameters device: Electrical Specification Timing Specification Timing Combinatorial Timing Synchronous Clock Mode Asynchronous Clock Mode Input Macrocell Timing
specification supply current given different modes operation. Before calculating total power consumption, determine percentage time that device each mode. Also, supply power considerably different Turbo power component gives Flash memory mA/MHz specification. Figure shows mA/MHz function number Product Terms (PT) used. fitter report PSDsoft Express indicates number Product Terms (PTs) used given design. This number used estimate power consumption using Figure timing parameters, required delay when Turbo
Timing Read Timing Write Timing Reset Timing
following issues concerning parameters presented:
Figure /Frequency Consumption (3.3
(mA)
100%
TURB
100%
AI03100
HIGHEST COMPOSITE FREQUENCY INPUTS (MHz)
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MAXIMUM RATING Stressing device above rating listed Absolute Maximum Ratings table cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification imTable Absolute Maximum RatingSymbol TSTG TLEAD VESD Storage Temperature Lead Temperature during Soldering seconds max.)1 Input Output Voltage Hi-Z) Supply Voltage Device Programmer Supply Voltage Electrostatic Discharge Voltage (Human Body model) -0.6 -0.6 -0.6 -2000 Parameter Min. Max. 14.0 2000 Unit
plied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents.
Note: IPC/JEDEC J-STD-020A JEDEC JESD22-A114A (C1=100 R1=1500 R2=500
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PARAMETERS This section summarizes operating measurement conditions, characteristics device. parameters Characteristic tables that follow derived from tests performed under MeasureTable Operating ConditionSymbol Supply Voltage Ambient Operating Temperature (industrial) Parameter Min. Max. Unit
ment Conditions summarized relevant tables. Designers should check that operating conditions their circuit match measurement conditions when relying quoted parameters.
Table Measurement ConditionSymbol Load Capacitance Input Rise Fall Times Input Pulse Voltages Input Output Timing Reference VoltageNote: Output Hi-Z defined point where data longer driven.
Parameter
Min.
Max.
Unit
Figure Measurement Waveform
Figure Measurement Load Circuit
0.9VCC Test Point
AI04947
1.5V Device Under Test
(Including Scope Capacitance)
AI04948
Table Capacitance
Symbol COUT CVPP Parameter Input Capacitance (for input pins) Output Capacitance (for input/ output pins) Capacitance (for CNTL2/VPP) Test Condition VOUT Typ.2 Max. Unit
Note: Sampled only, 100% tested. Typical values 25°C nominal supply voltages.
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Table Symbols Timing
Signal Letters Address Input CEout Output Input Data Input Reset Input Output Port Signal Output Output Data Input (read) Chip Select Input, BMS, DMS, IOMS, Input (write) VSTBY Output Output Macrocell Time Logic Level Logic Level High Valid Longer Valid Logic Level Float Pulse Width Signal Behavior
Example: tAVWL Time from Address Valid Write input Low. Figure Switching Waveforms
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
STEADY OUTPUT
CHANGE FROM CHANGE FROM
WILL CHANGING FROM WILL CHANGING
DON'T CARE
CHANGING, STATE UNKNOWN
OUTPUTS ONLY
CENTER LINE TRI-STATE
AI03102
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Table CharacteristicSymbol VIH1 VIL1 VHYS VLKO Parameter High Level Input Voltage Level Input Voltage Conditions Min. 0.7VCC -0.5 0.8VCC -0.5 3.0V Output Voltage Output High Voltage Except VSTBY Output High Voltage VSTBY Idle Current (VSTBY input) SRAM Data Retention Voltage Stand-by Supply Current Power-down Mode Input Leakage Current Output Leakage Current IOH1 VSTBY Only VSTBY >VCC -0.3 (Notes 2,3) 0.45 PLD_TURBO Off, (Note PLD_TURBO During Flash memory Write/ Flash memory Erase Only Read Only, VSTBY -0.1 0.15 2.99 0.45 µA/PT µA/PT 0.01 Typ. Max. +0.5 +0.5 0.2VCC -0.1 Unit
Reset High Level Input Voltage (Note Reset Level Input Voltage Reset Hysteresis (min) Flash Erase Program (Note
VOH1 IIDLE
Only (DC) (Note Operating Supply Current
Adder (AC) (Note Flash memory Adder
(see note
Note:
Reset (Reset) hysteresis. VIL1 valid below 0.2VCC -0.1. VIH1 valid above 0.8VCC deselected. non-Turbo mode, none inputs switching. Please Figure current calculation. IOUT
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Table CPLD Combinatorial Timing
Symbol Parameter CPLD Input Pin/Feedback CPLD Combinatorial Output CPLD Input CPLD Output Enable CPLD Input CPLD Output Disable CPLD Register Clear Preset Delay CPLD Register Clear Preset Pulse Width CPLD Array Delay Macrocell Conditions tARP tARPW tARD Aloc Turbo Slew Rate1 Unit
Note: Fast Slew Rate output available PB3-PB0, PD2-PD0.
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Table CPLD Macrocell Synchronous Clock Mode Timing
Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Time Clock Output Delay CPLD Array Delay Minimum Clock Period2 Clock Input Clock Input Clock Input Macrocell tCH+tCL Conditions 1/(tS+tCO) 1/(tS+tCO-10) 1/(tCH+tCL) 18.8 23.2 33.3 Aloc Turbo Slew Rate1 Unit
Note: Fast Slew Rate output available PB3-PB0, PD2-PD0. CLKIN (PD1) CLCL
Table CPLD Macrocell Asynchronous Clock Mode Timing
Symbol Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tCHA tCLA tCOA tARD tMINA Input Setup Time Input Hold Time Clock High Time Clock Time Clock Output Delay CPLD Array Delay Minimum Clock Period Macrocell 1/fCNTA Conditions 1/(tSA+tCOA) 1/(tSA+tCOA-10) 1/(tCHA+tCLA) 19.2 23.8 Aloc Turbo Slew Rate Unit
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Figure Input Output Disable Enable
INPUT
INPUT OUTPUT ENABLE/DISABLE
AI02863
Figure Asynchronous Reset Preset
tARPW
RESET/PRESET INPUT tARP REGISTER OUTPUT
AI02864
Figure Synchronous Clock Mode Timing
CLKIN
INPUT
REGISTERED OUTPUT
Figure Asynchronous Clock Mode Timing (product term clock)
tCHA tCLA
CLOCK
INPUT tCOA REGISTERED OUTPUT
AI02859
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Table Input Macrocell Timing
Symbol tINH tINL tINO Parameter Input Setup Time Input Hold Time Input High Time Input Time Input Combinatorial Delay Conditions (Note (Note (Note (Note (Note Aloc Turbo Unit
Note: Inputs from Port relative register/latch clock from PLD.
Figure Input Macrocell Timing (product term clock)
CLOCK
INPUT
OUTPUT
AI03101
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Table Read Timing
Symbol tAVQV tSLQV tRLQV tRHQX tRLRH tRHQZ Parameter Address Valid Data Valid Valid Data Valid Data Valid 8-Bit Data Hold Time Pulse Width Data High-Z Conditions (Note Turbo Unit
Note: input used select internal function.
Figure Read Timing
tAVQV ADDRESS NON-MULTIPLEXED DATA NON-MULTIPLEXED tSLQV tRLQV tRLRH tRHQZ tRHQX ADDRESS VALID
DATA VALID
AI04908
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Table Write Timing
Symbol tAVWL tSLWL tDVWH tWHDX tWLWH tWHAX1 tWHAX2 tWHPV tDVMV tWLMV
Note:
Parameter Address Valid Leading Edge Valid Leading Edge Data Setup Time Data Hold Time Pulse Width Trailing Edge Address Invalid Trailing Edge DPLD Address Invalid Trailing Edge Port Output Valid Using Port Data Register Data Valid Port Output Valid Using Macrocell Register Preset/Clear Valid Port Output Valid Using Macrocell Register Preset/Clear
Conditions (Notes 1.75 (Note4) (Note (Note
Unit
input used select internal function. Assuming data stable before active write signal. Assuming write active before data becomes valid. TWHAX2 address hold time DPLD inputs that used generate Sector Select signals internal memory.
Figure Write Timing
tAVWL ADDRESS NON-MULTIPLEXED DATA NON-MULTIPLEXED tSLWL tDVWH WLWH WHDX WHAX ADDRESS VALID DATA VALID
AI04909
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Table Flash Memory Program, Write Erase TimeSymbol Parameter Flash Bulk Erase1 (pre-programmed) Flash Bulk Erase (not pre-programmed) tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program Erase Cycles (per Sector) tWHWLO tQ7VQV Sector Erase Time-Out Valid Output (DQ7-DQ0) Valid (Data Polling)2 100,000 Min. Typ. 1200 Max. Unit cycles
Note: Programmed zero before erase. polling status, DQ7, valid tQ7VQV time units before data byte, DQ0-DQ7, valid reading.
Table Reset (Reset) Timing
Symbol tNLNH tNLNH-PO tOPR Parameter RESET Active Time Power Reset Active Time RESET High Operational Device Conditions Unit
Note: Reset (RESET) does reset Flash memory Program Erase cycles. Warm reset aborts Flash memory Program Erase cycles, puts device Read mode.
Figure Reset (RESET) Timing
VCC(min) tNLNH tNLNH-A Warm Reset
tNLNH-PO Power-On Reset
tOPR
tOPR
RESET
AI02866b
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Table Timing
Symbol tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ Parameter Clock (TCK, PC1) Frequency (except PLD) Clock (TCK, PC1) High Time (except PLD) Clock (TCK, PC1) Time (except PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Time (PLD only) Port Time Port Hold Time Port Clock Output Port High-Impedance Valid Output Port Valid Output High-Impedance Conditions (Note (Note (Note (Note (Note (Note Unit
Note: non-PLD Programming, Erase by-pass mode. Program Erase only.
Figure Timing
ISCCH
ISCCL ISCPSU ISCPH
TDI/TMS
ISCPZV ISCPCO
OUTPUTS/TDO
ISCPVZ
OUTPUTS/TDO
AI02865
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DSM2190F4
PACKAGE MECHANICAL PLCC52 lead Plastic Leaded Chip Carrier, rectangular, Package Outline
D2/E2 D3/E3
PLCC-B
Note: Drawing scale.
PLCC52 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
Symbol 1.27 0.89 Typ. Min. 4.19 2.54 0.33 0.66 0.246 19.94 19.05 17.53 19.94 19.05 17.53 Max. 4.57 2.79 0.91 0.53 0.81 0.261 20.19 19.15 18.54 20.19 19.15 18.54 0.050 0.035 Typ. inches Min. 0.165 0.100 0.013 0.026 0.0097 0.785 0.750 0.690 0.785 0.750 0.690 Max. 0.180 0.110 0.036 0.021 0.032 0.0103 0.795 0.754 0.730 0.795 0.754 0.730
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DSM2190F4
Table Assignments PLCC52
Assignments (VSTBY) Assignments AD10 AD11 AD12 AD13 AD14 AD15 CNTL0 RESET CNTL2 CNTL1
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DSM2190F4
PQFP52 lead Plastic Quad Flatpack, Package Outline
Note: Drawing scale.
PQFP52 lead Plastic Quad Flatpack, Package Mechanical Data
Symb. 13.20 10.00 7.80 13.20 10.00 7.80 0.65 0.88 1.60 2.00 1.80 0.22 0.11 12.95 9.90 12.95 9.90 0.73 0.10 Typ. Min. Max. 2.35 0.25 2.10 0.38 0.23 13.45 10.10 13.45 10.10 1.03 0.520 0.394 0.307 0.520 0.394 0.307 0.026 0.035 0.063 0.004 0.029 0.041 0.079 0.077 0.009 0.004 0.510 0.390 0.510 0.390 Typ. inches Min. Max. 0.093 0.010 0.083 0.015 0.009 0.530 0.398 0.530 0.398
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DSM2190F4
Table Assignments PQFP52
Assignments Assignments AD10 AD11 AD12 AD13 AD14 AD15 CNTL0 RESET CNTL2 CNTL1
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DSM2190F4
PART NUMBERING Table Ordering Information Scheme
Example: DSM21
Device Type DSM21 System Memory ADSP-21XX Family Applicability Analog Devices ADSP-219X family
Memory Density 2Mbit (256K Bytes)
Operating Voltage (Vcc) 3.3V Access Time Package 52-pin PLCC 52-pin PQFP Temperature Range 85oC (Industrial)
list available options (speed, package, etc.) further information aspect
device, please contact your nearest Sales Office.
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REVISION HISTORY Table Document Revision History
Date 27-Aug-2001 06-Nov-2001 17-Dec-2001 18-Sep-2002 Rev. Document written Document released PQFP52 package mechanical data updated JTAG Debug separated from JTAG Description Revision
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Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics other names property their respective owners 2002 STMicroelectronics Rights Reserved STMicroelectronics group companies Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States. www.st.com
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