Dual Filter HSP43168 Dual Filter consists independent 8-tap filte

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Dual Filter HSP43168 Dual Filter consists independent 8-tap filte

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HSP43168
Dual Filter
HSP43168 Dual Filter consists independent 8-tap filters. Each filter supports decimation from provides on-board storage sets coefficients. Block Diagram shows cells each separate coefficient bank separate inputs. outputs cells either summed multiplexed MUX/Adder. compute power Cells configured provide quadrature filtering, complex filtering, convolution, 1-D/2-D correlations, interpolating/decimating filters. cells take advantage symmetry coefficients pre-adding data samples prior multiplication. This allows 8-tap implemented using only multipliers filter cell. These cells configured either single 16-tap filter dual 8-tap filters. Asymmetric filtering also supported. Decimation provided boost effective number filter taps from times. Further, decimation registers provide delay necessary fractional data conversion filtering with kernels 16x16. flexibility Dual further enhanced sets user programmable coefficients. Coefficient selection changed asynchronously from clock clock. ability toggle between coefficient sets further simplifies applications such polyphase adaptive filtering. HSP43168 power fully static design implemented advanced CMOS process. configuration device controlled through standard microprocessor interface.
December 1996
Features
Independent 8-Tap Filters Configurable Single 16-Tap 10-Bit Data Coefficients On-Board Storage Programmable Coefficient Sets Taps, Kernels, 19-Bit Data Coefficients Programmable Decimation Programmable Rounding Output Standard Microprocessor Interface
Applications
Quadrature, Complex Filtering Polyphase Filtering Image Processing Adaptive Filtering
Ordering Information
PART NUMBER HSP43168VC-33 HSP43168VC-40 HSP43168VC-45 HSP43168JC-33 HSP43168JC-40 HSP43168JC-45 HSP43168JI-40 HSP43168GC-33 HSP43168GC-45 TEMP. RANGE (oC) PACKAGE MQFP MQFP MQFP PLCC PLCC PLCC PLCC CPGA CPGA PKG. Q100.14x20 Q100.14x20 Q100.14x20 N84.1.15 N84.1.15 N84.1.15 N84.1.15 G84.A G84.A
Block Diagram
CIN0 CSEL0 CONTROL/ CONFIGURATION
COEFFICIENT BANK INA0 CELL
COEFFICIENT BANK
CELL
INB0 OUT0
ADDER OUT9
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
Harris Corporation 1996
File Number
2808.6
HSP43168 Pinouts
LEAD CPGA BOTTOM VIEW
RVRS CIN8 'A1' MUX1 CSEL2 CIN9 CIN7 CIN5
LEAD CPGA VIEW
INB1 INB4 INB5 INB6 INB9
CSEL1 CSEL3 CSEL4
OUT15 OUT14 OUT12
OUT10 OUT11
SHFTEN
MUX0
OUT18
OUT16 OUT13
INB0
INB2
INB7
INB8
INA1
TXFR
FWRD
CSEL0
CIN6
CIN4
OUT19
OUT17
OUT9
INB3
INA0
INA2
ACCEN
CIN3
OUT21
OUT20
INA3
INA4
CIN2
CIN1
CIN0
OUT24
OUT23 OUT25
INA7
INA5
INA6
OUT27 OUT22 OUT26
HSP43168 BOTTOM VIEW
INA8
INA9
OUT27
OUT22 OUT26
HSP43168 VIEW
INA8
INA9
OUT24 OUT23 OUT25
INA7
INA5
INA6
CIN2
CIN1
CIN0
OUT21 OUT20
INA3
INA4
ACCEN
CIN3
OUT19 OUT17
OUT9
INB3
INA0
INA2
TXFR
FWRD
CSEL0
CIN6
CIN4
OUT18
OUT16 OUT13
INB0
INB2
INB7
INB8
INA1
SHFTEN
MUX0
MUX1
CSEL2
CIN9
CIN7
CIN5
'A1'
OUT15 OUT14 OUT12 OUT10 OUT11
INB1
INB4
INB5
INB6
INB9
RVRS
CSEL1 CSEL3 CSEL4
CIN8
LEAD PLCC VIEW
CSEL CSEL CSEL CSEL CSEL
RVRS SHFTEN TXFR ACCEN
HSP43168 Pinouts
(Continued) LEAD MQFP VIEW
CIN9 CSEL4 CSEL3 CSEL2 CSEL1 CSEL0 CIN8 CIN7 CIN6 CIN5 CIN4 CIN3 CIN2 CIN1 CIN0 INA9 INA8 INA7 INA6 INA5 INA4 INA3 INA2 INA1 INA0 INB9 INB8 INB7 INB6 INB5 INB4 INB3 INB2 INB1 INB0 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 MUX1 MUX0 RVRS SHIFTEN TXFR ACCEN OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17
HSP43168 SYMBOL CIN0-9 A0-8 TYPE VCC: power supply pin. Ground. Control/Coefficient Data Bus. Processor interface loading control data coefficients. CIN0 LSB. Control/Coefficient Address Bus. Processor interface addressing control coefficient registers. LSB. Control/Coefficient Write Clock. Data latched into control coefficient registers rising edge Coefficient Select. This input determines which coefficient sets used This input registered CSEL0 LSB. Input INA0 LSB. Bidirectional Input INB0 input only. When used output, INB1-9 LSBs output bus, INB9 these bits. MSBs Output Bus. Data format either unsigned two's complement depending configuration. OUT27 MSB. Shift Enable. This active input enables clocking data into part shifting data through decimation registers. Forward Input Enable. When active low, data from forward decimation path input ALUs through input. When high, inputs ALUs zeroed. Reverse Input Enable. When active low, data from reverse decimation path input ALUs through input. When high, inputs ALUs zeroed. Data Transfer Control. This active input switches LIFO being read into reverse decimation path with LIFO being written from forward decimation path (see Figure Adder/Mux Control. This input controls data flow through output Adder/Mux. Table lists various configurations. Clock. inputs except those associated with processor interface (CIN0-9, A0-8, output enables (OEL, OEH) registered rising edge CLK. Output Enable Low. This three-state control enables LSBs output INB1-9 when low. Output Enable High. This three-state control enables OUT9-27 when low. Accumulate Enable. This active high input allows accumulation Cell Accumulator. this input latches Accumulator contents into Output Holding Registers while zeroing feedback pass Accumulator. DESCRIPTION
CSEL0-4
INA0-9 INB0-9
OUT9-27
SHFTEN
FWRD
RVRS
TXFR
MUX0-1
ACCEN
TXFR DELAY DELAY DELAY DATA FEEDBACK CIRCUITRY DATA FEEDBACK CIRCUITRY LIFO LIFO DELAY 1-16
DATA REVERSAL ENABLE
DELAY
REVERSE PATH DECIMATION REGISTERS DELAY 1-16 DELAY 1-16 DELAY 1-16 DELAY 1-16 DELAY 1-16 DELAY 1-16 DELAY 1-16 LIFO DECIMATION REGISTERS
ODD/EVEN TAPS
LIFO
ODD/EVEN SYMMETRY MODE SELECT
ODD/EVEN TAPS
ODD/EVEN
SYMMETRY
FORWARD PATH
SHFTEN
DELAY
DATA REVERSAL ENABLE
REVERSE PATH FORWARD PATH
INA0-9
DELAY 1-16 DELAY 1-16 DELAY 1-16
DELAY
DELAY 1-16
DELAY 1-16
DELAY 1-16
DELAY 1-16
DELAY
INB0
ODD/EVEN
SYMMETRY
ODD/EVEN
SYMMETRY
INB1-9/ OUT0-8
FWRD
DELAY
RVRS
DELAY
INPUT MODE SELECT
SOURCE
COEF BANK
COEF BANK
COEF BANK
COEF BANK
COEF BANK
COEF BANK
COEF BANK
COEF BANK
HSP43168
ACCUMULATOR ADDER OUTPUT HOLDING REGISTER
CSEL0-4
DELAY
ACCUMULATOR
ADDER
CELL
OUTPUT HOLDING REGISTER
CELL
ACCEN
DELAY
MUX0-1
DELAY
ROUND ENABLE
MUX/ ADDER
CIN0-9 CONTROL
A0-8
DELAY
MODE SELECT EVEN SYMMETRY ODD/EVEN TAPS ODD/EVEN TAPS INPUT SOURCE DATA REVERSAL ENABLE ROUND ENABLE DECIMATION FACTOR
OUT9-27
Processor control words Decimation factor
FIGURE DUAL FILTER
HSP43168 Functional shown Figure HSP43168 consists 4-multiplier filter cells which process 10-bit data coefficients. cells operate independent 8-tap filters 4-tap asymmetric filters maximum rates. single filter mode provided which allows cells operate 16-tap filter 8-tap asymmetric filter. board coefficient storage sets coefficients provided. coefficient sets user selectable programmed through microprocessor interface. Programmable decimation also provided. utilizing decimation registers together with coefficient sets, polyphase filters realizable which allow user trade data rate filter taps. MUX/Adder configured either multiplex outputs filter cells depending upon whether cells operating single dual filter mode. addition, shifter MUX/Adder provided implementation filters with 10-bit data 20-bit coefficients vice versa. Dual Filter "pipeline" delay periods, once normal filtering operations begin. Five typical filtering operation examples provided Applications Examples Section guide configuration control Dual Filter. During normal filter operations, location duration TXFR signal assertions determined filter configuration operation mode. Once set, these signal parameters must maintained during normal operation ensure proper data alignment part.
NOTE: fixed periodic relationship between TXFR signal must maintained valid filter operation. This relationship only change when halted configuration control words loaded into device.
Microprocessor Interface
Dual write only microprocessor interface loading data into Control Block Coefficient Banks. interface consists 10-bit data (CIN0-9), 9-bit address (A0-8), write input (WR) latch data into on-board registers rising edge. configuration control coefficient data loading asynchronous CLK.
Preparing Dual Operation
configuration steps required prepare Dual Filter normal operation: loading Configuration Control Registers, loading Filter Coefficients. Configuration Control Registers loaded placing control register address address lines A0-8, placing configuration data configuration input lines CIN0-9, asserting line (followed release assertion). This action creates rising edge line, which clocks address configuration data into part. details "Load Configuration" process outlined Microprocessor Interface Section. Coefficients loaded placing address Coefficient Data Bank address lines A0-8, placing coefficient values configuration input lines CIN0-9 then asserting line (followed release assertion). This action creates rising edge line, which clocks Coefficient Band address Coefficient data into part. details "Load Coefficient" process outlined Filter Cells Section, Coefficient Bank Subsection. Both Configuration Load Coefficient Load done sequence asynchronous write commands Dual Filter. Once these actions complete, part ready normal filter operation. CLK, TXFR, FWRD, RVRS, ACCEN, SHFTEN signals must asserted manner determined application. MUX0-1 must meet setup hold times with respect clock proper filter operation. Details MUX1-0 control found Output MUX/Adder Section. Details ACCEN control found Cell Accumulator Section. locations various filter control/configuration signals found Input/Output Formats Section.
Control Block
Dual configured writing registers within Control Block. Figure shows timing diagram writing configuration control registers. These control registers memory mapped address 000H Hexadecimal) 001H A0-8. filter coefficient registers mapped 1XXH value described "Coefficient Banks" chapter Section).
RESET
A8-0 000H 001H
C9-0
FIGURE LATCHING C9-0 VALUES INTO ADDRESS A8-0 REGISTERS
format control registers shown Table Table Writing Control/Configuration registers causes reset which lasts cycles following assertion reset caused writing registers Control Block will clear contents Coefficient Bank. shown Figure either configuration control register written during reset.
HSP43168
TABLE CONFIGURATION/CONTROL WORD DEFINITIONS CONTROL ADDRESS 000H BITS FUNCTION Decimation Factor DESCRIPTION 0000 Decimation 1111 Decimation Single Filter Mode Dual Filter Mode
Mode Select
Odd/Even Filter Coef- Even symmetric coefficients ficient Symmetry symmetric coefficients Odd/Even Number Taps Odd/Even Number Taps Input Source number taps filter Even number taps filter (Defined same above)
Filter separate independent filters. single filter mode, data routed through forward paths Filters before entering reverse paths Filters (see Figure Coefficient symmetry selected Bits programmed configure cells even filter lengths (number taps). selects input source when cells configured independent operation. must programmed NOTE: When filter programmed even-taps, TXFR signal delayed only three CLKS (see Figure odd-taps, TXFR signal delayed four CLKS. LSBs control word loaded address 001H used configure format cell's data coefficients. programmed enable disable reversal data sample order prior entering reverse path decimation registers. Data reversal required symmetric filter coefficient sets both even numbers filter taps. Asymmetric filters some decimated symmetric filters require data reversal off. Bits used support programmable rounding output.
Input from INA0-9 Input from INB0-9 proper operation
Used
NOTE: Address locations 002H 011H reserved, writing these locations will have unpredictable effects part configuration. TABLE CONFIGURATION/CONTROL WORD DEFINITIONS CONTROL ADDRESS 001H BITS FUNCTION Input Format DESCRIPTION Unsigned Two's Complement
Filter Cells
Each filter cell based array four 11x10-bit two's complement multipliers. input multipliers comes from ALU's which combine data shifting through forward reverse decimation registers. second multiplier input comes from user programmable coefficient bank. multiplier outputs accumulator whose result passed output section where multiplexed added with result from other cell. Decimation Registers forward reverse decimation shift registers configured decimation factors from (see Table bits 0-3). NOTE: Setting decimation factor only affects delay registers between filter taps, filter control multiplexers. Example Example Applications Section discuss configure part actual decimation applications. reverse shifting registers with data reversal logic used take advantage symmetry linear phase filters aligning data ALUs pre-addition prior multiplication common coefficient. When cells configured single filter mode, decimation registers cell cell cascaded. This extended filter delay path allows computation filter which twice size that capable using single cell. decimation registers also provide data storage poly-phase filtering applications (See Applications Examples section). Data Feedback Circuitry each cell responsible transferring data from forward reverse shifting decimation registers. This circuitry feeds blocks samples into reverse shifting decimation path either reversed non-reversed sample order. MUX/DEMUX structure input Feedback Circuitry routes data LIFOs delay stage depending selected configuration. Feedback Circuitry Output selects which storage element feeds reverse shifting decimation registers.
Coefficient Format (Defined same input) Input Format Coefficient Data Reversal Enable (Defined same input) (Defined same input) Enabled Disabled 0000 2-10 1011 Enabled Disabled
Round Position
Round Enable
NOTE: Address locations 002H 011H reserved, writing these locations will have unpredictable effects part configuration.
LSBs control word loaded address 000H used select decimation factor. Decimation Factor programmed less than number delays between filter taps
delays between taps (EQ.
example, LSBs programmed with value 0010, forward reverse shifting decimation registers each configured with delay used select whether cells operate independent filters extended length filter. Dual filter mode assumes Filter
HSP43168
applications requiring reversal sample order, cells configured with data reversal enabled (see Table CW5, this mode, data transferred from forward backward shifting registers through pingponged LIFO structure. While LIFO being read into backward shifting path, other LIFO written with data samples. MUX/DEMUX controls which LIFO being written, Feedback Circuitry output controls which LIFO being read. TXFR SHIFTEN, switches LIFOs being read written, which causes block data read from structure reversed sample order (See Example Application Examples section). frequency with which TXFR asserted determines size data blocks which sample order reversed. example, TXFR asserted once every three CLKs, blocks data samples with order reversed, would into backward decimation registers. NOTE: Altering frequency phase TXFR assertion once filtering operation begun will invalidate filtering result. applications which require sample order reversal, cells must configured with data reversal disabled (see Table CW5, addition, TXFR must asserted ensure proper data flow. this configuration, data backward shifting decimation path routed though delay stage instead ping-pong LIFOs. number registers delay stage based programmed decimation factor. NOTE: Data reversal must disabled TXFR must asserted filtering applications which decimation. shifting data through forward reverse decimation registers enabled asserting SHFTEN input. When SHFTEN high, data shifting disabled, data sample latched into part previous clock last input filter structure. data sample filter input when SHFTEN asserted, will next data sample into forward decimation path. When operating cells independent filters, receives input data INA0-9 receives data from either INA0-9 INB0-9 depending application (see Table When cells configured single extended length filter, forward reverse decimation paths cells cascaded. this mode, data transferred from forward decimation path reverse decimation path Data Feedback Circuitry Thus, manner which data read into reverse decimation path determined configuration. When decimation paths cascaded, data routed through fourth delay stage forward path configuration cells even length filters determines point forward decimation path from which data multiplexed Data Feedback Circuitry. example, cell configured length filter, data prior last register third forward decimation stage routed Feedback Circuitry. cell configured even length filter, data output from third forward decimation stage multiplexed Feedback Circuitry. This required insure proper data alignment with symmetric filter coefficients (See Application Examples).
ALUs
Data shifting through forward reverse decimation paths feed inputs ALUs respectively. ALUs perform "b+a" operation cell configured even symmetric coefficients "b-a" operation configured symmetric coefficients. Control Word used operation. applications which pre-add subtract required, input zeroed disabling FWRD RVRS respectively. This effect producing output which either "a", "-a", depending filter symmetry chosen. example, cell configured even symmetric filter with FWRD RVRS high, data shifting through forward decimation registers would appear output. Coefficient Bank output multiplied coefficient from user programmable coefficient sets. Each consists coefficients coefficients CSEL0-4 used select coefficient used. Coefficient sets switched every clock support polyphase filtering operations. coefficients loaded into on-board registers using microprocessor interface, CIN0-9, A0-8, Each multiplier within Cells driven coefficient bank with coefficients. These coefficients addressed shown Table inputs A0-1 specify Coefficient Bank four multipliers each Cell; specifies Cell Bits A7-3 specify sets which coefficient stored. example, address 10dH would access coefficient second multiplier second coefficient set.
TABLE COEFFICIENT WRITE ADDRESSES COEFF. COEFF. A7-3 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx CELL MULTIPLIER A1-0 DESTINATION BANK
HSP43168 Cell Accumulator
registered outputs from multipliers each cell feed accumulator. ACCEN input controls each accumulator's running latching data from accumulator into Output Holding Registers. When ACCEN low, feedback from accumulator adder zeroed which disables accumulation. Also, output from accumulator latched into Output Holding Registers. When ACCEN asserted, accumulation enabled contents Output Holding Registers remain unchanged.
.2-1 INPUT DATA FORMAT INA0-9, INB0-9 FRACTIONAL TWO'S COMPLEMENT
OUTPUT DATA FORMAT OUT9-27 FRACTIONAL TWO'S COMPLEMENT .2-1 OUTPUT DATA FORMAT OUT0-8 FRACTIONAL TWO'S COMPLEMENT 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18
Output MUX/Adder
contents each Cell's Output Holding Register summed multiplexed Mux/Adder. operation Mux/Adder controlled MUX1-0 inputs shown Table Applications requiring 10-bit data 20-bit coefficients 20-bit data 10-bit coefficients made possible configuring MUX/Adder scale output 2-10 prior summing with When Dual configured independent filters, MUX1-0 inputs would used multiplex filter outputs each cell. applications which configured single filter, MUX/Adder configured output each cell.
TABLE MUX1-0 DEFINITIONS MUX1-0 DECODING MUX1-0 OUT0-27 FIRA FIRB (FIR Scaled 2-10) FIRA FIRB FIRA FIRB
INPUT DATA FORMAT INA0-9, INB0-9 FRACTIONAL UNSIGNED .2-1
OUTPUT DATA FORMAT OUT9-27 FRACTIONAL UNSIGNED .2-1 OUTPUT DATA FORMAT OUT0-8 FRACTIONAL UNSIGNED 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18
FIGURE INPUT/OUTPUT FORMAT DEFINITIONS
Input/Output Formats
Dual supports mixed mode arithmetic with both unsigned two's complement data coefficients. input output formats both data types shown below. Dual configured even symmetric filter with unsigned data coefficients, output will unsigned. Otherwise, output will two's complement. MUX/Adder configured implement programmable rounding locations 2-10 through round implemented adding specified location (see Table Figure illustrates rounding operation. example, configure part such that output rounded MSBs, OUT18 round position would chosen 2-1. negative sign indicates complement format.
IOUT 9-27 IOUT
2-10
1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 "ROUND POSITION" VALUE
NUMBER OUTPUT BITS LOCATION ADDITION OUTPUT BITS
FIGURE ROUND POSITION DEFINITION
HSP43168 Application Examples
this section number examples presented which detail even, odd, symmetric, asymmetric, decimating dual filter configurations. These examples intended illustrate different operational features HSP43168 should used guide developing application specific filter configuration. Table select find example that best matches your application.
TABLE FILTER EXAMPLE SELECTION GUIDE FILTER TYPE Even Even Symmetric Even Symmetric Asymmetric Even Decimating Decimating Dual Decimating EXAMPLE NUMBER
INA0-9 8-TAP EVEN SYMMETRIC INB0-9 OUT9-27 HSP43168 8-TAP EVEN SYMMETRIC
FIGURE USING HSP43168 INDEPENDENT FILTERS
operation cell better understood comparing data coefficient alignment given filter output, Figure with data flow through cell, shown Figure block diagrams Figure simplification cell shown Figure simplicity, ALUs Cell Accumulators were replaced adders, pipeline delay registers were omitted. this example, will only show data flow through cells.
h(n) TAPS
Examples explained using single four cell, same concept applies filters which both cells single filter configuration. Example details dual filter mode where cell implement different digital filters. Examples functionally verified configurations. Each example details complete design solution, including block diagram, data/coefficient alignment illustration, data flow diagram control signal timing diagram. programmable configuration control registers define unique filter configuration. Register 000H filter configuration unique parameters, while register 001H, filter configuration unique. Table details configuration control register values, number filter coefficient banks required MUX1-0 control values each filter example.
TABLE CONFIGURATION CONTROL REGISTER VALUES FILTER COEFFICIENT BANKS
x(n)
FIGURE DATA/COEFFICIENT ALIGNMENT 8-TAP EVEN SYMMETRIC FILTER
FILTER TYPE Even Even Symmetric Even Symmetric Asymmetric Even Decimate Decimate Dual: Even Decimate
Figure order data samples within filter cell shown numbers forward backward shifting decimation paths. output filter cell given equation bottom each block diagram. Figure shows data sample alignment pre-adders data/coefficient alignment shown Figure dual filter application configured writing 1d0H address 000H microprocessor interface, CIN0-9, A0-8, Since this application does decimation, control register address 001H must disable data reversal (see Table Failure disable data reversal will produce erroneous results. Using this architecture, only unique coefficients need stored Coefficient Bank. example, above filter would stored first coefficient writing address 100H, 101H, 102H, 103H respectively. write same filter first coefficient address sequence would change 104H, 105H, 106H, 107H. operate HSP43168 this mode, TXFR tied ensure proper data flow; both FWRD RVRS tied enable data samples from forward reverse data paths ALUs pre-adding; ACCEN tied prevent accumulation over multiple CLKs; SHFTEN tied
Example Even-Tap Even Symmetric Filter Example HSP43168 configured independent 8-tap symmetric filters shown block diagram Figure Each cells takes advantage symmetric filter coefficients pre-adding data samples common given coefficient. result, each cell implement 8-tap symmetric filter using only four multipliers. Similarly, when HSP43168 configured single filter mode 16-tap symmetric filter possible using multipliers both cells.
HSP43168
allow shifting data through decimation registers; MUX0-1 programmed multiplex output either CSEL0-4 programmable access stored coefficient set, this example CSEL 00000. Example Odd-Tap Even Symmetric Filter Example HSP43168 configured independent 7-tap symmetric filters with functional block diagram shown Figure Again, this example shows data flow through cells. 8-tap filter example, HSP43168 implements filtering operation summing data samples sharing common coefficient prior multiplication that coefficient. However, length filters pre-addition requires that center coefficient scaled 1/2.
HSP43168 7-TAP EVEN SYMMETRIC INA0-9 7-TAP EVEN SYMMETRIC OUT9-27
INB0-9
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE FIGURE USING HSP43168 INDEPENDENT FILTERS
operation cell length filters better understood comparing data/coefficient alignment Figure with data flow diagrams Figure block diagrams Figure simplification cell shown Figure
h(n) 7-TAPS
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
x(n)
FIGURE DATA/COEFFICIENT ALIGNMENT 7-TAP SYMMETRIC FILTER
length filters, proper data/coefficient alignment ensured routing data entering last register third forward decimation stage backward shifting registers. this configuration, center coefficient must scaled compensate summation same data sample from both forward backward shifting registers.
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE FIGURE DATA FLOW DIAGRAMS 8-TAP SYMMETRIC FILTER
HSP43168
C3/2
Also, data reversal must disabled setting control register address 0001H. 8-tap example, only unique coefficients need stored Coefficient Bank. These coefficients stored first coefficient writing address 100H, 101H, 102H, 103H respectively. write same filter first coefficient address sequence would change 104H, 105H, 106H, 107H. control signals TXFR, FWRD, RVRS, ACCEN, SHFTEN, CSEL0-4 controlled described Example Example Asymmetric Filter Example cells within HSP43168 each calculate asymmetric taps each clock. Thus, single cell implement 8-tap asymmetric filter HSP43168 clocked twice input data rate. Similarly, Dual configured single filter, 16-tap asymmetric filter realizable. Only cells used this example block diagram shown Figure this example, cells configured 8-tap asymmetric filters which clocked twice input data rate. data shifted into forward backward decimation paths every other assertion SHFTEN. filter output computed passing data from each decimation path multipliers alternating clocks. sets coefficients required, data forward decimation path, data reverse path. filter output generated accumulating multiplier outputs CLKs.
HSP43168 8-TAP ASYMMETRIC
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
C3/2
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
INA0-9
8-TAP ASYMMETRIC INB0-9
OUT9-27
C3/2
FIGURE USING HSP43168 INDEPENDENT FILTERS
DATA FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE FIGURE DATA FLOW DIAGRAMS 7-TAP SYMMETRIC FILTER
operation this configuration better understood comparing data/coefficient alignment Figure with data flow diagrams Figure ALUs have been omitted from cell diagrams because data multipliers directly from forward reverse decimation paths. data samples within cell shown numbers decimation paths.
h(n) 8-TAPS
data flow diagrams Figure order data samples input filter cell shown numbers forward backward shifting decimation paths. output filter cell given equation bottom block. diagram Figure shows data sample alignment pre-adders data/coefficient alignment shown Figure This dual filter application configured writing 110H address 000H microprocessor interface, CIN0-9, A0-8,
x(n)
FIGURE DATA/COEFFICIENT ALIGNMENT 8-TAP ASYMMETRIC FILTER
HSP43168
ACCUMULATOR
ACCUMULATOR
(X0)C0+(X1)C1+(X2)C2+(X3)C3
(X0)C0+(X1)C1+(X2)C2+(X3)C3 +(X7)C7+(X6)C6+(X5)C5+(X4)C4
DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS
SHIFTING DATA SAMPLE INTO CELL ENABLED, FORWARD SHIFTING REGISTERS FEEDING MULTIPLIERS
ACCUMULATOR
ACCUMULATOR
(X1)C0+(X2)C1+(X3)C2+(X4)C3
(X1)C0+(X2)C1+(X3)C2+(X4)C3 +(X8)C7+(X7)C6+(X6)C5+(X5)C4
DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS
SHIFTING DATA SAMPLE INTO CELL ENABLED, FORWARD SHIFTING REGISTERS FEEDING MULTIPLIERS
FIGURE DATA FLOW DIAGRAMS 8-TAP ASYMMETRIC FILTER
this application, each filter cell configured length filter writing 110H control register address 000H. Even though even filter being implemented, filter cells must configured length ensure proper data flow. addition, filters must even symmetry. Also, control address 001H must enable data reversal, TXFR must tied low. Since 8-tap asymmetric filter being implemented, sets coefficients must stored. These eight coefficients could loaded into first coefficient sets writing address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH respectively. products required this 8-tap filter require dynamic control over FWRD, RVRS, ACCEN, CSEL0-4. relative timing these signals shown Figure
INA0-9 CSEL0-4
ACCEN FWRD RVRS SHFTEN TXFR (TIED LOW)
Note that data rate. FIGURE CONTROL TIMING 8-TAP ASYMMETRIC FILTER
HSP43168
Example Even-Tap Decimating Filter Example HSP43168 supports filtering applications requiring decimation these applications output data rate reduced factor result, clock cycles used computation filter output. example, each cell calculate symmetric asymmetric taps clock. application requires decimation two, filter output calculated over clocks thus boosting number taps cell symmetric asymmetric. this example, each cell configured independent 24-tap decimate filter. Again, data flow diagrams show only cells shown Figure
HSP43168 EVEN-TAP DECIMATING INA0-9 EVEN-TAP DECIMATING INB0-9
x(n)
alignment data relative filter coefficients particular output depicted graphically Figure previous examples, HSP43168 implements filtering operation summing data samples prior multiplication common coefficient. this example output required every third which allows CLKs computation. each CLK, three sets coefficients used calculate filter taps. block diagrams Figure show data flow accumulator output data/coefficient alignment Figure
C11C11 24-TAPS
h(n)
OUT9-27
FIGURE EVEN-TAP DECIMATING FILTER, 24-TAP
FIGURE DATA/COEFFICIENT ALIGNMENT 24-TAP DECIMATE FILTER
CSEL
CSEL
ACCUMULATOR
ACCUMULATOR
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
CSEL ACCEN ASSERTED ACTIVE
CSEL
ACCUMULATOR
TXFR ASSERTED ACTIVE
ACCUMULATOR
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
FIGURE DATA FLOW DIAGRAMS 24-TAP DECIMATE FILTER
HSP43168
Proper data coefficient alignment achieved asserting TXFR once every three CLKs switch LIFOs which being read written. This effect feeding blocks three samples into backward shifting decimation path which reversed sample order. addition, ACCEN deasserted once every three clocks allow accumulation over three CLKs. three sets coefficients required calculation 24-tap symmetric filter cycled through using CSEL0-4. timing relationship between CSEL04, ACCEN, TXFR shown Figure
INA0-9 INA0-9 ODD-TAP DECIMATING INB0-9
Example Odd-Tap Decimating Symmetric Filter This example highlights HSP43168 independent, 23-tap, symmetric, decimate filters. this example, operational differences control signals data reversal structure compared previously discussed even-tap decimating filter. Figure shows cells. data flow this example uses only cells.
HSP43168 ODD-TAP DECIMATING OUT9-27
CSEL0-4
ACCEN FWRD RVRS SHIFTEN TXFR
FIGURE USING HSP43168 INDEPENDENT FILTERS
Tied low. FIGURE CONTROL SIGNAL TIMING 24-TAP DECIMATE FILTER
24-tap example, output required every third which allows CLKs computation. each CLK, three sets coefficients used calculate filter taps. Since this length filter, center coefficient must scaled compensate summation same data sample from forward backward shifting decimation paths. block diagrams Figure show data flow, accumulator output data coefficient alignment shown Figure Proper data coefficient alignment achieved asserting TXFR once every three CLKs switch LIFOs which being read written. odd-tap mode, TXFR internally delayed clock cycle with respect ACCEN that convolutional will computed correctly. length filters, data prior last register forward decimation path routed Feedback Circuitry. result, TXFR should asserted cycle prior input data samples which align with center tap. timing relationship between CSEL0-5, ACCEN, TXFR shown Figure
operate this mode Dual configured writing address 000H microprocessor interface, CIN0-9, A0-8, Data reversal must enabled (Table unique coefficients this example stored three sets coefficients either cell. coefficients loaded into Coefficient Bank writing C11, C10, address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH, 110H, 111H, 112H, 113H, respectively.
C11/2
CSEL
CSEL
ACCUMULATOR
ACCUMULATOR
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE TXFR TAKES AFFECT THIS CLOCK CYCLE
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
FIGURE DATA FLOW DIAGRAMS 23-TAP DECIMATE SYMMETRIC FILTER
HSP43168
CSEL ACCEN ASSERTED ACTIVE TXFR ASSERTED
C11/2
CSEL
ACCUMULATOR
ACCUMULATOR
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE TXFR TAKES AFFECT THIS CLOCK CYCLE
FIGURE DATA FLOW DIAGRAMS 23-TAP DECIMATE SYMMETRIC FILTER (Continued)
h(n)
C9C10 C10C9
23-TAPS
(C11)/ C10, address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH, 110H, 111H, 112H, 113H, respectively. Example Dual Decimation Example purpose this example give overview more complex applications HSP43168. input data streams samples. Figure shows upper level block diagram system being implemented. decimation rate loaded into decimation factor control word 000H.
/(N+1) INB0-9 HSP43168 INA0-9 DECIMATE OUT9-27 BOUT1 AOUT1 BOUT0 AOUT0
x(n)
FIGURE DATA/COEFFICIENT ALIGNMENT 23-TAP DECIMATE SYMMETRIC FILTER
INA0-9
FIGURE MULTIPLEXED DECIMATION BLOCK DIAGRAM
CSEL0-4
ACCEN FWRD RVRS SHIFTEN TXFR
demonstrate muxed decimation, lets suppose that application requires filter configured even-decimate-by-3 filter filter configured odd-decimate-by-3 filter. output data made decimated data streams multiplexed together data rate equal times input sampling rate divided decimation factor. Figure shows data/coefficient alignment operate this mode, control word 000H must written with 0x152. Data reversal must enabled setting control word 001H filter selected CSEL0-4 should loaded writing C11, (D11)/ into 100H, 101H, 102H, 103H, 104H, 105H, 106H, 107H. filter selected CSEL0-4 should loaded writing C10, into 108H, 109H, 10aH, 10bH, 10cH, 10dH, 10eH, 10fH. filter selected CSEL0-4 should loaded writing into 110H, 111H, 112H, 113H, 114H, 115H, 116H, 117H.
Tied low. FIGURE CONTROL SIGNAL TIMING 23-TAP SYMMETRIC FILTER
operate this mode, Dual configured writing 112H address 000H microprocessor interface, CIN0-9, A0-8, Data reversal must enabled (see Table unique coefficients this example stored three sets coefficients either cell. coefficients loaded into Coefficient Bank writ-
HSP43168
23-TAPS FIRB h2(n)
Figure shows timing diagram required obtained multiplexed/decimated output. output filters provided selecting odd-decimation filter first, then even-decimation second using MUX0-1. Figure shows data flow diagram multiplexed decimation example.
B(n)
INA0-9 CSEL0-4
h1(n)
FIRA
24-TAPS
ACCEN MUX0-1
A(n)
TXFR
FIGURE DATA/COEFFICIENT ALIGNMENT MULTIPLEXED DECIMATION EXAMPLE
FIGURE TIMING DIAGRAM MULTIPLEXED DECIMATION EXAMPLE
DATA STREAM
CSEL
D11/2
CSEL
ACCUMULATOR ACCUMULATOR
DATA STREAM
CSEL
CSEL
ACCUMULATOR
ACCUMULATOR
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
FIGURE DATA FLOW DIAGRAM MULTIPLEXED DECIMATION EXAMPLE
HSP43168
CSEL
D11/2
CSEL
ACCUMULATOR
OUTPUT SENT OUT9-27
ACCUMULATOR
CSEL
CSEL
ACCUMULATOR
ACCUMULATOR
OUTPUT SENT OUT9-27
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
COMPUTATIONAL FLOW DATA SAMPLE CLOCKED INTO FEED FORWARD STAGE
FIGURE DATA FLOW DIAGRAM MULTIPLEXED DECIMATION EXAMPLE (Continued)
HSP43168
Absolute Maximum Ratings
Supply Voltage +8.0V Input, Output Voltage -0.5V +0.5V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) MQFP Package 33.0 PLCC Package 22.0 CPGA Package Maximum Junction Temperature CPGA Package 175oC MQFP PLCC Packages 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (MQFP PLCC Leads Tips Only)
Operating Conditions
Voltage Range Temperature Range, Commercial. .0oC 70oC Temperature Range, Industrial -40oC
Characteristics
Back Side Potential. Number Transistors Gates 32529
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Power Supply Current SYMBOL ICCOP TEST CONDITIONS Frequency 33MHz Notes Max, Outputs Loaded Max, Input Max, Input -400µA, 2mA, Frequency 1MHz measurements referenced GND. +25oC, Note UNITS
Standby Power Supply Current Input Leakage Current Output Leakage Current Logical Input Voltage Logical Zero Input Voltage Logical Output Voltage Logical Zero Output Voltage Clock Input High Clock Input Input Capacitance Output Capacitance
ICCSB VIHC VILC COUT
NOTES: Controlled design process parameters directly tested. Characterized upon initial design after major process and/or changes. Power Supply current proportional operating frequency. Typical rating ICCOP 11mA/MHz. Output load test load circuit 40pF. Maximum junction temperature must considered when operating part high clock frequencies.
HSP43168
Electrical Specifications
+4.75V +5.25V, 70oC Commercial, -40oC 85oC Industrial (Note (33MHz) PARAMETER Period High Period High Setup Time A0-8 Going Hold Time A0-8 from Going High Setup Time CIN0-9 Going High Hold Time CIN0-9 from Going High Setup Time Setup Time CIN0-9 Setup Time CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, INA0-9, INB0-9, ACCEN, MUX0-1 Going High Hold Time CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, INA0-9, INB0-9, ACCEN, MUX0-1 Going High Output Delay OUT0-27 Output Enable Time Output Disable Time Output Rise, Fall Time NOTES: tests performed with 40pF, 2mA, -400µA. Input reference level 2.0V. Input reference level other inputs 1.5V. Test 3.0V, VIHC 4.0V, VILC Setup time requirement loading data CIN0-9 guarantee recognition following clock. Controlled design process parameters directly tested. Characterized upon initial design after major process and/or changes. SYMBOL tAWS tAWH tCWS tCWH tWLCL tCVCL tECS Note Note NOTES (40.8MHz) 24.5 24.5 (45MHz) UNITS
tECH
Note Note
Test Load Circuit
(NOTE)
SWITCH OPEN ICCSB ICCOP
1.5V
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
HSP43168 Waveforms
CSEL0 MUX0 SHFTEN, FWRD RVRS, TXFR INA0 INB0 ACCEN OUT0
tECS
tECH
tWLCL
tAWS
tAWH
tCWS CIN0
tCWH
tCVCL
OEL,
1.5V
1.5V 1.7V 1.3V
OUT0 HIGH IMPEDANCE
HIGH IMPEDANCE
FIGURE OUTPUT ENABLE, DISABLE TIMING
2.0V 0.8V
2.0V 0.8V
FIGURE OUTPUT RISE FALL TIMES
HSP43168 Ceramic Grid Array Packages (CPGA)
G84.A MIL-STD-1835 CMGA3-P84C (P-AC)
LEAD CERAMIC GRID ARRAY PACKAGE INCHES SYMBOL
MILLIMETERS 5.46 1.78 0.41 0.41 1.07 28.96 8.76 3.68 0.55 0.51 1.47 2.03 29.97 NOTES
0.215 0.070 0.016 0.016 0.042 1.140
0.345 0.145 0.0215 0.020 0.058 0.080 1.180
1.000 1.140 1.180
25.4 28.96 29.97
1.000 0.100 0.008 0.120 0.040 0.140 0.060
25.4 2.54 0.20 3.05 1.02 3.56 1.52
INDEX CORNER NOTE NOTE
0.000 0.003
0.00 0.08
Rev. 6/28/95
SECTION 0.008 SEATING PLANE STANDOFF
NOTES: represents maximum matrix size. represents maximum allowable number pins. Number pins location pins within matrix shown pinout listing this data sheet. Dimension "A1" includes package body both cavity-up cavity-down configurations. This package cavity Dimension "A1" does include heatsinks other attached features. Standoffs intrinsic shall located matrix diagonals. seating plane defined standoffs dimensions Dimension applies cavity-up configurations only. pins shall 0.100 inch grid. Datum plane package interface both cavity down configurations. diameter includes solder custom finishes. tips shall have radius chamfer. Corner shape (chamfer, notch, radius, etc.) vary from that shown drawing. index corner shall clearly unique. Dimension measured with respect datums Dimensioning tolerancing ANSI Y14.5M-1982. Controlling dimension: INCH.
SECTION
HSP43168 Metric Plastic Quad Flatpack Packages (MQFP)
Q100.14x20 (JEDEC MO-108CC-1 ISSUE LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
INCHES SYMBOL 0.010 0.100 0.009 0.009 0.904 0.783 0.667 0.547 0.026 0.026 0.134 0.120 0.015 0.013 0.923 0.791 0.687 0.555 0.037 MILLIMETERS 0.25 2.55 0.22 0.22 22.95 19.90 16.95 13.90 0.65 0.65 3.40 3.05 0.38 0.33 23.45 20.10 17.45 14.10 0.95 NOTES Rev. 1/94 NOTES: Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact. dimensions tolerances ANSI Y14.5M-1982. Dimensions determined seating plane Dimensions determined datum plane Dimensions include mold protrusion. Allowable protrusion 0.25mm (0.010 inch) side. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08mm (0.003 inch) total. number terminal positions.
SEATING PLANE 0.10 0.004 0.40 0.016 0o-7o 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING 5o-16o 0.12 0.005
5o-16o
0.13/0.23 0.005/0.009
HSP43168 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) 0.004 (0.10)
N84.1.15 (JEDEC MS-018AF ISSUE LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES SYMBOL 0.165 0.090 1.185 1.150 0.541 1.185 1.150 0.541 0.180 0.120 1.195 1.158 0.569 1.195 1.158 0.569 MILLIMETERS 4.20 2.29 30.10 29.21 13.75 30.10 29.21 13.75 4.57 3.04 30.35 29.41 14.45 30.35 29.41 14.45 NOTES Rev. 3/95
0.025 (0.64) 0.045 (1.14)
D2/E2
D2/E2 VIEW
0.020 (0.51) PLCS
0.020 (0.51)
SEATING PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14)
0.025 (0.64) VIEW TYP.
NOTES: Controlling dimension: INCH. Converted millimeter dimensions necessarily exact. Dimensions tolerancing ANSI Y14.5M-1982. Dimensions include mold protrusions. Allowable mold protrusion 0.010 inch (0.25mm) side. measured seating plane contact point. Centerline determined where center leads exit plastic body. number terminal positions.
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Dual Filter HSP43168 Dual Filter consists independent 8-tap filte

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