Mbit (512K x8), Asynchronous SRAM FEATURES SUMMARY SUPPLY VOLTAGE
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M68AF511A
Mbit (512K x8), Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 5.5V
Figure Packages
512K bits SRAM with OUTPUT ENABLE EQUAL CYCLE ACCESS TIMES: 55ns STANDBY CURRENT DATA RETENTION: TRI-STATE COMMON ACTIVE STANDBY POWER
TSOP32 Type (NC)
SO32 (MC)
October 2002
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M68AF511A
TABLE CONTENTS SUMMARY DESCRIPTION Figure Logic Diagram Table Signal Names Figure TSOP Connections Figure Block Diagram
MAXIMUM RATING. Table Absolute Maximum Ratings PARAMETERS. Table Operating Measurement Conditions Figure Measurement Waveform Figure Measurement Load Circuit Table Capacitance. Table Characteristics. OPERATION Table Operating Modes Read Mode Figure Address Controlled, Read Mode Waveforms Figure Chip Enable Output Enable Controlled, Read Mode Waveforms. Table Read Standby Mode Characteristics Write Mode Figure Write Enable Controlled, Write Waveforms Figure Chip Enable Controlled, Write Waveforms Table Write Mode Characteristics Table Data Retention Characteristics. PACKAGE MECHANICAL TSOP Type lead Plastic Thin Small Outline Type Package Outline TSOP Type lead Plastic Thin Small Outline Type Package Mechanical Data SO32 lead Plastic Small Outline, Package Outline SO32 lead Plastic Small Outline, Package Mechanical Data. PART NUMBERING Table Ordering Information Scheme REVISION HISTORY Table Document Revision History
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M68AF511A
SUMMARY DESCRIPTION M68AF511A Mbit (4,194,304 bit) CMOS SRAM, organized 524,288 words bits. device features fully static operation requiring external clocks timing strobes, with equal address access cycle times. requires single 5.5V supply.
This device automatic power-down feature, reducing power consumption over when deselected. M68AF511A available lead TSOP Type lead packages.
Figure Logic Diagram
Table Signal Names
A0-A18 DQ0-DQ7 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Supply Voltage Ground
A0-A18
DQ0-DQ7
M68AF511A
AI03948C
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Figure TSOP Connections
M68AF511A
AI03949C
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M68AF511A
Figure Block Diagram
DECODER MEMORY ARRAY
CIRCUITS COLUMN DECODER
AI05916
MAXIMUM RATING Stressing device above rating listed Absolute Maximum Ratings table cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification imTable Absolute Maximum Ratings
Symbol TSTG Output Current Ambient Operating Temperature Storage Temperature Supply Voltage Input Output Voltage Power Dissipation Parameter
plied. Exposure Absolute Maximum Rating conditions periods greater than affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents.
Value -0.5 -0.5 +0.5
Unit
Note: output time, exceed second duration. maximum operating 6.0V only.
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M68AF511A
PARAMETERS This section summarizes operating measurement conditions, well characteristics device. parameters following Characteristic tables derived from tests performed under Measure-
ment Conditions listed relevant tables. Designers should check that operating conditions their projects match measurement conditions when using quoted parameters.
Table Operating Measurement Conditions
Parameter Supply Voltage Range Commercial Ambient Operating Temperature Range Industrial Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages Output Transition Timing Ref. Voltages 85°C 100pF 3.0k 3.1k 1ns/V VCC/2 0.3VCC; 0.7VCC M68AF511A 5.5V 70°C
Figure Measurement Waveform
Figure Measurement Load Circuit
Timing Reference Voltage VCC/2 DEVICE UNDER TEST Output Transition Timing Reference Voltage 0.7VCC 0.3VCC
AI05910
includes probe TTLcapacitance
AI05832
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M68AF511A
Table Capacitance
Symbol COUT Parameter(1,2) Input Capacitance pins (except Output Capacitance Test Condition VOUT Unit
Note: Sampled only, 100% tested. 25°C, 1MHz, 5.0V.
Table Characteristics
Symbol ICC1 (1,2) ICC2
Note:
Parameter Operating Supply Current Operating Supply Current Input Leakage Current Output Leakage Current Standby Supply Current CMOS Input High Voltage Input Voltage Output High Voltage Output Voltage
Test Condition 5.5V, 1/tAVAV, IOUT 5.5V, 1MHz, IOUT VOUT 5.5V, 0.2V,
Unit
-0.3
-1.0mA 2.1mA
Average current, cycling tAVAV minimum. VIL, VIL. 0.2V, 0.2V 0.2V. Output disable.
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M68AF511A
OPERATION M68AF511A Chip Enable power down feature which invokes automatic standby mode whenever Chip Enable de-asserted High). Output Enable signal provides high speed tri-state control, allowing fast read/write cyTable Operating Modes
Operation Output disabled Read Write Deselect
Note: VIL.
cles achieved with common data bus. Operational modes determined device control inputs summarized Operating Modes table (Table
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z
Power Active (ICC) Active (ICC) Active (ICC) Standby (ISB)
Read Mode M68AF511A Read mode whenever Write Enable High with Output Enable Low, Chip Enable asserted. This provides access data from eight 4,194,304 locations static memory array, specified address inputs. Valid data will available eight output pins within tAVQV after last
stable address, providing Low. Chip Enable Output Enable access times met, data access will measured from limiting parameter ELQV tGLQV) rather than address. Data indeterminate tELQX tGLQX, data lines will always valid tAVQV.
Figure Address Controlled, Read Mode Waveforms
tAVAV A0-A18 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI03034
Note: Low, Low, High.
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M68AF511A
Figure Chip Enable Output Enable Controlled, Read Mode Waveforms.
tAVAV A0-A18 tAVQV tELQV tELQX tGLQV tGLQX DQ0-DQ7 VALID
AI05912
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable High.
Figure Chip Enable Controlled, Standby Mode Waveforms
AI03036
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M68AF511A
Table Read Standby Mode Characteristics
M68AF511A Symbol tAVAV tAVQV tAXQX tEHQZ (2,3) tELQV tELQX tGHQZ (2,3) tGLQV tGLQX Read Cycle Time Address Valid Output Valid Data hold from Address change Chip Enable High Output Hi-Z Chip Enable Output Valid Chip Enable Output Transition Output Enable High Output Hi-Z Output Enable Output Valid Output Enable Output Transition Chip Enable High Power Down Chip Enable Power Parameter Unit
Note: Test conditions assume transition timig reference level 0.3V 0.7VCC. given temperature voltage condition, tEHQZ less than ELQX tGHQZ less than GLQX given device. These parameters defined time which outputs achieve open circuit conditions referenced output voltage levels. Tested initially after design process changes that affect these parameters
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M68AF511A
Write Mode M68AF511A Write mode whenever pins Low. Either Chip Enable input Write Enable input must deasserted during Address transitions subsequent write cycles. Write begins with concurrence Chip Enable being active with low. Therefore, address setup time referenced Write Enable Chip Enable tAVWL tAVEH respectively, determined latter occurring edge.
Write cycle terminated earlier rising edge Output enabled Low), then will return outputs high impedance within WLQZ falling edge. Care must taken avoid contention this type operation. Data input must valid tDVWH before rising edge Write Enable, DVEH before rising edge whichever occurs first, remain valid tWHDX tEHDX.
Figure Write Enable Controlled, Write Waveforms
tAVAV A0-A18 VALID tAVWH tELWH tWLWH tAVWL tWLQZ tWHDX DQ0-DQ7 DATA
tWHAX
tWHQX
DATA INPUT tDVWH
DATA
AI05913
Note: During this period DQ0-DQ7 output state input signal should applied.
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Figure Chip Enable Controlled, Write Waveforms
tAVAV A0-A18 VALID tAVEH tAVEL tWLEH tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI05914
tELEH
tEHAX
Table Write Mode Characteristics
M68AF511A Symbol tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tELWH tWHAX tWHDX tWHQX tWLEH tWLQZ (1,2) tWLWH Write Cycle Time Address Valid Chip Enable High Address Valid Chip Enable Address Valid Write Enable High Address Valid Write Enable Input Valid Chip Enable High Input Valid Write Enable High Chip Enable High Address Transition Chip Enable High Input Transition Chip Enable Chip Enable High Chip Enable Write Enable High Write Enable High Address Transition Write Enable High Input Transition Write Enable High Output Transition Write Enable Chip Enable High Write Enable Output Hi-Z Write Enable Write Enable High Parameter Unit
Note: These parameters defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tWLQZ less than tWHQX given device.
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M68AF511A
Figure Data Retention Waveforms.
DATA RETENTION MODE 5.5V 4.5V 2.0V tCDR 0.2V 2.2V
AI05915
Table Data Retention Characteristics
Symbol Parameter Test Condition 0.2V, tAVAV 0.2V, Unit ICCDR Supply Current (Data Retention) tCDR (1,2) Chip Deselected Data Retention Time Operation Recovery Time Supply Voltage (Data Retention)
Note: other Inputs -0.2V 0.2V. Tested initially after design process that affect these parameteres. tAVAV Read cycle time. input exceed +0.2V.
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M68AF511A
PACKAGE MECHANICAL Figure TSOP Type lead Plastic Thin Small Outline Type Package Outline
TSOP-e
Note: Drawing scale.
Table TSOP Type lead Plastic Thin Small Outline Type Package Mechanical Data
millimeters Symbol 1.27 20.82 11.56 10.03 0.40 0.05 0.95 0.30 0.12 1.20 0.15 1.05 0.52 0.21 0.10 21.08 11.96 10.29 0.60 0.050 0.820 0.455 0.395 0.016 0.002 0.037 0.012 0.005 0.047 0.006 0.041 0.020 0.008 0.004 0.830 0.471 0.405 0.024 inches
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M68AF511A
Figure SO32 lead Plastic Small Outline, Package Outline
SO-C
Note: Drawing scale.
Table SO32 lead Plastic Small Outline, Package Mechanical Data
millimeters Symbol 1.27 0.10 2.57 0.36 0.15 20.14 11.18 13.87 0.58 1.19 2.82 0.51 0.30 20.75 11.43 14.38 0.99 1.60 0.10 0.050 3.00 0.004 0.101 0.014 0.006 0.793 0.440 0.546 0.023 0.047 0.111 0.020 0.012 0.817 0.450 0.566 0.039 0.063 0.004 0.118 inches
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M68AF511A
PART NUMBERING Table Ordering Information Scheme
Example: Device Type Mode Asynchronous Operating Voltage 4.5V 5.5V Array Organization Mbit (512K Option Chip Enable Option L-Die M-Die Speed Class 55ns Package TSOP32 Type SO32 Operative Temperature Shipping Tape Reel Packing M68AF511
list available options (Speed, Package, etc.) further information aspect this device, please contact STMicroelectronics Sales Office nearest you.
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M68AF511A
REVISION HISTORY Table Document Revision History
Date July 2001 08-Aug-2001 27-Sep-2001 18-Oct-2001 29-Nov-2001 08-Jan-2002 08-Feb-2002 Version First Issue SO32 Package added 55ns Speed class introduced Industrial Temperature Range added (Range Typing error, Table Note SO32 Package Mechanical Data added Note Removed from Ordering Information Scheme PDIP32 package added Document fully revised tELQX, tAXQX changed Read Standby Mode Characteristics Table (Table tDVEH, tDVWH, tWLWH changed Write Mode Characteristics Table (Table PDIP32 package removed Block Diagram clarified (Figure Absolute Maximum Ratings table clarified (Table Operating Measurement Conditions table figure clarified (Table Figure Characteristics table clarified (Table Read Standby Mode Characteristics table clarified (Table Write Mode Characteristics table clarified (Table Operating Measurement Conditions table clarified (Table ICCDR Test Condition clarified (Table Read Standby Mode Characteristics clarified (Table Data Retention Characteristics clarified (Table Read Standby Mode Characteristics (Table clarified Characteristics Table clarified (Table Write Mode Characteristics Table clarified (Table ICCDR values clarified Revision numbering modified: minor revision will indicated incrementing digit after dot, major revision, incrementing digit before (revision version equals 13.0). part number added. Datasheet number simplified. Revision Details
25-Feb-2002
03-Mar-2002 25-Mar-2002 18-Apr-2002 26-Apr-2002 17-May-2002
02-Oct-2002
13.1
09-Oct-2002
13.2
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M68AF511A
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics other names property their respective owners. 2002 STMicroelectronics Rights Reserved STMicroelectronics GROUP COMPANIES Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www.st.com
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