Table ContentsGENERAL DESCRIPTION FEATURES APPLICATIONS.2 Feature
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Preliminary W91031 CALLING LINE IDENTIFIER
Table ContentsGENERAL DESCRIPTION FEATURES APPLICATIONS.2
Features Applications.2
CONFIGURATION DESCRIPTION.3 SYSTEM DIAGRAM BLOCK DIAGRAM FUNCTIONAL DESCRIPTION
Ring Detector.6 Input Pre-processor Dual Tone Alert Signal Detection.8 Demodulation.10 Other Functions
ELECTRICAL CHARACTERISTICS.14
Absolute Maximum Ratings Recommended Operating Conditions.14 Electrical Characteristics.14 Electrical Characteristics Gain Control OP-Amplifier Electrical Characteristics.16 Timing Characteristics
APPLICATION INFORMATION
Application Circuit.22 Application Environment
information described this document exclusive intellectual property Winbond Electronics Corporation shall reproduced without permission from Winbond. Winbond provides this document reference purposes W-based system design only. Winbond assumes responsibility errors omissions. data specifications subject change without notice.
Publication Release Date: August 2000 Revision
Preliminary W91031
GENERAL DESCRIPTION
Winbond Caller Identification device W91031, power CMOS integrated circuit used receive physical layer signals transmitted according Bellcore British Telecom (BT) specifications. There types Caller Identifications, first type on-hook calling with caller message second type call waiting. W91031 device provides features functions Caller Identification specification both these types, including demodulation, Tone Alert Signal detection ring detection. demodulation function demodulate Bell CCITT V.23 Frequency Shift Keying (FSK) with 1200 baud rate. Tone Alert Signal detect function detect dual tones Bellcore CPE* Tone Alerting Signal (CAS) idle State Loop State Tone Alert Signal. line reversal ring burst ring signal Bellcore detected ring detector. There modes data output interface. first mode data transfer activated device, whose clock data change depending upon changing frequency analog signal input. second mode allows microcontroller extract 8-bit data from device serially; device notifies micro-controller when 8-bit data been received.
Note: "CPE*" Customer Primises Equipment
FEATURES APPLICATIONS
Features
Compatible with Bellcore TR-NWT-000030 SR-TSV-002476, British Telecom (BT) SIN227, U.K.
Cable Communications Association (CCA) specification
Ring line reversal detection Bellcore Alerting Signal (CAS) idle State Loop State Tone Alerting Signal
detection dual tone alerting signal detector
BELL CCITT V.23 demodulation with 1200 baud rate 3.579545 crystal ceramic resonator power CMOS technology with sleep mode High input sensitivity Variable gain input amplifier carry detect output modes 3-wire data interface Packaged 24-pin inch (600 mil) plastic 24-pin inch (300 mil) plastic
Applications
Bellcore Calling Identity Delivery (CID), Calling Line Identity Presentation (CLIP), CLIP
systems
Feature phones Phone adjunct boxes answering machines Data base telephone system Computer Telephony Integration (CTI) systems
Preliminary W91031
CONFIGURATION
GCFB VREF TEST1 RNGDI RNGRC RNGON MODE OSCI OSCO
ALGRC ALGR ALGO INTN FCDN FDRN DATA DCLK FSKE SLEEP/RESET TEST2
W91031
View
DESCRIPTION
NAME GCFB TYPE DESCRIPTION Non-inverting Input gain control op-amp. Inverting Input gain control op-amp. Op-amp Feed-back Gain Control signal. Select input gain connecting this with feed-back resistor. recommended that op-amp unity gain. Reference Voltage. Nominally, VDD/2 used bias input gain control op-amp. Test pin, Must connected normal operation. Ring Detect Input (Schmitt trigger input). Used ring detection line reversal detection. Must maintain voltage between VSS. Ring (Open drain output schmitt trigger input). Used time interval from RNGDI inactive condition RNGON pin. external resistor must connected capacitor connected VSS, time interval time constant. Ring detection output (Low active). Indicates detection line reversal and/or ringing. Data interface MODE select. Sets data output interface mode when low, mode when high. Oscillator Input. 3.579545 crystal ceramic resonator should connected between this OSCO pin. driven external clock source.
VREF TEST1 RNGDI RNGRC
RNGON MODE OSCI
Publication Release Date: August 2000 Revision
Preliminary W91031
Descriptions, continued
NAME OSCO
TYPE
DESCRIPTION Oscillator Output. 3.579545 crystal ceramic resonator should connected between this OSCI pin. Should left open drive another clocked device when external clock connected OSCI pin. Power Supply Ground. Test pin. Must connected normal operation. Reset Sleep Input (Schmitt input). When high device will reseted enter power state disabling gain control op-amp, oscillator other internal circuits. function RNGDI, RNGRC RNGON pins affected when device sleep condition. This must normal operation. device must reseted micro controller external pulse after power Enable. Must high when demodulation. Should disable demodulator enable dual tone alert signal detector when dual tone alert signal expected. Data Clock interface. data output interface mode (MODE low), this output with changing frequency. interface mode this input. Data signal interface. Serial data output according frequency input data output interface mode (MODE low). Data shifted rising edge DCLK data output interface mode Both logic mark logic space. Data Ready interface (Low active). interface mode (MODE low), this identifies 8-bit data boundary serial output string. interface mode this used notify microcontroller extract 8-bit data (ie. 8-bit data been ready internally). Carrier Detect (Low active). When low, indicates signal been detected. Interrupt signal (open drain). used interrupt microcontroller when RNGON FDRN low, ALGO high. Remains until three signals have become inactive. Dual tone Alert signal Guard time detect Output. When high, guard time qualified dual tone alert signal been detected. Dual tone Alert signal Guard time Resistor. Also functions dual tone alert signal detect output without guard time. external resistor must connected between this ALGRC implement guard time detection. Dual tone Alert signal Guard time (CMOS output internal voltage comparator input). external resistor must connected between this ALGR external capacitor between this implement guard time detection. Power supply input.
TEST2 SLEEP/ RESET
FSKE
DCLK
DATA
FDRN
FCDN INTN
ALGO ALGR
ALGRC
Preliminary W91031
SYSTEM DIAGRAM
W91031 device applications include telephone systems which have caller features which display calling message display. Figure shows system diagram. illustrates chip connect between tip/ring microcontroller telephone system. ring signal detected W91031 device then interrupt sent microcontroller. ring detected signal will also directed ringer circuit. data decoded microcontroller displayed display. DTMF signal also generated DTMF generator call waiting performed. Other functions same telephone set.
Display
Keypads
Winbond Caller
Micro Controller Ringer
Speaker
Ring
Line Interface
(W91031)
Handset
DTMF Generator
Figure System Diagram Caller Application
Publication Release Date: August 2000 Revision
Preliminary W91031
BLOCK DIAGRAM
FSKE
MODE
Input Pre-processor
Demodulation Circuit Bandpass Filter Demodulator Data Output Interface
GCFB VREF
Anti-alias Filter
DCLK DATA FDRN FCDN
Carrier Detector internal circuit Bias Voltage Generator Power Saving Circuit Dual Tone Alert Signal Detection Circuit High Tone Detector Guard Time Circuit
INTN
Interrupt Generator
SLEEP/ RESET
High Tone Bandpass Filter internal circuit Tone Bandpass Filter
ALGO
ALGRC ALGR
Tone Detector
Oscillator Clock Driver
Ring Detector
OSCI OSCO
RNGDI
RNGRC
RNGON
Figure Block Diagram Winbond Caller
FUNCTIONAL DESCRIPTION
Figure shown functional blocks W91031. device must operate with 3.579545 system clock consists four major functions decribed follows:
Ring Detector
application circuit Figure illustrates relationship between RNGDI, RNGRC RNGON signals. three combination used detect increase RNGDI voltage from ground level above Schmitt trigger high going threshold voltage VT+.
Preliminary W91031
0.1uF
470K
Tip/A
200K
W91031 RNGDI
0.1uF
300K
Ring/B
470K
R5=150K
RNGRC
0.22uF
Allowance minimal ring voltage (peak peak) (max ring) T+(max) 0.7) Tolerance noise between Ring Vpeak (max noise)
T+(min)
RNGON
Time constant [VDD (VDD T+(min)
T+(max)
from 500K ohm. from 0.68
Figure 7-1. Application Circuit Ring Detecter
time constant RNGRC used delay output pulse RNGON going edge RNGDI. This edge goes from above voltage Schmitt trigger going threshold voltage VT-. time constant must greater than maximum period ring signal, ensure minimum RNGON interval filter ring signal envelope output. diode bridge shown Figure works both single ended ring signal balanced ringing. used maximum loading must equal value achieve balanced loading both ring line. form resistor divider supply reduced voltage RNGDI input. attenuation value determined detection minimal ring voltage maximum noise tolerance between tip/ring ground.
Publication Release Date: August 2000 Revision
Preliminary W91031
Input Pre-processor
input signal processed Input Pre-processor, which added offset voltage adjust input amplitude filter unwanted frequencies. gain control op-amp used bias input voltage with VREF signal voltage. voltage VREF VDD/2 typically, this must connected capacitor VSS. also used select input gain connecting feedback resistor between this pin. Figure shows necessary connections with tip/ring line inputs. single-ended configuration, gain control op-amp connected shown Figure 7-3.
W91031
VREF
W91031
VREF
Input
Ring
GCFB
Differential Input Amplifier +R5)
Voltage Gain Input Impedance
Voltage Gain
GCFB
Figure Differential Input Gain Control Circuit
Figure Single-ended Input Gain Control Circuit
Dual Tone Alert Signal Detection
dual tone alert signal separated into high tones detected high/low tone detector. dual tone alert signal detection circuit enabled when FSKE signal low. requires enable time enable dual tone alert signal detector when FSKE goes from high low. ALGR output dual tone detector when high indicates that high tone tone alert signals have been detected. guard time improves detection performance rejecting detected signals with insufficient duration masking momentary detection dropout. Figure shows relationship between ALGR, ALGRC ALGO pins Figure shows guard time waveform same pins. total recognition time tREC tGP, where tone present detect time tone present guard time. tone present guard time time constant with capacitor discharging from (the ALGRC discharges from through resistor). capacitor will discharge rapidly discharge switch after ALGO returns high. total absent time tABS tGA, where tone absent detect time tone absent guard time. tone absent guard time time constant with capacitor charging from (the ALGRC charges from through resistor). capacitor will charge rapidly charge switch after ALGO returns low. obtain unequal present absent guard times, diode connected shown Figure 7-6, give unequal resistance required during capacitor charging discharging.
Preliminary W91031
W91031
Dual tone detected Capacitor Charge/Discharge Control Circuit
Discharge Switch
ALGRC Comparator CPth Charge Switch
ALGR
ALGO
Figure 7-4. Guard Time Circuit Dual Tone Alert Signal Detection
Tip/Ring
Alerting Signal
ALGR
ALGRC
CPth
CPth
ALGO Discharge Switch Charge Switch
Figure 7-5. Guard Time Waveform ALGR, ALGRC ALGO Pins
Publication Release Date: August 2000 Revision
Preliminary W91031
W91031
ALGRC
W91031
ALGRC
(VDD -VCPth R2)) CPth R2))] diode forward voltage
[(VDD R2)) DD-V CPth R2))] (VDD VCPth diode forward voltage
Figure 7-6. Guard Time Circuits with Unequal Present Absent Time
Demodulation
demodulation circuit enabled when FSKE signal high. enable time required enable demodulator circuitry after FSKE signal goes from high. Carrier Detector carrier detector provides indication presence signal within frequency band. output amplitude bandpass filter sufficient magnitude holds carrier detect output signal FCDN goes low. FCDN will released bandpass filter output amplitude insufficient magnitude greater than hysteresis carrier detector allow momentary signal drop after FCDN been activated. When FCDN inactive, output demodulator ignored data output interface. mode 3-wire data output interface, DCLK DATA FDRN high clock data driven. mode internal shift registers updated, FDRN inactive (high state). DATA undefined DCLK clocked. 3-wire Interface 3-wire interface, DCLK, DATA FDRN pins, form data interface demodulation. DCLK data clock which either generated W91031 external device. DATA serial data that outputs data external devices. FDRN data ready signal, also output from W91031 external devices. There modes this 3-wire interface that selected. Mode where data transfer initiated W91031 device, Mode where data transfer initiated external microcontroller.
Preliminary W91031
Mode (MODE low): W91031 processes signal outputs signals DCLK, DATA FDRN pins. Figure shows timing diagram 3-wire signals input signal mode each received stop start sequence, device outputs fixed frequency clock string pulses DCLK pin. Each clock rising edge occurs middle each data bit. DCLK generated stop start bits. DCLK used clock driving signal serial parallel shift register serial data input microcontroller. After 8-bit data been shifted device, FDRN will supply pulse inform microcontroller process 8-bit data.
start
byte data
stop start
byte data
stop start
Tip/Ring
byte data start
stop start
byte data
stop start
DATA
DCLK0
DCLK
FDRN
Mark redundant stop bit(s), will omitted.
Figure 7-7. Serial Data Interface Timing Demodulation Mode
Mode (MODE high): W91031 processes signal sets FDRN denote 8-bit boundary indicate microcontroller that data been transmitted. FDRN will return high first rising edge DCLK. FDRN half nominal time (1/2400 sec) DCLK driven high. DCLK used shift 8-bit data (LSB shift first) rising edge. After last (MSB) been read, additional clock pulses DCLK ignored. Figure shows timing diagram 3-wire signals input signal mode
Publication Release Date: August 2000 Revision
Preliminary W91031
byte data
1)th byte data stop start stop start
Demodulated internal stream
FDRN
Note
Note
DCLK
DCLK1
DATA
byte data
1)th byte data
Notes: FDRN cleared high DCLK. FDRN cleared, maximum time (1/2 width).
Figure 7-8. Serial Data Interface Timing Demodulation Mode
Other Functions
Interrupt interrupt INTN open drain output used interrupt microcontroller. Either RNGON low, FDRN ALGO high will INTN will remain until these three pins return inactive state. microcontroller must read these pins know what kind interrupt occurred make correct interrupt response. When system powered there charge capacitors. voltage RNGRC RNGON will low. Also voltage ALGRC high ALGO will high SLEEP low. This will cause interrupt upon power which will cleared until both capacitors charged. microcontroller should therefore ignore interrupt from these source until capacitors charged microcontroller examine RNGON ALGO pins wait until these signals inactive during power interrupt. possible clear ALGO interrupt quickly setting SLEEP high. sleep mode, ALGO forced charge switch Figure will turn forcing capacitor charge rapidly. Sleep Mode W91031 into sleep mode setting SLEEP high, resulting reduced power consumption. this mode, gain control op-amp, oscillator internal circuits, except ring detector disabled. RNGDI, RNGRC RNGON pins affected, device still react call arrival indicators activate interrupt wake microcontroller. sleep mode disabled microcontroller.
Preliminary W91031
Crystal Oscillator operation frequency W91031 3.579545 MHz. Crystal oscillators, ceramic resonators other clock sources used. crystal oscillator ceramic resonator directly connected OSCI OSCO pins without need external components. other clock sources used, OSCI should driven clock source OSCO used drive other external clocked devices, left open. Figure shows some applications. crystal specification follows: Frequency: Frequency tolerance: Resonance mode: Load capacitance: Maximum drive level (mV): 3.579545 (-40° +85° Parallel
Maximum series resistance:
W91031
OSCI OSCO
3.579545
other clock
W91031
OSCI OSCO
W91031
OSCI OSCO
W91031
OSCI OSCO
Oscillator
OSCO
3.579545
Figure 7-9. Some Application Clock Driven Circuit
Bias Voltage Generator bias voltage generator provides impedance voltage source equal VDD/2 used bias gain control op-amp. voltage source also used internal circuits. capacitor should placed between VREF reduce noise.
Publication Release Date: August 2000 Revision
Preliminary W91031
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voltage referenced pin)
PARAMETER Supply Voltage with Respect Voltage Other Than Supplies (Note Current Other Than Supplies Storage Temperature
Notes:
SYMBOL
RATING -0.3 -0.7
UNITS
+0.7 should exceed maximum rating supply voltage. Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
Recommended Operating Conditions
(Voltages referenced
PARAMETER Power Supplies Clock Frequency Clock Frequency Tolerance Operational Temperature
SYMBOL FOSC
RATING 3.579545 -0.1 +0.1
UNIT
Electrical Characteristics
(VDD-VSS 3.0V. electrical characteristics supersede recommended operating conditions unless otherwise stated.)
PARAMETER Operating Supply Voltage Standby Supply Current Operating Supply Current
CONDITION
SYM.
MIN.
TYP.*
MAX. UNITS
TEST/ NOTES
Test Test
IDDQ 3.0V FSKE Mode 3.0V FSKE Alert Mode 5.0V FSKE Mode 5.0V FSKE Alert Mode IDD2 IDD1 IDD2 IDD1
Preliminary W91031
Electrical Characteristics, continued
PARAMETER Schmitt Input High Threshold Schmitt Input Threshold
CONDITION RNGDI, RNGRC SLEEP
SYM.
MIN. 0.48 0.28
TYP.*
MAX. 0.68 0.48
UNITS
TEST/ NOTES
Schmitt Hysteresis CMOS Input High Voltage CMOS Input Voltage Output High Source Current DCLK, MODE, FSKE RGNON, DCLK, DATA, FDRN, FCDN, ALGO, ALGRC, ALGR RGNON, DCLK, DATA, FDRN, FCDN, ALGO, ALGRC, ALGR, INTN RNGRC Input Current Input Current Output High-Z Current Output High-Z Current Output High-Z Current Reference Output Voltage Reference Output Resistance Comparator Threshold Voltage INP, INN, RNGDI SLEEP, DCLK, MODE, FSKE RNGRC ALGRC INTN VREF VREF ALGRC
VHYS
Note
Output Sink Current
Note
IIN1 IIN2 IOZ1 IOZ2 IOZ3 VRef RRef VCPth
Note Note Note Note Note
Tests: input pins except oscillator pins, analog inputs, output unloaded SLEEP VDD. input pins except oscillator pins, analog inputs, output unloaded, SLEEP FSKE FSKE VSS. Notes: Typical figure temperature design aids only, guaranteed subject production testing. VDD. VDD. VSS. VOUT VSS. Magnitude measurement, ignore signs. Output load.
Publication Release Date: August 2000 Revision
Preliminary W91031
Electrical Characteristics Gain Control OP-Amplifier
(Electrical characteristics supersede recommended operating conditions unless otherwise stated.)
PARAMETER Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Ratio Maximum Capacitive Load (GCFB) Maximum Resistive Load (GCFB)
SYM. PSRR
MIN.
TYP.*
MAX.
UNITS TEST CONDITIONS
ripple
Note: typical figure temperature design aids only, guaranteed subject production testing.
Electrical Characteristics
electrical characteristics supersede recommended operating conditions unless otherwise stated.)
Dual Tone Alert Signal Detection PARAMETER Tone Frequency High Tone Frequency Frequency Deviation Acceptance Frequency Deviation Rejection Maximum Input Signal Level Input Sensitivity Tone Reject Signal Level Tone Positive Negative Twist Accept Noise Tolerance SNRTONE
SYM.
MIN.
TYP. 2130 2750
MAX.
UNITS
NOTES
0.22
Notes: decibels with reference power into ohms, 0.7746 Vrms. Twist amplitude amplitude). range within which tones accepted. range outside which tones rejected. These characteristics temperature Both tones have same amplitude. Both tones nominal frequencies. Band limited random noise 300-3400 Present only when tone present.
Preliminary W91031
Detection
PARAMETER Input Frequency Detection Bell Mark (logic Bell Space (logic CCITT V.23 Mark (logic CCITT V.23 Space (logic Maximum Input Signal Level Input Sensitivity Transmission Rate Input Noise Tolerance SNRFSK 1188 1200 1212 FMARK FSPACE FMARK FSPACE 1188 2178 1280.5 2068.5 1200 2200 1300 2100 1212 2222 1319.5 2131.5 -5.78 baud SYMBOL MIN. TYP. MAX. UNITS +/-1% +/-1% +/-1.5% +/-1.5% NOTES
Notes: Both mark space have same amplitude nominal frequencies. These characteristics fort temperature Band limited random noise 3400 Present only when signal present.
Timing Characteristics
timing characteristics supersede recommended operating conditions unless otherwise stated.)
System PARAMETER Wake-up Time Sleep-down Time SYMBOL tWAKE tSLP CONDITION SLEEP OSCO MIN. TYP.* MAX. UNITS NOTES
Note: typical figures temperature design aids only, guaranteed subject production testing.
Dual Tone Alert Signal Detection
PARAMETER Alert Detection Enable Time Alert Signal Present Detect Time Alert Signal Absent Detect Time SYMBOL tALTE CONDITION FSKE (low) ALGR MIN. TYP.* MAX. UNITS NOTES
Note: typical figure temperature design aids only, guaranteed subject production testing.
Detection
PARAMETER Detection Enable Time Input FCDN Delay SYMBOL tFSKE CONDITION FSKE (high) MIN. TYP.* MAX. UNITS NOTES
Publication Release Date: August 2000 Revision
Preliminary W91031
Detection, continued
PARAMETER Input FCDN High Delay Hysteresis
SYMBOL
CONDITION FCDN
MIN.
TYP.*
MAX.
UNITS
NOTES
Note: typical figure temperature design aids only, guaranteed subject production testing.
3-Wire Interface (Mode
PARAMETER Rise Time Fall Time Time Rate Input Data Delay Rise Time Fall Time DATA DCLK Delay DCLK DATA Delay Frequency High Time Time DCLK FDRN Delay tIDD tDCD tCDD fDCLK0 tCRD DCLK, FDRN DCLK DCLK DATA 1201.6 1202.8 1204 SYMBOL DATA FDRN 1188 1200 CONDITION MIN. TYP.* MAX. 1212 UNITS NOTES
Notes: Ttypical figure temperature design aids only, guaranteed subject production testing. input data rate 1200 +/-12 baud. OSCI frequency 3.579545 +/-0.1%. Function signal condition. loading.
3-Wire Interface (Mode
PARAMETER Frequency Duty Cycle Rise Time DCLK Set-up FDRN DCLK Hold Time After FDRN tDDS tDDH DCLK, FDRN SYMBOL fDCLK1 DCLK CONDITION MIN. TYP.* MAX. UNITS NOTES
Note: typical figure temperature design aids only, guaranteed subject production testing.
Preliminary W91031
SLEEP
WAKE
OSCO
Figure 8-1. Wake Sleep Down Timing
Tip/Ring
ALTE
Alerting Signal
Alerting Signal
FSKE
Note
ALGR
Figure 8-2. Alert Detection Enable Alert Signal Present Absent Detect Timing Note: minimal delay from FSKE ALGR high tALTE tDP, alerting signal present before tALTE elapsed.
Tip/Ring
FSKE
Analog Signal
Analog Signal
FSKE
Note
FCDN
Figure 8-3. Detection Enable Carrier Detect Present Absent Timing Note: minimal delay from FSKE high FCDN high tFSKE tCP, analog signal present before tFSKE elapsed.
Publication Release Date: August 2000 Revision
Preliminary W91031
DATA
DCLK
Figure 8-4. Data DCLK Mode Ouput Timing
FDRN
Figure 8-5. FDRN Output Timing
byte data start
stop start
byte data
stop start
Tip/Ring
byte data start
stop start
byte data
stop start
DATA
DCLK0
DCLK
FDRN Mark redundant stop bit(s), will omitted.
Figure 8-6. Serial Data Interface Timing Demodulation Mode
Preliminary W91031
DCLK
Figure 8-7. DCLK Mode Input Timing
byte data
1)th byte data stop start stop start
Demodulated internal stream
FDRN
Note
Note
DCLK
DCLK1
DATA
byte data
1)th byte data
Notes:
FDRN cleared high DCLK. FDRN cleared, maximum time (1/2 width).
Figure 8-8. Serial Data Interface Timing Demodulation Mode
Publication Release Date: August 2000 Revision
Preliminary W91031
APPLICATION INFORMATION
Application Circuit
application circuit W91031 Figure shows device being used within typical system. Note that only circuit between W91031 line interface shown. gain control op-amp unity gain allow electrical characteristics this application circuit. should also noted that glitch with sufficient amplitude appears ring interface, this will detected ringing input this circuit.
22nF Tip/A 430K 0.1uF
W91031
22nF Ring/B 430K 53K6 60K4 0.1uF 470K 464K GCFB VREF TEST1 RNGDI RNGRC RNGON 200K MODE 150K OSCI 0.1uF 470K 300K 0.22uF OSCO FSKE SLEEP/ RESET TEST2 ALGRC ALGR ALGO INTN FCDN FDRN DATA DCLK
Must rest microcontroller pulse.
Resistor must have tolerance. Resistor have tolerance. Crystal 3.579545MHz with 0.1% frequency tolerance. must calculated according formula Figure 7-6(a) Bellcore application. 3-wire interface Mode selected.
Figure 9-1. Application Circuit.
Another application circuit W91031, which provides common mode rejection ringing circuit signals, shown Figure 9-2. When voltage between ring greater than zener diode breakdown voltage, photo-coupler will turn driving RNGDI high thus detecting ringing signal. Note however this case, glitch ring interface able turn photo-coupler therefore will detected ringing signal.
Preliminary W91031
Tip/A 22nF 430K
0.1uF
W91031
22nF Ring/B 430K 53K6 60K4 0.33uF
464K GCFB
ALGRC ALGR ALGO INTN FCDN FDRN DATA DCLK FSKE SLEEP/ RESET TEST2
VREF TEST1 RNGDI
0.1uF
RNGRC RNGON MODE
200K 0.01uF 470K
150K OSCI OSCO 0.22uF
Must reset microcontroller pulse.
Resistor must have tolerance. Resistor have tolerance. Crystal 3.579545MHz with 0.1% frequency tolerance. must calculated according formula Figure 7-6(a) Bellcore application. 3-wire interface Mode selected.
Figure 9-2. Application Circuit with Improved Common Mode Noise Immunity
Application Environment
There three major timing differences caller sequences, Bellcore, CCA. Figure timing diagram Bellcore on-hook data transmission Figure timing diagram Bellcore off-hook data transmission. Figure timing diagram caller display service on-hook data transmission Figure timing diagram caller display service off-hook data transmission. Figure timing diagram caller display service on-hook data transmission.
Publication Release Date: August 2000 Revision
Preliminary W91031
Tip/Ring
Ring
seizure Mark
Message
Ring
INTN
(M-mode C-mode)
RNGON
SLEEP
Note
Note
Note
Note
FSKE
Note
(C-mode)
FCDN
FDRN
DCLK
DATA
.101010.
Data
Figure 9-3. Input Output Timing Bellcore On-hook Data Transmission
typical 250-500 Depends data length
Notes designer choose wake W91031 only after RNGON signal conserve power battery operated CPE. delay from RNGON SLEEP (and FSKE) reactive time microcontroller. designer choose FSKE always high while on-hook, ensure emodulator does react other in-band noise. microcontroller places W91031 sleep condition after FCDN become inactive. W91031 woken this ring signal after data been processed. W91031 been woken ring, microcontroller times FCDN activated then puts W91031 into sleep condition.
Preliminary W91031
goes off-hook
mutes handset disables keypad sends
unmutes handset enables keypad Message
Tip/Ring
Note
Note
Mark
SLEEP
INTN
ALGO
FSKE
Note
Note
Note
FCDN
FDRN
DCLK
DATA
Data
Figure 9-4. Input Output Timing Bellcore Off-hook Data Transmission
75-85 55-65 58-75
0-100 0-500 Depends data length
Notes: where power available, designer choose switch over line power when goes off-hook battery power while on-hook. FSKE should enable alert tone detector when dual tone alert signal expected. capability disable detection setting FSKE always high during on-hook state. FSKE high soon finished sending acknowledge signal ACK. FSKE should when FCDN become inactive. unsuccessful attempts where office does send signal, should disable FSKE, unmute handset enable keypad after this interval elapsed.
Publication Release Date: August 2000 Revision
Preliminary W91031
Line Reversal
Wires
Alert Signal
Seizure
Mark
Message
Ring
RNGON
SLEEP
Note
INTN
tREC tABS
ALGO
load
(optional) Current wetting pulse (Refer SIN227)
load
Note
(Refer SIN227)
Note
FSKE
Note
FCDN
FDRN
sec) (500 typical)
DCLK
DATA
.101010.
Data
Figure 9-5. Input Output Timing Idle State (On-hook) Data Transmission
Notes: SIN227 specifies that loads should applied after dual tone alert signal. SIN227 specifies that loads should removed between 50-150 after signal. W91031 also placed sleep condition. FSKE should disable demodulator when expected. tone alerting signal speech DTMF tones same frequency band signal. W91031 woken this ring signal after data been processed.
Preliminary W91031
goes off-hook Start Point
mutes handset disables keypad sends Note Mark Message
unmutes handset enables keypad
Tip/Ring
Note Note
Alert Signal
SLEEP
INTN
tREC tABS
ALGO
FSKE
Note
Note
Note
FCDN
FDRN
DCLK
DATA
Data
Figure 9-6. Input Output Timing Loop State (Off-hook) Data Transmission
40-50 5-100 Depends data length
Notes:
80-85 65-75 45-75
where power available, designer choose switch over line power when goes off-hook battery power while on-hook. FSKE should enable alert tone detector when dual tone alert signal expected. exchange will have already disabled speech path distant customer both transmission directions. FSKE high soon finished sending acknowledge signal ACK. FSKE should when FCDN become inactive. unsuccessful attempts where exchange does send signal, should disable FSKE, unmute handset enable keypad after this interval.
Publication Release Date: August 2000 Revision
Preliminary W91031
Line Reversal
First Ring Cycle Seizure Mark Message
Wires
Ring Burst
RNGON
SLEEP
Note
INTN
load
load
Note
Note
FSKE
Note
FCDN
FDRN
(500 typical)
DCLK
DATA
.101010.
Data
Figure 9-7. Input Output Timing Caller Display Service Data Transmission
Notes: designer choose FSKE always high while on-hook signal expected. TW/P E/312 specifies that loads should applied between 250-400 after ring burst. TW/P E/312 specifies that loads should removed between 50-150 after signal. W91031 also placed sleep condition. W91031 woken first ring cycle after data been processed.
Preliminary W91031
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, Creation III, Kwun Tong Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice Fax-on-demand: -2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 First Street, Jose, 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, 115, Sec. -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: data specifications subject change withou notice.
Publication Release Date: August 2000 Revision
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