4683 Advanced Dual Dual Linear Power Controller HIP6020 prov

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4683 Advanced Dual Dual Linear Power Controller HIP6020 prov

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HIP6020
4683
Advanced Dual Dual Linear Power Controller
HIP6020 provides power control protection four output voltages high-performance, graphics intensive microprocessor computer applications. integrates controllers linear controllers, well monitoring protection functions into 28-pin SOIC package. controller regulates microprocessor core voltage with synchronous-rectified buck converter. second controller supplies computer system's 1.5V 3.3V power with standard buck converter. linear controllers regulate power 1.5V 1.8V power North/South Bridge core voltage and/or cache memory circuits. HIP6020 includes Intel-compatible, 5-input digital-to-analog converter (DAC) that adjusts core output voltage from 1.3VDC 2.05VDC 0.05V steps from 2.1VDC 3.5VDC 0.1V increments. precision reference voltage-mode control provide static regulation. second controller's output userselectable, through TTL-compatible signal applied SELECT pin, levels 1.5V 3.3V with accuracy. linear regulators external N-Channel MOSFETs bipolar pass transistors provide fixed output voltages 1.5V (VOUT3) 1.8V (VOUT4). HIP6020 monitors output voltages. single Power Good signal issued when core within ±10% setting other outputs above their undervoltage levels. Additional built-in over-voltage protection core output uses lower MOSFET prevent output voltages above 115% setting. controllers' over-current function monitors output current using voltage drop across upper MOSFET's rDS(ON) eliminating need current sensing resistor.
Features
Provides Regulated Voltages Microprocessor Core, Bus, North/South Bridge and/or Cache Memory, Power Drives N-Channel MOSFETs Linear Regulator Drives Compatible with both MOSFET Bipolar Series Pass Transistors Simple Single-Loop Control Designs Voltage-Mode Control Fast Converter Transient Response High-Bandwidth Error Amplifiers Full 100% Duty Ratios Excellent Output Voltage Regulation Core Output: Over Temperature Output: Over Temperature Other Outputs: Over Temperature TTL-Compatible Microprocessor Core Output Voltage Selection Wide Range 1.3VDC 3.5VDC Power-Good Output Voltage Monitor Over-Voltage Over-Current Fault Monitors Switching Regulators Require Extra Current Sensing Elements, MOSFET's rDS(ON) Small Converter Size Constant Frequency Operation 200kHz Free-Running Oscillator; Programmable From 50kHz Over 1MHz Small External Component Count
Applications
Motherboard Power Regulation Computers
Pinout
HIP6020 (SOIC) VIEW
UGATE2 PHASE2 VID4 VID3 VID2 VID1 VID0 PGOOD OCSET2 VSEN2 SELECT FAULT/RT VSEN4 UGATE1 PHASE1 LGATE1 PGND OCSET1 VSEN1 COMP1 VSEN3 DRIVE3 VAUX DRIVE4
Ordering Information
PART NUMBER HIP6020CB HIP6020EVAL1 TEMP. RANGE (oC) PACKAGE SOIC PKG. M28.3
Evaluation Board
2-281
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
VSEN3
OCSET2 VSEN1
OCSET1
Block Diagram
VAUX
DRIVE3 POWER-ON
0.75
HIP6020
PWM2 FAULT
VSEN2 ERROR AMP2
0.75 OSCILLATOR
SELECT
1.5V 3.3V
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1.10
RESET (POR) 200µA
VAUX
DRIVE4 1.26V
0.90
LINEAR UNDERVOLTAGE
VSEN4 200µA
1.15
PGOOD
UGATE2
DRIVE2
PHASE2 INHIBIT COMP2 INHIBIT SOFTSTART FAULT LOGIC
DRIVE1 UGATE1
GATE CONTROL
PHASE1
ERROR AMP1
GATE CONTROL
COMP1
PWM1
LGATE1
28µA DACOUT
SYNCH DRIVE CONVERTER (DAC) 4.5V
PGND
FAULT
COMP1
VID0 VID1
VID2
VID4 VID3
HIP6020 Simplified Power System Diagram
+5VIN PWM2 CONTROLLER VOUT1 PWM1 CONTROLLER
VOUT2
+3.3VIN
HIP6020
LINEAR CONTROLLER LINEAR CONTROLLER
VOUT3
VOUT4
Typical Application
+12VIN +5VIN OCSET1 PGOOD POWERGOOD
OCSET2
VOUT2 1.5V 3.3V
LOUT2
UGATE2 PHASE2
UGATE1 PHASE1 COUT2 LGATE1 PGND TYPEDET SELECT VSEN1 +3.3VIN VOUT3 1.5V VAUX
LOUT1
VOUT1 1.3V 3.5V
VSEN2
COUT1
HIP6020
DRIVE3 VSEN3
COMP1
COUT3 FAULT VID0 VOUT4 1.8V DRIVE4 VSEN4 VID1 VID2 VID3 COUT4 VID4
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HIP6020
Absolute Maximum Ratings
Supply Voltage, +15V PGOOD, RT/FAULT, DRIVE, PHASE, GATE Voltage 0.3V 0.3V Input, Output Voltage -0.3V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) SOIC Package. Maximum Junction Temperature (Plastic Package) .150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) .300oC (SOIC Lead Tips Only)
Operating Conditions
Supply Voltage, +12V ±10% Ambient Temperature Range 70oC Junction Temperature Range 125oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER SUPPLY CURRENT Nominal Supply Current POWER-ON RESET Rising Threshold Falling Threshold Rising VAUX Threshold VAUX Threshold Hysteresis Rising VOCSET1 Threshold OSCILLATOR Free Running Frequency Total Variation Ramp Amplitude
Recommended Operating Conditions, Unless Otherwise Noted. Refer Figures SYMBOL TEST CONDITIONS UNITS
UGATE1, LGATE1, UGATE2, DRIVE3, DRIVE4 Open
VOCSET 4.5V VOCSET 4.5V VOCSET 4.5V VOCSET 4.5V
1.26
10.4
FOSC VOSC
OPEN 200k Open
VP-P
STANDARD BUCK REGULATOR REFERENCE DAC(VID0-VID4) Input Voltage DAC(VID0-VID4) Input High Voltage DACOUT Voltage Accuracy PWM2 Reference Voltage PWM2 Reference Voltage PWM2 Reference Voltage Tolerance 1.5V 1.8V LINEAR REGULATORS (VOUT3 VOUT4) Regulation VSEN3 Regulation Voltage VSEN4 Regulation Voltage VSEN3,4 Under-Voltage Level VSEN3,4 Under-Voltage Hysteresis Output Drive Current VREG3 VREG4 VSEN3UV VSEN3 Rising VSEN3 Falling VAUX-VDRIVE 0.6V SELECT 0.8V SELECT 2.0V -1.0 +1.0
SYNCHRONOUS CONTROLLER ERROR AMPLIFIER Gain Gain-Bandwidth Product Slew Rate GBWP COMP1 10pF V/µs
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HIP6020
Electrical Specifications
PARAMETER CONTROLLERS GATE DRIVERS UGATE1,2 Source UGATE1,2 Sink LGATE Source LGATE Sink PROTECTION VSEN1 Over-Voltage (VSEN1/DACOUT) FAULT Sourcing Current OCSET1,2 Current Source Soft-Start Current POWER GOOD VSEN1 Upper Threshold (VSEN1/DACOUT) VSEN1 Under-Voltage (VSEN1/DACOUT) VSEN1 Hysteresis (VSEN1/DACOUT) PGOOD Voltage VPGOOD VSEN1 Rising VSEN1 Rising Upper/Lower Threshold IPGOOD -4mA IOVP IOCSET VSEN1 Rising VFAULT/RT 2.0V VOCSET 4.5VDC IUGATE RUGATE ILGATE RLGATE 12V, VUGATE1 VUGATE2) VGATE-PHASE 12V, VLGATE1 VLGATE Recommended Operating Conditions, Unless Otherwise Noted. Refer Figures (Continued) SYMBOL TEST CONDITIONS UNITS
Typical Performance Curves
CUGATE1 CUGATE2 CLGATE1 1000 RESISTANCE PULLUP +12V (mA) 3600pF 1500pF PULLDOWN SWITCHING FREQUENCY (kHz) 1000 660pF 4800pF
1000
SWITCHING FREQUENCY (kHz)
FIGURE RESISTANCE FREQUENCY
FIGURE BIAS SUPPLY CURRENT FREQUENCY
Functional Descriptions
(Pin
Provide bias supply this pin. This also provides gate bias charge MOSFETs controlled voltage this monitored Power-On Reset (POR) purposes.
PGND (Pin
This power ground connection. synchronous converter's lower MOSFET source this pin.
VAUX (Pin
+3.3V input voltage this monitored power-on reset (POR) purposes. Connected input, this provides boost current linear regulator output drives event bipolar transistors (instead N-channel MOSFETs) employed pass elements.
(Pin
Signal ground voltage levels measured with respect this pin.
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HIP6020
(Pin
Connect capacitor from this ground. This capacitor, along with internal 28µA current source, sets soft-start interval converter.
UGATE1, UGATE2 (Pins
Connect UGATE pins respective converter's upper MOSFET gate. These pins provide gate drive upper MOSFETs.
FAULT (Pin
This provides oscillator switching frequency adjustment. placing resistor (RT) from this GND, nominal 200kHz switching frequency increased according following equation:
200KHz
LGATE1 (Pin
Connect LGATE1 synchronous converter's lower MOSFET gate. This provides gate drive lower MOSFET.
COMP1 (Pins
COMP1 available external pins synchronous regulator error amplifier. inverting input error amplifier. Similarly, COMP1 error amplifier output. These pins used compensate voltage-mode control feedback loop synchronous converter.
GND)
Conversely, connecting pull-up resistor (RT) from this reduces switching frequency according following equation:
200KHz
12V)
VSEN1 (Pin
This connected synchronous converters' output voltage. PGOOD comparator circuits this signal report output voltage status overvoltage protection.
Nominally, voltage this 1.26V. event over-voltage over-current condition, this internally pulled VCC.
PGOOD (Pin
PGOOD open collector output used indicate status output voltages. This pulled when synchronous regulator output within ±10% DACOUT reference voltage when other outputs below their under-voltage thresholds. PGOOD output open `11111' code.
VSEN2 (Pin
Connect this output standard buck regulator. voltage this regulated level predetermined logic-level status SELECT pin. This also monitored PGOOD comparator circuit.
SELECT (Pin
This determines output voltage switching regulator. input sets output voltage 1.5V, while high input sets output voltage 3.3V.
VID0, VID1, VID2, VID3, VID4 (Pins
VID0-4 TTL-compatible input pins 5-bit DAC. logic states these five pins program internal voltage reference (DACOUT). level DACOUT sets microprocessor core converter output voltage, well coresponding PGOOD thresholds.
DRIVE3 (Pin
Connect this gate external MOSFET. This provides drive 1.5V regulator's pass transistor.
OCSET1, OCSET2 (Pins
Connect resistor (ROCSET) from this drain respective upper MOSFET. ROCSET, internal 200µA current source (IOCSET), upper MOSFET's onresistance (rDS(ON)) converter over-current (OC) trip point according following equation:
OCSET OCSET PEAK
VSEN3 (Pin
Connect this output 1.5V linear regulator. This monitored undervoltage events.
DRIVE4 (Pin
Connect this gate external MOSFET. This provides drive 1.8V regulator's pass transistor.
VSEN4 (Pin
Connect this output linear 1.8V regulator. This monitored undervoltage events.
over-current trip cycles soft-start function. voltage OCSET1 monitored power-on reset (POR) purposes.
Description
Operation
HIP6020 monitors precisely controls output voltage levels (Refer Figures designed microprocessor computer applications with 3.3V, bias input from power supply.
PHASE1, PHASE2 (Pins
Connect PHASE pins respective converter's upper MOSFET source. These pins represent gate drive return current path used monitor voltage drop across upper MOSFETs over-current protection.
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HIP6020
linear controllers. first controller (PWM1) designed regulate microprocessor core voltage (VOUT1). PWM1 controller drives MOSFETs synchronous-rectified buck converter regulates core voltage level programmed 5-bit digital-to-analog converter (DAC). second controller (PWM2) designed regulate advanced graphics port (AGP) voltage (VOUT2). PWM2 controller drives MOSFET (Q3) standard buck converter regulates output voltage digitally-programmable level 1.5V 3.3V. Selection either output voltage achieved applying proper logic level SELECT pin. linear controllers supply 1.5V power (VOUT3) 1.8V memory power (VOUT4). voltage. input clamp voltage exceeds reference voltage output voltage regulation.
PGOOD SOFT-START (1V/DIV)
VOUT2 3.3V)
Initialization
HIP6020 automatically initializes upon receipt input power. Special sequencing input supplies necessary. Power-On Reset (POR) function continually monitors input supply voltages. monitors bias voltage (+12VIN) pin, input voltage (+5VIN) OCSET1 pin, 3.3V input voltage (+3.3VIN) VAUX pin. normal level OCSET1 equal +5VIN less fixed voltage drop (see over-current protection). function initiates soft-start operation after supply voltages exceed their thresholds.
VOUT1 (DAC 2.5V) VOUT4 1.8V) OUTPUT VOLTAGES (0.5V/DIV)
VOUT3 1.5V)
Soft-Start
function initiates soft-start sequence. Initially, voltage rapidly increases approximately (this minimizes soft-start interval). Then internal 28µA current source charges external capacitor (CSS) 4.5V. error amplifiers reference inputs terminal) outputs (COMP1 pin) clamped level proportional voltage. voltage slews from output clamp allows generation PHASE pulses increasing width that charge output capacitor(s). After output voltage increases approximately value, reference input clamp slows output voltage rate-of-rise provides smooth transition final voltage. Additionally both linear regulators' reference inputs clamped voltage proportional voltage. This method provides rapid controlled output voltage rise. Figure shows soft-start sequence typical application. voltage rapidly increases approximately error amplifier output voltage reach valley oscillator's triangle wave. oscillator's triangular wave form compared clamped error amplifier output voltage. voltage increases, pulse-width PHASE increases. interval increasing pulse-width continues until each output reaches sufficient voltage transfer control error amplifier input reference clamp. consider 3.3V output (VOUT2) Figure this time occurs During interval between error amplifier reference ramps final value converter regulates output voltage proportional
TIME
FIGURE SOFT-START INTERVAL
remaining outputs also programmed follow voltage. PGOOD signal toggles `high' when output voltage levels have exceeded their under-voltage levels. Soft-Start Interval section under Applications Guidelines procedure determine soft-start interval.
Fault Protection
four outputs monitored protected against extreme overload. sustained overload output overvoltage VOUT1 output (VSEN1) disables outputs drives FAULT/RT VCC.
OVERCURRENT LATCH 0.15V INHIBIT
COUNTER FAULT LATCH FAULT
FIGURE FAULT LOGIC SIMPLIFIED SCHEMATIC
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HIP6020
Figure shows simplified schematic fault logic. over-voltage detected VSEN1 immediately sets fault latch. sequence three over-current fault signals also sets fault latch. over-current latch dependent upon states over-current (OC1 OC2), linear under-voltage (LUV) soft-start signals. window comparator monitors indicates when fully charged 4.5V signal). under-voltage either linear output (VSEN3 VSEN4) ignored until after soft-start interval Figure This allows VOUT3 VOUT4 increase without fault start-up. Cycling bias input voltage (+12VIN then resets counter fault latch. excessive currents cause VSEN3 VSEN4 fall below linear under-voltage threshold, signal sets overcurrent latch, providing fully charged. Blanking signal during charge interval allows linear outputs build above under-voltage threshold during normal operation. Cycling bias input power then resets counter fault latch.
FAULT/RT
COUNT
FAULT REPORTED
COUNT
COUNT
SOFT-START
Over-Voltage Protection
During operation, short across synchronous upper MOSFET (Q1) causes VOUT1 increase. When output exceeds over-voltage threshold 115% DACOUT, over-voltage comparator trips fault latch turns lower MOSFET (Q2) This blows input fuse reduces VOUT1. fault latch raises FAULT/RT VCC. separate over-voltage circuit provides protection during initial application power. voltages below power-on reset (and above ~4V), output level monitored voltages above 1.3V. Should VSEN1 exceed this level, lower MOSFET, driven
OVERLOAD APPLIED
INDUCTOR CURRENT
TIME
FIGURE OVER-CURRENT OPERATION
Over-Current Protection
outputs protected against excessive over-currents. Both controllers upper MOSFET's onresistance, rDS(ON) monitor current protection against shorted outputs. Both linear regulators monitor their respective VSEN pins under-voltage protect against excessive currents. Figure illustrates over-current protection with overload OUT2. overload applied current increases through inductor (LOUT2). time OVER-CURRENT2 comparator trips when voltage across rDS(ON)) exceeds level programmed ROCSET. This inhibits outputs, discharges soft-start capacitor (CSS) with 28µA current sink, increments counter. recharges initiates soft-start cycle with error amplifiers clamped soft-start. With OUT2 still overloaded, inductor current increases trip overcurrent comparator. Again, this inhibits outputs, soft-start voltage continues increasing 4.5V before discharging. counter increments soft-start cycle repeats trips over-current comparator. voltage increases 4.5V counter increments This sets fault latch disable converter. fault reported FAULT/RT pin. PWM1 controller operates same PWM2 over-current faults. Additionally, linear controllers monitor VSEN pins under-voltage. Should
OVER-CURRENT TRIP: OCSET OCSET OCSET IOCSET 200µA OVERCURRENT DRIVE UGATE PHASE PHASE OCSET
ROCSET
VSET
GATE CONTROL
FIGURE OVER-CURRENT DETECTION
Resistors (ROCSET1 ROCSET2) program over-current trip levels each converter. shown Figure internal 200µA current sink (IOCSET) develops voltage across ROCSET (VSET) that referenced DRIVE signal enables over-current comparator (OVER-CURRENT1 OVER-CURRENT2). When voltage across upper MOSFET (VDS(ON)) exceeds VSET, over-current comparator trips over-current latch. Both VSET referenced small capacitor across ROCSET helps VOCSET track variations
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HIP6020
MOSFET switching. over-current function will trip peak inductor current (IPEAK) determined
OCSET OCSET PEAK VID4 TABLE OUT1 VOLTAGE PROGRAM NAME VID3 VID2 VID1 VID0 NOMINAL DACOUT VOLTAGE 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05
trip point varies with MOSFET's rDS(ON) temperature variations. avoid over-current tripping normal operating load range, determine ROCSET resistor value from equation above with: maximum rDS(ON) highest junction temperature minimum IOCSET from specification table Determine IPEAK IPEAK IOUT(MAX) where output inductor ripple current. equation ripple current section under component guidelines titled `Output Inductor Selection'.
OUT1 Voltage Program
output voltage PWM1 converter programmed discrete levels between 1.3VDC 3.5VDC This output (OUT1) designed supply core voltage Intel's advanced microprocessors. voltage identification (VID) pins program internal voltage reference (DACOUT) with TTL-compatible 5-bit digital-to-analog converter (DAC). level DACOUT also sets PGOOD thresholds. Table specifies DACOUT voltage different combinations connections pins. pins left open logic input, because they internally pulled internal voltage about 10µA current source. Changing inputs during operation recommended could toggle PGOOD signal exercise over-voltage protection. `11111' combination disables opens PGOOD pin.
OUT2 Voltage Selection
regulator output voltage internally discrete levels, based status SELECT pin. SELECT internally pulled `high', such that left open, output voltage default 3.3V. other discrete setting available 1.5V, which obtained grounding SELECT using jumper another suitable method capable sinking tens microamperes. status SELECT cannot changed during operation without immediately causing fault condition.
NOTE: connected GND, open connected through pull-up resistors
Application Guidelines
Soft-Start Interval
Initially, soft-start function clamps error amplifier's output converters. This generates PHASE pulses increasing width that charge output capacitor(s). After output voltage increases approximately value, reference input error amplifier clamped voltage proportional voltage. resulting output voltages start-up shown Figure soft-start function controls output voltage rate rise limit current surge start-up. soft-start interval surge current programmed soft-start capacitor, CSS. Programming faster soft-start interval
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HIP6020
increases peak surge current. peak surge current occurs during initial output voltage rise value. Using recommended 0.1µF soft start capacitor insures output voltages ramp their values within 10ms input voltages reaching levels. component ground connections with vias this layer. Dedicate another solid layer power plane break this plane into smaller islands common voltage levels. power plane should support input power output power nodes. copper filled polygons bottom circuit layers PHASE nodes, unnecessarily oversize these particular islands. Since PHASE nodes subjected very high dV/dt voltages, stray capacitor formed between these islands surrounding circuitry will tend couple switching noise. remaining printed circuit layers small signal wiring. wiring traces from control MOSFET gate source should sized carry peak currents.
+5VIN
Shutdown
Neither output switches until soft-start voltage (VSS) exceeds oscillator's valley voltage. Additionally, reference each linear's amplifier clamped softstart voltage. Holding (with open drain open collector signal) turns four regulators. `11111' code, also shuts down
Layout Considerations
MOSFETs switch very fast efficiently. speed with which current transitions from device another causes voltage spikes across interconnecting impedances parasitic circuit elements. voltage spikes degrade efficiency, radiate noise into circuit, lead device over-voltage stress. Careful component layout printed circuit design minimizes voltage spikes converter. Consider, example, turn-off transition upper MOSFET. Prior turn-off, upper MOSFET carrying full load current. During turnoff, current stops flowing upper MOSFET picked lower MOSFET Schottky diode. inductance switched current path generates large voltage spike during switching interval. Careful component selection, tight layout critical components, short, wide circuit traces minimize magnitude voltage spikes. There sets critical components DC-DC converter using HIP6020 controller. switching power components most critical because they switch large amounts energy, such, they tend generate equally large amounts noise. critical small signal components those connected sensitive nodes those supplying critical bypass current. power components controller should placed first. Locate input capacitors, especially highfrequency ceramic de-coupling capacitors, close power switches. Locate output inductor output capacitors between MOSFETs load. Locate controller close MOSFETs. critical small signal components include bypass capacitor soft-start capacitor, CSS. Locate these components close their connecting pins control Minimize leakage current paths from node, since internal current source only 28µA. multi-layer printed circuit board recommended. Figure shows connections critical components converter. Note that capacitors COUT each could represent numerous physical capacitors. Dedicate solid layer ground plane make critical
+12V COCSET2
CVCC
OCSET2 OCSET1 UGATE2 UGATE1 PHASE2 PHASE1
COCSET1 ROCSET1 LOUT1 VOUT1 LOAD VOUT4 LOAD
ROCSET2 VOUT2 LOUT2 LOAD COUT2
COUT1
LGATE1 HIP6020
VOUT3 COUT3 +3.3VIN
LOAD
DRIVE3 DRIVE4 PGND
COUT4
ISLAND POWER PLANE LAYER ISLAND CIRCUIT PLANE LAYER CONNECTION GROUND PLANE
FIGURE PRINTED CIRCUIT BOARD POWER PLANES ISLANDS
PWM1 Controller Feedback Compensation
Both controllers voltage-mode control output regulation. This section highlights design consideration voltage-mode controller requiring external compensation. Apply these methods considerations only synchronous controller. considerations standard controller presented separately. Figure highlights voltage-mode control loop synchronous-rectified buck converter. output voltage (VOUT) regulated Reference voltage level. reference voltage level output voltage (DACOUT) PWM1. error amplifier output (VE/A) compared with oscillator (OSC) triangular wave provide pulse-width modulated wave with amplitude PHASE node. wave smoothed output filter CO).
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DRIVER COMP DRIVER PHASE (PARASITIC) VOUT
Compensation Break Frequency Equations
VOSC
VE/A
ERROR
REFERENCE
DETAILED COMPENSATION COMPONENTS VOUT
Figure shows asymptotic plot DC-DC converter's gain frequency. actual Modulator Gain high gain peak dependent quality factor output filter, which shown Figure Using above guidelines should yield Compensation Gain similar curve plotted. open loop error amplifier gain bounds compensation gain. Check compensation gain with capabilities error amplifier. Closed Loop Gain constructed log-log graph Figure adding Modulator Gain Compensation Gain dB). This equivalent multiplying modulator transfer function compensation transfer function plotting gain.
OPEN LOOP ERROR GAIN COMPENSATION GAIN
COMP
HIP6020
DACOUT GAIN (dB)
MODULATOR GAIN
FIGURE VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
modulator transfer function small-signal transfer function VOUT /VE/A. This function dominated Gain, given /VOSC shaped output filter, with double pole break frequency zero FESR
FESR 100K
CLOSED LOOP GAIN
Modulator Break Frequency Equations
FREQUENCY (Hz)
FIGURE ASYMPTOTIC BODE PLOT CONVERTER GAIN
compensation network consists error amplifier (internal HIP6020) impedance networks ZFB. goal compensation network provide closed loop transfer function with high crossing frequency (f0dB) adequate phase margin. Phase margin difference between closed loop phase f0dB degrees. equations below relate compensation network's poles, zeros gain components (R1, Figure these guidelines locating poles zeros compensation network: Pick Gain (R2/R1) desired converter bandwidth Place Zero Below Filter's Double Pole (~75% FLC) Place Zero Filter's Double Pole Place Pole Zero Place Pole Half Switching Frequency Check Gain against Error Amplifier's Open-Loop Gain Estimate Phase Margin Repeat Necessary
compensation gain uses external impedance networks provide stable, high bandwidth (BW) overall loop. stable control loop gain crossing with -20dB/decade slope phase margin greater than degrees. Include worst case component variations when determining phase margin.
PWM2 Controller Feedback Compensation
reduce number external small-signal components required typical application, standard controller internally stabilized. only stability criteria that needs relates minimum value output inductor equivalent output capacitor bank, shown following equation:
1.75
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HIP6020
where LOUT(MIN) minimum output inductor value full output current ESROUT equivalent output capacitor bank desired converter bandwidth (not exceed 0.25 0.30 switching frequency) design procedure this output should follow following steps: Choose number type output capacitors meet output transient requirements based dynamic loading characteristics output. Determine equivalent output capacitor bank calculate minimum output inductor value. Verify that chosen inductor meets this minimum value criteria full output load). recommended chosen output inductor more than saturated full output load. High frequency decoupling capacitors should placed close power pins load physically possible. careful inductance circuit board wiring that could cancel usefulness these inductance components. Consult with manufacturer load specific decoupling requirements. only specialized low-ESR capacitors intended switching-regulator applications bulk capacitors. bulk capacitor's determines output ripple voltage initial voltage drop following high slew-rate transient's edge. aluminum electrolytic capacitor's value related case size with lower available larger case sizes. However, equivalent series inductance (ESL) these capacitors increases with case size reduce usefulness capacitor high slew-rate transient loading. Unfortunately, specified parameter. Work with your capacitor supplier measure capacitor's impedance with frequency select suitable component. most cases, multiple electrolytic capacitors small case size perform better than single large case capacitor.
Oscillator Synchronization
controllers triangle wave comparison with error amplifier output provide pulse-width modulated signal. Should output voltage converters programmed close each other, then crosstalk between converters could cause non-uniform PHASE pulse-widths increased output voltage ripple. HIP6020 avoids this problem synchronizing converters degrees phase output voltage settings within same range. Therefore, both output voltage settings less than 2.4V both output voltage settings greater equal 2.4V, PWM1 operates phase with PWM2. output voltage setting below 2.4V other output voltage setting 2.4V above, PWM1 operates phase with PWM2.
Linear Output Capacitors
output capacitors linear regulators provide dynamic load current. Thus capacitors COUT3 COUT4 should selected transient load regulation.
Output Inductor Selection
Each converter requires output inductor. output inductor selected meet output voltage ripple requirements sets converter's response time load transient. Additionally, PWM2 output inductor meet minimum value criteria loop stability described paragraph `PWM2 Controller Feedback Compensation'. inductor value determines converter's ripple current ripple voltage function ripple current. ripple voltage current approximated following equations:
Component Selection Guidelines
Output Capacitor Selection
output capacitors each output have unique requirements. general output capacitors should selected meet dynamic regulation requirements. Additionally, converters require output capacitor filter current ripple. load transient microprocessor core requires high quality capacitors supply high slew rate (di/dt) current demands.
Increasing value inductance reduces ripple current voltage. However, large inductance values increase converter's response time load transient. parameters limiting converter's response load transient time required change inductor current. Given sufficiently fast control loop design, HIP6020 will provide either 100% duty cycle response load transient. response time time interval required slew inductor current from initial current value post-transient current level. During this interval difference between inductor current transient current level must supplied output capacitor(s). Minimizing response time minimize output capacitance required.
Output Capacitors
Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply transient current slow load rate-of-change seen bulk capacitors. bulk filter capacitor values generally determined (effective series resistance) voltage rating requirements rather than actual capacitance requirements.
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response time transient different application load removal load. following equations give approximate response time interval application removal transient load:
TRAN RISE TRAN FALL
main component power dissipation lower MOSFETs. Only upper MOSFET significant switching losses, since lower device turns into near zero voltage. equations presented assume linear voltage-current transitions model power loss reverse recovery lower MOSFET's body diode. gate charge losses dissipated HIP6020 don't heat MOSFETs. However, large gate-charge increases switching time, tSW, which increases upper MOSFET switching losses. Ensure that both MOSFETs within their maximum junction temperature high ambient temperature calculating temperature rise according package thermal resistance specifications. separate heatsink necessary depending upon MOSFET power, package type, ambient temperature flow.
UPPER LOWER
where: ITRAN transient load current step, tRISE response time application load, tFALL response time removal load. sure check both these equations minimum maximum output levels worst case response time.
Input Capacitor Selection
important parameters bulk input capacitor voltage rating current rating. reliable operation, select bulk input capacitors with voltage current ratings above maximum input voltage largest current required circuit. capacitor voltage rating should least 1.25 times greater than maximum input voltage. current rating requirement input capacitors buck regulator approximately summation output load current. input bypass capacitors control voltage overshoot across MOSFETs. ceramic capacitance high frequency decoupling bulk capacitors supply current. Small ceramic capacitors placed very close upper MOSFET suppress voltage induced parasitic circuit impedances. through-hole design, several electrolytic capacitors (Panasonic series Nichicon series Sanyo MV-GX equivalent) needed. surface mount designs, solid tantalum capacitors used, caution must exercised with regard capacitor surge current rating. These capacitors must capable handling surge current power-up. series available from AVX, 593D series from Sprague both surge current tested.
rDS(ON) different equations above even same device used both. This because gate drive applied upper MOSFET different than lower MOSFET. Figure shows gate drive where upper MOSFET's gate-to-source voltage approximately less input supply. main power +12VDC bias, gate-to-source voltage lower gate drive voltage +12VDC. logic-level MOSFET good choice logic-level MOSFET used absolute gate-to-source voltage rating exceeds maximum voltage applied
LESS +12V
HIP6020
UGATE PHASE
NOTE: NOTE:
MOSFET Selection/Considerations
HIP6020 requires external transistors. Three N-channel MOSFETs employed converters. memory linear controllers each drive MOSFET bipolar pass transistor. these transistors should selected based upon rDS(ON) current gain, saturation voltages, gate supply requirements, thermal management considerations. LGATE PGND
FIGURE UPPER GATE DRIVE DIRECT DRIVE
PWM1 MOSFET Selection Considerations
high-current applications, MOSFET power dissipation, package selection heatsink dominant design factors. power dissipation includes loss components; conduction loss switching loss. These losses distributed between upper lower MOSFETs according duty factor. conduction losses
Rectifier clamp that catches negative inductor swing during dead time between turn lower MOSFET turn upper MOSFET. diode must Schottky type prevent lossy parasitic MOSFET body diode from conducting. acceptable omit diode body diode lower MOSFET clamp negative inductor swing, efficiency could drop, some
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HIP6020
cases, percent result. diode's rated reverse breakdown voltage must greater than maximum input voltage.
Linear Controllers Transistor Selection
HIP6020 linear controllers compatible with both bipolar well N-Channel MOSFET transistors. main criteria selection pass transistors linear regulators package selection efficient removal heat. power dissipated linear regulator
LINEAR
PWM2 MOSFET Schottky Selection
power dissipation PWM2 converter similar PWM1 except that power losses lower device Schottky MOSFET. power losses PWM2 converter distributed between upper MOSFET Schottky. equations below describe approximation this distribution assume linear voltage-current switching transitions.
Select package heatsink that maintains junction temperature below maximum desired temperature with maximum expected ambient temperature. When selecting bipolar transistors with linear controllers, insure current gain given operating sufficiently large provide desired output load current when base with minimum driver output current.
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HIP6020 HIP6020 DC-DC Converter Application Circuit
Figure shows application circuit power supply microprocessor computer system. power supply provides microprocessor core voltage (VOUT1), voltage (VOUT2), voltage (VOUT3), memory voltage (VOUT4) from +3.3V, +5VDC, +12VDC.
+12VIN +5VIN 1000pF 2.7K OCSET2 OCSET1 PGOOD 1.0K POWERGOOD C1-7 7x1000µF 1000pF
detailed information circuit, including Bill-ofMaterials circuit board description, Application Note AN9836. Also Intersil' page (http://www.intersil.com) Intersil AnswerFAX (407-7247800), document number 99836 latest information.
VOUT2 (3.3V/1.5V)
HUF76107D3S
UGATE2 PHASE2
UGATE1 PHASE1
Q1,2 HUF76143S3S
4.2µH
VOUT1 (1.3V-3.5V)
6.2µH C12-14 3x1000µF MBRD835L
VSEN2 SELECT VAUX
LGATE1
C15-22 8x1000µF 10.2K
PGND VSEN1 10pF 1.62K
TYPEDET +3.3VIN HUF76107D3S
HIP6020
DRIVE3 VSEN3 VOUT3 (1.5V) C26,27 2x1000µF FAULT/RT HUF76107D3S VID0 VID1 VID2 VID3 VID4 2.7nF 150K COMP1
0.22µF
499K
VOUT4 (1.8V)
DRIVE4 VSEN4
C28,29 2x1000µF
0.1µF
FIGURE POWER SUPPLY APPLICATION CIRCUIT MICROPROCESSOR COMPUTER SYSTEM
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, site http://www.intersil.com
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4683 Advanced Dual Dual Linear Power Controller HIP6020 prov

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