Cost VMEbus Interface Controller Family 80-Mbyte-per-second block

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Cost VMEbus Interface Controller Family 80-Mbyte-per-second block

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CY7C960 CY7C961
Cost VMEbus Interface Controller Family
80-Mbyte-per-second block transfer rates VME64 transactions provided, including A64/D64, A40/MD32 transfers Auto Slot CR/CSR space standard (Rev VMEbus transactions implemented VMEbus Interrupter local required Programmable from VMEbus, serial PROM, local DRAM controller, including refresh On-chip controller Local controller Flexible VMEbus address scheme User-configured VMEbus response 64-pin TQFP, 10x10mm (CY7C960) 100-pin TQFP, 14x14mm (CY7C961)
Functional Description
CY7C960 Slave VMEbus Interface Controller provides board designer with integrated, full-featured VME64 interface. This 64-pin device programmed handle every transaction defined VME64 specification. CY7C961 based upon CY7C960: additional features include Remote Master capability whereby CY7C961 commanded move data VMEbus master. CY7C961 packaged 100-pin outline. CY7C960 contains circuitry needed control large DRAM arrays local circuitry without intervention local CPU. There registers read write, complex command blocks constructed memory. CY7C960 simply fetches configuration parameters during power-on reset period. After reset CY7C960 responds appropriately VMEbus activity controls local circuitry transparently.
CY7C960 Logic Block Diagram
STROBE DENO* DENIN* DENIN1* LADI LAEN LEDI LEDO ABEN*
REGION [3:0]
[5:0]
REGION/ TABLE POWER-ON RESET GENERATOR
CY7C964 CONTROLLER
LOCAL ADDRESS CONTROLLER
[7:1] WORD
SYSRESET* DS0* DS1* DTACK* WRITE* IRQ* IACK* IACKIN* IACKOUT*
TIMING GENERATOR
CHIP SELECT OUTPUT PATTERN TABLE
CS[5:0]
CONTROL INTERF REFRESH CONTROLLER INTERRUPT INTERF DRAM CONTROLLER
DATABYTE LANE DECODER
DATA BYTE ENABLE CONTROLLER
[3:0] LACK*
LOCAL CONTROL CIRCUIT
LDEN* PREN* SWDEN*
LIRQ*
RAS* CAS*
c960-1
Cypress Semiconductor Corporation
3901 North First Street
Jose 95134 408-943-2600 December 1994 Revised December 1997
CY7C960 CY7C961
STROBE DENO* DENIN* DENIN1* LADI LAEN LEDI LEDO ABEN* MWB* LADO LAEN321 VMECNT LOCAL ADDRESS CONTROLLER
CY7C961 Logic Block Diagram
REGION [3:0] SELECTLM
AM[5:0]
REGION/ AMTABLE POWER-ON RESET GENERATOR
CY7C964 CONTROLLER
[7:1] LWORD
SYSRESET* DS0* DS1* DTACK* WRITE* BBSY* BERR* BGIN* BGOUT* IRQ* IACK* IACKIN* IACKOUT*
CHANNEL REGISTERS TIMING GENERATOR CHIP SELECT OUTPUT PATTERN TABLE CONTROLLER DATA BYTE ENABLE DATABYTE CONTROLLER LANE DECODER LOCAL CONTROL CIRCUIT
[7:0]
[5:0]
CONTROL INTERF
[3:0] LACK* LBERR* LDEN* PREN* SWDEN*
REFRESH CONTROLLER INTERRUPT INTERF LOCK CONTROLLER DRAM CONTROLLER
c960-2
CY7C960 Configuration
TQFP View
PREN* SWDEN* RAS*/CS4 CAS*/CS5 ROW/CS2 COL/CS3
LIRQ*
DBE0
LACK* LIRQ* LDEN* REGION3/CS2 REGION2 WRITE* REGION1 REGION0 DENIN* 2728 c960-3 ABEN* DTACK* DS0* SYSRESET* LEDO LEDI DENO* IACKOUT* IACKIN* IACK* LADI STROBE IRQ* DS1* LWORD DENIN1* LAEN
DBE1 DBE2 DBE3
RAS* CAS*
CY7C960 CY7C961
CY7C961 Configuration
ROW/CS2 PREN* SWDEN* RAS*/CS4 CAS*/CS5
TQFP View
COL/CS3 DBE0 DBE1 DBE2 DBE3
10099 LACK* LIRQ* LDEN* REGION3/CS2 BERR* VMECNT REGION2 WRITE* REGION1 REGION0 DENIN* 3637 4546 SELECTLM* LBERR* IRQ* LAEN321 BBSY* DS1* LWORD DENIN1* LAEN
c960-4 DS0* SYSRESET* LADO LEDO LADI STROBE BGIN* ABEN* DTACK* DENO* IACKOUT* IACKIN* BGOUT* IACK* MWB* LEDI
Functional Description (continued)
CY7C960 controls bridge between VMEbus local DRAM I/O. Once programmed, CY7C960 provides activities such DRAM refresh local handshaking manner that requires additional local circuitry. VMEbus control signals connected directly CY7C960. VMEbus address data signals connected companion address/data transceivers which controlled CY7C960. CY7C964 VMEbus Interface Logic Circuit ideal companion device: CY7C964 provides slice data address logic that been optimized VME64 transactions. addition providing specified drive strength timing VME64 transactions, CY7C964 contains circuitry needed multiplex address/data multiplexed VMEbus transactions. contains counters latches needed during operations; also contains address comparators which used board's Slave Address Decoder. application, four CY7C964 devices controlled single CY7C960. applications, CY7C960 controls CY7C964 devices address latch. design CY7C960 makes unnecessary know details VMEbus transaction timing protocol. complex VMEbus activities translated CY7C960 simple local cycles involving familiar control signals. Similarly, necessary understand operation com-
panion device, CY7C964: control sequences part generated automatically CY7C960 response VMEbus local activity. more information desired, consult CY7C964 chapter VIC64 Design Notes (available separately). VMEbus transactions supported CY7C960 include D16, (incl. UAT), MD32, D64, A16, A24, A32, A40, single-cycle block-transfer reads writes, Read-Modify-Write cycles (incl. multiplexed), Address-only (with without Handshake). CY7C960 functions VMEbus Interrupter, supports Auto Slot standard CR/CSR space. CY7C960 also handles LOCK cycles, although full LOCK support possible within constraints CY7C960 pinout. Full LOCK support provided CY7C961. local side, needed program CY7C960, manage transactions. programmable parameters initialized through either VMEbus, serial PROM, some other local circuit. CY7C960 incorporates reliable power-on reset circuit, parameters self-loaded device power-up after system reset. VMEbus used provide parameters, VMEbus Master provides programming information using protocol, described User's Guide, which compliant with Auto Slot protocol from VME64 specification.
CY7C960 CY7C961
assist generating configuration file, WindowsTM-based program available which guides user through process selecting appropriate options. Contact your Sales Office further details. CY7C961 true superset CY7C960. Signal pins have been added control CY7C964 functions. Existing VMEbus input pins have been changed bidirectional augmented complete master interface. data port chip select signal (SELECTLM*) complete additions. VMEbus Slave, CY7C961 behaves every respect like CY7C960. simply more pins, master block transfer facility, (because addition BBSY* connection) full lock cycle support. From system perspective, CY7C961 master block transfer capability viewed channel that resides slave card, controlled over VMEbus more VMEbus masters programmed from local bus. CY7C961 master block facility provides "block transfer demand" capability slave cards built around Cypress CY7C961/CY7C964 chipset. This facility allows many VMEbus masters write short series commands slave card, telling much data move, where from, where what transfer protocol while moving Blocks moved over VMEbus indivisible single cycles BLTs. protocol menu includes D16, D32, MD32, D64. A16, A24, A32, A40, address spaces specified. Burst lengths from bytes megabytes requested. Eight registers accessible from VMEbus make facility simple configure simple control. facility busy semaphore, VMEbus Interrupt completion feature with programmable Status/ID byte, built requester grant daisychain.
System Diagram Using CY7C960
[31:0] DRAMMEMORY DBE[3:0], LACK* RAS*, CAS*, ROW,COL
LIRQ* CS[2:0] SWDEN D[31:16] SWAP BUFFER LD[15:0]
DECODER
VCOMP REGION [31:0] [7:1, LWORD]
CY7C964
CY7C964
CY7C964
CY7C964
CY7C960
A[7:1], LWORD*
D[31:24]
D[23:16]
A[31:24]
A[23:16]
A[15:8]
AM[5:0]
DS1/0* DTACK WRITE*
D[15:8]
D[7:0]
VMEDATABUS
D[31:0]
ADDRESS
[31:1], LWORD* INTERRUPT
IRQ* IACK* IACKIN* IACKOUT* SYSRESET*
c960-5
CY7C960 CY7C961
Specifications VMEbus Signals AS*, DS1*, DS0*, DTACK*, BBSY
Parameter Description Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Input Clamp Voltage Maximum Output Leakage Current Test Conditions Comm. Min., Min., Max., Min., Max. VOUT Outputs Disabled -1.2 Industrial -1.2 Military -1.2 Units
Specifications VMEbus Signals AM5, AM4, AM3, AM2, AM1, AM0, IRQ*, BERR*, Write, BR[1]
Parameter Description Maximum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Minimum Low-Level Output Voltage Maximum Input Leakage Current Input Clamp Voltage Maximum Output Leakage Current Test Conditions Comm. Min., Min., Max., Min., Max. VOUT Outputs Disabled -1.2 Industrial -1.2 Military -1.2 Units
Specifications Other Output Signals[2]
Parameter Description Maximum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Minimum Low-Level Output Voltage Maximum Input Leakage Current Input Clamp Voltage Maximum Output Leakage Current Test Conditions Comm. Min., Min., Max., Min., Max. VOUT Outputs Disabled -1.2 Industrial -1.2 Military -1.2 Units
Notes: BERR* signal on-chip pull-up resistor. this signal value modified Pullup/Pulldown Current. Some signals have on-chip pull-up pull-down resistors. these signals value modified.
CY7C960 CY7C961
Capacitance Signals
Parameters COUT Description Input Capacitance Output Capacitance Test Conditions 25°C, MHz, 5.0V Max. Units
Pullup/Pulldown Current Signals
Parameters Description Input Pullup Current Input Pullup Current Test Conditions -55°C, 5.5V -55°C, 5.5V Typ. Max.
Operating Current (CY7C960/CY7C961)
Parameters Description Test Conditions Maximum Operating Current external load Max. Units
Related Documents
VMEBus Interface Handbook
Ordering Information
Ordering Code CY7C960-ASC CY7C960-NC CY7C960-UM CY7C960-UMB Package Name Package Name A100 Package Type 10x10 body 64-Lead Plastic Thin Quad Flatpack 14x14 body 64-Lead Plastic Thin Quad Flatpack 14x14 body lead Ceramic Quad Flatpack 14x14 body lead Ceramic Quad Flatpack Operating Range Military Operating Range Commercial
Ordering Code CY7C961-NC
Package Type
14x14 body 100-Lead Plastic Thin Quad Flatpack Commercial
Windows trademark Microsoft Corporation. Document 38-00250-D
CY7C960 CY7C961
Package Diagrams
64-Pin Thin Quad Flatpack
CY7C960 CY7C961
Package Diagrams (continued)
100-Pin Thin Quad Flatpack A100
CY7C960 CY7C961
Package Diagrams (continued)
64-Lead Plastic Thin Quad Flatpack
CY7C960 CY7C961
Package Diagrams (continued)
64-Lead Ceramic Quad Flatpack (Cavity
Cypress Semiconductor Corporation, 1997. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

Cost VMEbus Interface Controller Family 80-Mbyte-per-second block

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