Edition 2001-12-05 Published Infineon Technologies St.-Martin-Strasse

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Line Interface Unit
Edition 2001-12-05 Published Infineon Technologies St.-Martin-Strasse D-81669 Germany
Infineon Technologies 2001. Rights Reserved.
Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
Line Interface Unit
3452 PRELIMINARY Revision History: Previous Version: Page
2001-12-05
Preliminary Data Sheet TE3-LIU V1.2, 2001-07,
Subjects (major changes since last revision) Chapter 4.1.4 Table Figure
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com
3452 TE3-LIU V1.3
Table Contents 3.3.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.5.1 4.1.5.2 4.1.5.3 4.1.6 4.1.6.1 4.1.6.2 4.1.6.3 4.1.7 4.1.8 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.6.1 4.2.6.2 4.2.6.3 4.2.7 Page
Overview Features Logic Symbol Typical Applications
Descriptions Diagram Definitions Functions Functional Description Functional Overview Block Diagram Functional Blocks Hardware Control Unit Interface Description Receiver Standard Receiver Application Line Monitoring Application Receive Line Interface Receive Clock Data Recovery Receive Line Coding Code B3ZS Code HDB3 Code Alarm Handling Definition STS-1 Definition Definition Jitter Tolerance Receive Output Jitter Transmitter Transmit Line Interface Transmit Clock System Jitter Attenuation Intrinsic Jitter Pulse Shaper Transmit Line Coding Code B3ZS Code HDB3 Code Insertion Framer Interface Maintenance Functions
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
Table Contents 4.4.1 4.4.2 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.7.1 6.4.7.2 6.4.7.3 Page
Remote Loop Local Loop Operational Description Operational Overview Device Reset Device Power Down Transmit Line Inactive Electrical Characteristics Absolute Maximum Ratings Operating Range Characteristics Characteristics Reset Reference Clock Jitter Attenuator Reference Clock Microprocessor Control Transmit Input Timing Receive Output Timing Pulse Templates Pulse Template Pulse Template Pulse Template STS-1 Capacitances Package Characteristics Test Configuration
Package Outlines Appendix Cable Characteristics Application Example
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Page
Logic Symbol T3/T1 Multiplexer Application. Channelized Link Layer Application Unchannelized Link Layer Application Configuration Block Diagram Receiver Configuration Line Monitoring Receive Clock System Loss Signal Definition Jitter Tolerance Principle Jitter Tolerance Transmitter Configuration Transmit Clock System Jitter Attenuation Characteristic Remote Loop Signal Flow Local Loop Signal Flow Reset Timing Reference Clock Timing. XTAL Clock Timing Recommended Crystal Circuit Crystal Pulling Range Chip Select Timing XCLK Input Timing RCLK Output Timing Pulse Shape Transmitter Output Pulse Shape Cross Connect Point (450 ft.) STS-1 Pulse Shape Cross Connect Point (450 ft.) Thermal Behavior Package Input/Output Waveforms Testing Cable Characteristics Application Circuit
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Page
Interface Functions Control Functions. Power Supply Pins Test Pins Hardware Control Functions Hardware Indication Signals External Component Values Receiver External Component Values Line Monitoring Receive Return Loss Input Jitter Requirements External Component Values Transmitter Transmit Return Loss Jitter Attenuation Operation Frequencies Transmit Output Jitter Maximum Ratings Power Supply Range Parameters Reset Timing Parameter Values REFCLK Timing Parameter Values XTAL Timing Parameter Values XTAL Crystal Parameter Values Chip Select Timing Parameter Values XCLK Timing Parameter Values RCLK Timing Parameter Values Pulse Mask Pulse Mask (ANSI T1.404, GR-499-CORE) Pulse Mask (ANSI T1.404) Pulse Mask (GR-499-CORE) STS-1 Pulse Mask STS-1 Pulse Mask (ANSI T1.102) Capacitances Package Characteristic Values Test Conditions
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY
Preface
3452 (TE3-LIUTM) flexible line interface unit wide area telecommunication data communication applications. device addressed fulfill requirements build DS3, STS-1 line interface.
Organization this Document This Preliminary Data Sheet organized follows: Overview Gives general description product, lists features, presents some typical applications. Descriptions Lists locations with associated signals, categorizes signals according function, describes signals. Functional Description Describes functional blocks principle operation modes. Interface Description Describes device interfaces. Operational Description Shows operation modes their initialization. Electrical Characteristics Specifies maximum ratings, characteristics. Package Outlines Shows mechanical values device package. Appendix Index
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Related Documentation This document refers following international standards alphabetical/numerical order): TS016 (general requirements Australia) CTR-24/TBR-24 requirements) transmit return loss) ITU-T G.703 pulse mask, B3ZS/HDB3 code, receive return loss) ITU-T G.751 (jitter requirements ITU-T G.775 (loss signal definition) ITU-T G.823 (jitter requirements ITU-T G.824 (jitter requirements DS3) ITU-T O.151 (pseudo random binary sequence (PRBS) definition) GR-253-CORE (STS-1 jitter requirements) GR-499-CORE (DS3 pulse mask, jitter requirements) ANSI T1.102 (STS-1 pulse mask) ANSI T1.102 Annex (DS3 monitoring) ANSI T1.231 (maintenance functions, defect definitions) ANSI T1.404 (DS3 pulse mask) MIL-STD 883D (ESD requirements)
Your Comments welcome your comments this document. continuously trying improving documentation. Please send your remarks suggestions e-mail com.docu_comments@infineon.com Please provide subject your e-mail: device name (TE3-LIUTM), device number (PEF 3452), device version (Version 1.3), body your e-mail: document type (Preliminary Data Sheet), issue date (2001-12-05) document revision number (DS1).
Preliminary Data Sheet 2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Overview
Overview
TE3-LIUPEF 3452 Line Interface Unit used connect DS3/STS-1 framer device analog transmission line. line interface fulfills relevant standards (44.736 Mbit/s), STS-1 (51.840 Mbit/s) (34.368 Mbit/s) systems. TE3-LIUcomes P-MQFP-44-2 package (SMD) save significant amount board space. integrated jitter attenuation further reduces overall system complexity cost. This CMOS power device contains integrated pulse shaper drive line length within range 1100 without need external length selection (Line Build Out). hardware configuration mode allows cost systems with flexible device setting without need microprocessor. optional microprocessor mode allows connection standard microprocessor control hardware settings.
Preliminary Data Sheet
2001-12-05
PRELIMINARY
Line Interface Unit DS3, STS1 TE3-LIU
3452
Version
Features
Generic analog interface DS3/STS-1/E3 applications Single chip solution receive transmit direction power device Integrated receive equalization network Integrated noise crosstalk filter Clock data recovery using integrated P-MQFP-44-2 with ultra-low intrinsic jitter Transmit clock duty cycle correction external components required clock data recovery receive equalizer receive line monitor (additional gain according ANSI T1.102) transmitter output impedances high transmit return loss Disable function analog transmit line outputs Transmit pulse shaper fulfill requirements ANSI T1.404, Telcordia GR-499-CORE, ANSI T1.102 ITU-T G.703 (E3) Maximum line length 1100 (using standard coaxial cable, example AT&T 728A, 734A 734D) External line length selection (LBO) required Jitter specifications GR-499-CORE ITU-T G.823 Integrated jitter attenuation buffer transmit direction Dual single rail digital inputs outputs from/to framer interface Selectable line codes (HDB3 (E3), B3ZS (DS3/STS-1), AMI) Analog digital loss signal detection indication Automatic RDOP/RDON blanking option case Bipolar violation indication Local loop remote loop diagnostic purposes Insertion alarm indication signal ("all ones") Flexible hardware software controlled device configuration Device power down function
Type 3452 V1.3
Preliminary Data Sheet
Package P-MQFP-44-2
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Hardware Interface Mode DS3/STS-1 Line Coding (E3: HDB3 AMI; DS3/STS-1: B3ZS AMI) Transmitter disable Power down Remote loop Local loop Single/dual rail operation Receive clock edge selection Transmit clock edge selection Transmit "all ones" Receive line monitoring mode Automatic RDOP/RDON blanking option Jitter attenuation Loss signal indication Bipolar violation indication Overview
Microprocessor Interface Mode Microprocessor compatible interface Hardware control lines directly accessible General CMOS device P-MQFP-44-2 package (body size lead pitch Single power supply: 5V-tolerant digital input lines Temperature range -40°C +85°C power device
Applications Interface SONET/DS3 network equipment gateways CSU/DSU Multiplexers Digital crossconnect systems DS3/STS-1/E3 Test Equipment
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Overview
Logic Symbol
VDDRP VSSRP
VDDR VSSR
REFCLK
RDOP RDON/BPV RCLK
XTAL1 XTAL2
3452 TE3-LIU
XDIP XDIN XCLK Access
DS3/STS-1 DS3/E3
VDDXP VSSXP
DR/SR LCODE XAIS
VDDX VSSX
JATT
F0229
Figure
Logic Symbol
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Overview
Typical Applications
Figure Figure show typical applications using TE3-LIUTM.
digital digital
TE3_LIUTE3-MUX
QuadLIU#1
analog
analog
QuadLIU#7
analog
F0087
Figure
T3/T1 Multiplexer Application
analog
TE3-LIU
TE3CHATT
F0217
Figure
Channelized Link Layer Application
analog
TE3-LIU
TE3-MUX
DSCC4
F0140
Figure
Unchannelized Link Layer Application
2001-12-05
Preliminary Data Sheet
3452 TE3-LIU V1.3
PRELIMINARY Overview
Note: TE3-MUX (PEB 3445) MUltipleXer/demultiplexer with integrated framer QuadLIU(PEB 22504) 4-channel Line Interface Unit E1/T1/J1 DSCC4(PEB 20534) 4-channel Serial Communication Controller TE3-CHATT(PEB 3456) CHAnnelized Termination with
Framer, Multiplexer, T1/E1 Framers Channel HDLC/PPP controller
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Descriptions
Descriptions
Diagram
P-MQFP-44-2 (top view)
RDON/BPV
REFCLK
RDOP
RCLK
XCLK
XDIN
XDIP
VDDXP XTAL2 XTAL1 VSSXP JATT VDDX
3452 TE3-LIU
VDDRP VSSRP
XAIS
LCODE
DR/SR
VSSX
DS3/E3
VSSR
DS3/STS1
VDDR
F0230
Figure
Configuration
2001-12-05
Preliminary Data Sheet
3452 TE3-LIU V1.3
PRELIMINARY Descriptions
Table
Definitions Functions
Interface Functions Symbol Input Output Supply (analog) Function
Receive Direction Line Receiver Analog input from external transformer (receive bipolar ring). signal must coded according B3ZS HDB3. Line Receiver Analog input from external transformer (receive bipolar tip). signal must coded according B3ZS HDB3. Receive Data Output/Positive Received data RL1/2 sent RDOP/ RDON framer interface. Data clocked with rising falling edge RCLK, depending RPE. single rail mode (DR/SR=0), data sent format. Receive Data Output/Negative dual rail data format selected, negative data signal output RDON/ BPV. Bipolar Violation single rail data format selected, bipolar violation indication signal output RDON/BPV. synchronized RCLK. Receive Clock Receive Clock extracted from incoming data pulses. active clock edge determined RPE. During LOS, clock signal generated internally driven RCLK (derived from REFCLK).
(analog)
RDOP
RDON
RCLK
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Table Interface Functions (cont'd) Symbol Input Output Supply (analog) Function Descriptions
Transmit Direction Transmit Line (transmit bipolar ring) Analog output external transformer. switched into inactive mode. Transmit Line (transmit bipolar tip) Analog output external transformer. switched into inactive mode. Transmit Data In/Positive Transmit data received from framer interface output XL1/2. dual rail positive data provided XDIP. Latching data done with rising falling transitions XCLK, depending XPE. Transmit Data In/Negative dual rail format selected, negative data signal read from XDIN. single rail data format selected, data XDIN ignored. Latching data done with rising falling transitions XCLK, depending XPE. Transmit Clock Input working clock transmitter. active clock edge determined XPE. DS3: 44.736 STS-1: 51.840 34.368 fulfill e.g. ITU-T G.832 clock accuracy required. correct function clock signal always supplied XCLK.
(analog)
XDIP
XDIN
XCLK
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Table Interface Functions (cont'd) Symbol Input Output Supply Function Descriptions
Global Clock Reference REFCLK Reference Clock REFCLK basic internal clock. must stable during reset operation. This clock also used synchronize receive case signal. clock frequency depends target application: DS3: 44.736 STS-1: 51.840 34.368 fulfill e.g., ITU-T G.832 clock accuracy required. XTAL1 XTAL2 Jitter Attenuation Reference Connection external pullable crystal. DS3: 14.912 STS-1: 17.280 11.456 jitter attenuation disabled (default), XTAL1 internally driven fixed level (not floating).
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Table Control Functions Symbol Input Output Supply Function Descriptions
Hardware Reset signal this forces device into reset state. Chip Select hardware control signals switched through hardware control signals ignored DS3/STS-1 Select Primary mode selection. This signal stable during reset change afterwards. must connected bus. STS-1 (see DS3/STS-1) STS-1 Select Primary mode selection. This signal stable during reset change afterwards. must connected bus. STS-1 Line Code Select receive transmit direction HDB3 DS3/STS-1: B3ZS
DS3/E3
DS3/STS-1
LCODE
XAIS
Transmit Alarm Indication all-ones insertion
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Table Control Functions (cont'd) Symbol Input Output Supply Function Descriptions
Remote Loop Switching loop Remote Loop Local Loop Switching loop Local Loop1) Transmitter inactive transmitter enabled transmitter disabled (outputs common mode voltage) Line Monitoring Mode additional gain RL1/RL2 normal Blanking Enable detected signal switched through even case all-zero signal sent RDOP/RDON case LOS, REFCLK used drive RCLK Dual Rail/Single Rail Select framer interface operated either dual rail single rail mode. single rail mode, signal output RDON/ input XDIN ignored. single rail dual rail RCLK Positive Edge Selection RDOP, RDON clocked with negative (falling) edge RCLK RDOP, RDON clocked with positive (rising) edge RCLK XCLK Positive Edge Selection XDIP, XDIN clocked with negative (falling) edge XCLK XDIP, XDIN clocked with positive (rising) edge XCLK
2001-12-05
DR/SR
Preliminary Data Sheet
3452 TE3-LIU V1.3
PRELIMINARY Table Control Functions (cont'd) Symbol Input Output Supply Function Descriptions
JATT
Jitter Attenuation Enable This signal stable during reset change afterwards. must connected bus. jitter attenuation (default left open) jitter attenuation transmit direction Loss Signal Indication correct signal loss signal synchronized RCLK. During LOS, clock signal generated internally driven RCLK.
RL=LL=1, device into power down mode.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Table Power Supply Pins Symbol Input Output Supply (analog) (analog) (analog) (analog) (analog) (analog) (analog) (analog) Function Descriptions
VDDR VSSR VDDX VSSX VDDRP VSSRP VDDXP VSSXP
Positive Power Supply analog receiver Power Supply Ground analog receiver Positive Power Supply analog transmitter Power Supply Ground analog transmitter Positive Power Supply analog receiver Power Supply Ground analog receiver Positive Power Supply analog transmitter Power Supply Ground analog transmitter Positive Power Supply digital subcircuits digital receiver output Power Supply Ground digital subcircuits digital receiver output
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Table Test Pins Symbol Input Output Supply Function Descriptions
Controller Reset Active test controller reset; this must connected Test Data Input Test Mode Select Test Clock Test Data Output
These pins used factory test only; boundary scan mode provided.
Note: input input/output comprising internal pullup device input input/output comprising internal pulldown device override internal pullup (pulldown) external pulldown (pullup), resistor value recommended. Unused pins containing pullups pulldowns left open.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Functional Description
Functional Description
Functional Overview
TE3-LIUdevice contains analog digital functional blocks, which configured controlled direct hardware microprocessor control. main interfaces Receive Line Interface Transmit Line Interface Framer Interface Hardware Interface
main internal functional blocks Analog line receiver with noise crosstalk filter, equalizer network clock/data recovery Analog line driver with programmable pulse shaper Central clock generation module Jitter attenuator Maintenance functions (e.g., loop switching local remote) Hardware/microprocessor control interface
Preliminary Data Sheet
2001-12-05
Preliminary Data Sheet 2001-12-05
Figure Block Diagram
Gain Stage Noise Filter Local Loop Line Driver Hardware/µP Interface XAIS LCODE DR/SR
PRELIMINARY
Autom. Gain Control
Level Detection
ALOS Detection LOS, Detection
Block Diagram
Var. Gain Amplifier
Equalizer
Clock Data Recovery
Decoder
RCLK RDOP RDON/BPV
REFCLK
DR/SR LCODE DS3/STS1/E3 Remote Loop
Transmit
Jitter Attenuator
XTAL1 XTAL2 JATT
Pulse Shaper
Jitter Attenuator Buffer
Insertion
Encoder
XCLK XDIP XDIN
XAIS Mode Control General Control Test Mode Control
DR/SR LCODE DS3/STS1/E3
Functional Description
3452 TE3-LIU V1.3
JATT
DS3/STS-1
DS3/E3
REFCLK
F0231
3452 TE3-LIU V1.3
PRELIMINARY Functional Description
3.3.1
Functional Blocks Hardware Control Unit
hardware control signals except DS3/E3, DS3/STS-1 JATT gated other control signals gated allow easy connection microprocessor (µP) data bus. DS3/E3, DS3/STS-1 JATT connected data bus. direct hardware control without intended, connected After reset control input values cleared. default control values (driven internal pullups) activated after applied first time after reset. Table Hardware Control Functions Control Signal DS3/E3 STS-12) DS3/STS-1 STS-1 DS32) This ignored, mode selected DS3/E3 DR/SR single rail data RDOP XDIP dual rail data RDOP/RDON XDIP/XDIN2) data change negative edge data change positive edge2) data change negative edge data change positive edge2) LCODE HDB3 (E3)2) B3ZS (DS3/STS-1)2)
Device Function Selection DS3/STS-1 mode1)
Selection STS-1 mode1)
Dual rail select
Receive clock edge selection
Transmit clock edge selection
Selection line coding
Send (all-ones alarm indication signal) XAIS insertion insertion2)
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Table Hardware Control Functions (cont'd) Control Signal normal operation remote loop normal operation local loop normal operation remote loop operation local loop operation power down2) Functional Description
Device Function Select remote loop
Select local loop
Select power down mode
Blanking enable
data signal switched through even case all-zero signal transmitted RDOP/RDON case using RCLK derived from REFCLK2) additional gain stage activated normal amplifier setting2) normal operation inactive2)3)4) JATT jitter attenuation disabled2) jitter attenuation enabled
Line monitoring mode
Transmitter inactive mode
Jitter attenuation enable
selected while reset active (RST default, left open been asserted least once outputs common mode voltage connecting asserting parallel suppresses spurious output XL1/2
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Table Hardware Indication Signals Indication Signal normal signal loss signal violation bipolar violation Available single rail mode only RDON/BPV. Functional Description
Device Function Indicate (loss signal)
Indicate (bipolar violation)
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.1
Interface Description
Receiver Standard Receiver Application
TE3-LIU
F0080
Figure Table Parameter
Receiver Configuration External Component Values Receiver Characteristic Line Impedance STS-1
[nF]
external components same DS3, STS-1 applications.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.2
Line Monitoring Application
cross connect point
TE3-LIUReceiver Mode MON=1
TE3-LIUMonitor Mode MON=0 F0081
Figure Table Parameter
Line Monitoring External Component Values Line Monitoring Values
[nF]
external components according ANSI T1.102 Annex dimensions given above lead signal level monitor device input approximately below level receiver device. Similar configurations using line monitoring mode possible STS-1 applications.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.3
Receive Line Interface
receive line interface consists pre-amplifier, noise crosstalk filter, variable gain amplifier equalizer followed clock data recovery. noise crosstalk filter reduces distortions within incoming analog signal. amplifies analog signal equalizer compensates frequency dependent line attenuation. Digital signal levels formed within retiming block clock data recovery. Receive return loss requirements ITU-T G.703 fulfilled required operation. Table Receive Return Loss Frequency Range from [kHz] 1720 34368 [kHz] 1720 34368 51550 Return Loss [dB]
equalizer contains additional gain stage, which used line monitoring mode amplify resistively attenuated signals.
Reference Clock
Automatic Gain Control
Level Detection
False Lock Detection
Gain Stage
Noise Crosstalk Filter
Variable Gain Amplifier
Equalizer
Receive
Receive Clock
Retiming
Dual Rail Receive Data
F0094 V1.3
Figure
Receive Clock System
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.4
Receive Clock Data Recovery
receive clock data recovery extracts route clock RCLK from digital data stream converts data stream into dual rail stream. clock data recovery needs reference clock keep stable during times without data signal RL1/RL2. clock that output RCLK recovered clock signal provided RL1/RL2 duty cycle close intrinsic jitter generated absence input jitter defined Chapter 4.1.8. reference clock generated internally without need external components.
4.1.5
Receive Line Coding
applications HDB3 coding provided data received from ternary interface. DS3/STS-1 mode B3ZS code supported. B3ZS code code violations detected indicated.
4.1.5.1
Code
code defined dual rail data signal, where combinations ("0"), ("+1") ("-1") valid. subsequent "+1" "-1" bits allowed, these will detected bipolar violations indicated RDON/BPV, single rail mode selected (according ANSI T1.231 chapter 7.1). received data stream either switched transparently framer interface dual rail data converted into single rail data stream.
4.1.5.2
B3ZS Code
B3ZS line code each block three consecutive zeros replaced either replacements codes which 00V, where represents pulse which applies bipolar rule ("+1" "-1") represents bipolar violation (two consecutive "+1" "-1" bits). replacement code chosen that there number valid pulses between consecutive pulses avoid introduction component into analog signal. receive line decoder decodes incoming B3ZS data signal changes replacement patterns original three-zeros pattern. Pattern sequences violation these rules reported bipolar violation errors. Data output framer interface selected either dual rail single rail.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.5.3
HDB3 Code
HDB3 line code each block four consecutive zeros replaced either replacements codes which B00V 000V, where represents pulse which applies bipolar rule ("+1" "-1") represents bipolar violation (two consecutive "+1" "-1" bits). replacement code chosen that there number valid pulses between consecutive pulses avoid introduction component into analog signal. receive line decoder decodes incoming HDB3 data signal changes replacement patterns original three-zeros pattern. Pattern sequences violation these rules reported bipolar violation errors. Data output framer interface selected either dual rail single rail.
4.1.6
Alarm Handling
receive line interface includes alarm detection loss signal (LOS). indicated either analog digital loss signal condition detected. During clock signal sent RCLK. clock internally derived from REFCLK.
4.1.6.1
Definition
Detection recovery digital defects mode done according ANSI T1.231: defect occurs when contiguous pulse positions with pulses either positive negative polarity line interface detected. defect terminated upon detecting average pulse density least over period contiguous pulse positions following receipt pulse. defect shall terminated pulse-position interval, subintervals pulse positions contain pulses either polarity.
4.1.6.2
STS-1 Definition
Detection recovery digital defects STS-1 mode defined ANSI T1.231 (chapter 8.1.2.1.1) follows: defect occurs upon detection transitions incoming signal (before descrambling) time where defect terminated after time period equal greater containing transition-free interval length where
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.6.3
Definition
Analog detected, signal level pins RL1/2 drops below fixed level ("B") certain period. Loss signal level defined between below normal signal level "A". signal exceeds contiguous pulse periods, analog defect indicated. Analog defect cleared, signal exceeds threshold below nominal level contiguous pulse periods 255). ITU-T G.775 reference.
ITU-T G.775 page
Maximum cable loss
Nominal value
Level below Nominal
"transition condition" must detected
Tolerance range, transition condition" "transition condition" declared
transition condition" must detected
F0101 V1.2
Figure
Loss Signal Definition
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.1.7
Jitter Tolerance
TE3-LIUreceiver's tolerance input jitter complies exceeds relevant international standards. Especially requirements Telcordia GR-499-CORE (DS3), ITU-T G.824 (DS3), GR-253-CORE (STS-1) ITU-T G.823 (E3) fulfilled exceeded. Figure Table show different input jitter specifications. frequency jitter called "wander", where defined border between jitter wander DS3/E3 STS-1.
Input Jitter Amplitude
pass fail
Jitter Frequency
F0085
Figure Table Reference
Jitter Tolerance Principle Input Jitter Requirements [UIPP] 0.15
def. def.
def.
2300 1000 10-5
22.3
[Hz]
def. def. def. def.
GR-499-CORE, Category GR-499-CORE, Category GR-253-CORE, Category ITU-T G.823 ETSI TBR24 ITU-T G.824
def. def.
0.15
def.
def.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
Jitter Amplitude [UI]
pass area
fail area
0,01 0,10
1,00
10,00
100,00
1000,00
10000,00
100000,00
1000000,00
Jitter Frequency [Hz] GR-499-CORE Cat. GR-499-CORE Cat. ITU-T G.823 ITU-T G.824 GR-253-CORE Cat. TE3-LIU TE3-LIU PUCCINI F0104 F0104
Figure
Jitter Tolerance
GR-499-CORE Jitter Tolerance Requirements (DS3) input jitter tolerance defined minimum amplitude sinusodial jitter given frequency that when modulating signal equipment input port results more than errored seconds 30-second measurement interval. Requirements input jitter tolerances then given terms jitter tolerance mask, which represents minimum acceptable jitter tolerances specified range jitter frequencies. There different jitter tolerance masks defined Category (SONET interfaces) Category (non-SONET interfaces) equipment. GR-253-CORE Jitter Tolerance Requirements (STS-1) Category interfaces, same requirements used defined GR-499-CORE. Category interfaces that specified having reduced jitter tolerance, shall tolerate, minimum, input jitter applied according mask given Table
4.1.8
Receive Output Jitter
intrinsic jitter receiver output signal RDOP/RDON/RCLK input jitter applied) DS3: STS-1: 0.06 0.08 0.10
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
Transmitter
serial stream then processed transmitter which following functions: generation AMI, B3ZS (DS3/STS-1) HDB3 (E3) coded signals all-ones generation (alarm indication signal)
4.2.1
Transmit Line Interface
received data stream pins XDIP (single rail data) XDIP/XDIN (dual rail data) converted into ternary signal which output pins XL2. mode HDB3 line code supported, DS3/STS-1 mode B3ZS supported.
TE3-LIU
F0079
Figure
Transmitter Configuration
Table Parameter
External Component Values Transmitter Characteristic Line Impedance STS-1 37.51) 372)
[pF]
This value refers ideal transformer without parasitics. transformer resistance other parasitic resistances have taken into account when calculating final value output serial resistors. This value includes parasitic capacitances secondary side transformer.
external components same DS3, STS-1 applications. Transmit return loss requirements defined fulfilled. Pulse mask
Preliminary Data Sheet 2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
requirements according ANSI T1.102 cross connect point, ft.) fulfilled.
Note: additional capacitor primary secondary side transformer required some applications improve pulse mask, parasitic capacitances very small.
Table
Transmit Return Loss Frequency Range Return Loss [kHz] 1720 51550
from [kHz] 1720
[dB]
measured with unframed PRBS pattern
4.2.2
Transmit Clock System
supplied transmit clock XCLK duty-cycle corrected internal circuit provide clock signal internal line driver unit. pulse shaper working frequency fourfold XCLK frequency. transmit clock XCLK failing, all-zero signal generated automatically. insertion selected, output signal referenced REFCLK.
XAIS
fnom REFCLK JATT XTAL1 XTAL2 disable testmode fnom fnom Transmit
Jitter Attenuator XAIS fnom
fnom
XCLK XDIP XDIN
Encoder
Insertion
Jitter Attenuator Buffer
Pulse Shaper
Line Driver
F0232
Figure
Transmit Clock System
2001-12-05
Preliminary Data Sheet
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.2.3
Jitter Attenuation
Jitter reduced transmit direction, jitter attenuator activated (JATT JATT control signal enables/disables jitter attenuation activates/bypasses buffer. jitter attenuator consists buffer PLL. jitter attenuation delivers "jitter free" clock (nominal frequency divided Table transmit which generates buffer read clock. jitter attenuation uses pullable crystal supports tuning range ppm. jitter attenuator uses 64-bit dual rail buffer fulfills requirements GR-499CORE GR-253-CORE shown Figure This covers requirements ITUT G.751, G.752 G.755 well. avoid need high frequency crystal, reference clock jitter attenuation only third nominal frequency. detailed block diagram transmit clocking given Figure Table Jitter Attenuation Operation Frequencies Jitter Attenuation Input Frequency 44.736 51.840 34.368 Jitter Attenuation Output Frequency 14.912 17.280 11.456 Crystal Frequency
Operation mode
STS-1
14.912 17.280 11.456
Further requirements external crystal found Table page
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
dB/decade
Jitter Gain
ITU-T G.755 GR-499-CORE ITU-T G.751
TE3-LIU
ITU-T G.752 GR-253-CORE
1000
Jitter Frequency
10000 100000 15000
F0141
Figure
Jitter Attenuation Characteristic
4.2.4
Intrinsic Jitter
TE3-LIUtransmit generates output jitter which fulfills requirements specified Table below. Table Specification GR-499-CORE (DS3) ANSI T1.404 (DS3) GR-253-CORE (STS-1) ETSI TBR24 (E3)
Transmit Output Jitter Measurement Filter Bandwidth Lower Cutoff Upper Cutoff UIPP UIrms UIPP 0.05 UIPP UIPP UIrms UIPP 0.15 UIPP Output Jitter1)
Measured with maximum input jitter applied (see Figure 12).
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.2.5
Pulse Shaper
internal pulse shaper generates required pulse shapes STS-1 signals according ANSI T1.102, T1.404, Telcordia GR-499-CORE ITU-T G.703). specific pulse mask fulfilled crossconnect point distance transmitter (DS3 requirement). maximum line length between TE3-LIUtransmitter TE3-LIUreceiver 1100 coaxial cable AT&T type 728A, 734A 734D.
4.2.6 4.2.6.1
Transmit Line Coding Code
code defined dual rail data signal, where combinations ("0"), ("+1") ("-1") valid. Additionally subsequent "+1" "-1" bits allowed (bipolar violations). dual rail data stream passed transparently, even contains bipolar violations. single rail data stream encoded correct coded bipolar data stream without zero code suppression.
4.2.6.2
B3ZS Code
B3ZS line code each block three consecutive zeros replaced either replacements codes which 00V, where represents pulse which applies bipolar rule ("+1" "-1") represents bipolar violation (two consecutive "+1" "-1" bits). replacement code chosen that there number valid pulses between consecutive pulses avoid introduction component into analog signal. transmit line encoder detects three-zeros pattern sequences changes them appropriate replacement pattern. Although B3ZS coding normally used with single rail data, transmit line encoder accepts either dual rail single rail data. Bipolar violations incoming dual rail data stream converted valid data pulses.
4.2.6.3
HDB3 Code
HDB3 line code each block four consecutive zeros replaced either replacements codes which B00V 000V, where represents pulse which applies bipolar rule ("+1" "-1") represents bipolar violation (two consecutive "+1" "-1" bits). replacement code chosen that there number valid pulses between consecutive pulses avoid introduction component into analog signal. transmit line encoder detects three-zeros pattern sequences changes them appropriate replacement pattern.
Preliminary Data Sheet 2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
Although HDB3 coding normally used with single rail data, transmit line encoder accepts either dual rail single rail data. Bipolar violations incoming dual rail data stream converted valid data pulses.
4.2.7
Insertion
unframed all-ones signal inserted into transmitted data stream. fulfill required accuracy, reference clock needed REFCLK. local loop configuration insertion selected together, signal looped back RDOP/RDON.
Framer Interface
interface receive framer realized RDOP, RDON RCLK. Data RDOP/N clocked with either rising (RPE=1) falling edge (RPE=0) RCLK. Alternatively single rail signal selected output RDOP (DR/SR=0). Bipolar violation indications output RDON/BPV this case. Data from framer interface sampled XDIP XDIN active edge XCLK. active edge rising (XPE=1) falling edge (XPE=0) XCLK. Alternatively single rail signal used XDIP (DR/SR=0).
Note: Selection dual rail/single rail mode common receive transmit direction.
Figure page Figure page details.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.4.1
Maintenance Functions Remote Loop
remote loopback mode clock data recovered from line inputs RL1/2 routed back line outputs XL1/2. normal mode they also processed synchronizer then sent framer interface. Data passes decoder encoder circuit. recovered receive clock used drive transmit pulse shaper.
Noise Crosstalk Filter
Equalizer
Clock Data Recovery
Decoder
RDON RDOP RCLK
Remote Loop
Line Driver
Pulse Shaper
Jitter Attenuator
Encoder
XDIN XDIP XCLK
F0083
Figure
Remote Loop Signal Flow
Note: remote loop local loop selected simultaneously, device will into power down mode. Note: jitter attenuator switched optionally.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Interface Description
4.4.2
Local Loop
local loopback mode disconnects receive lines RL1/2 from receiver. Instead signals coming from line data provided system interface routed through analog receiver back framer interface. transmit stream sent transmit line unchanged. XAIS=1 selected, transmit data stream replaced all-ones signal looped back.
Noise Crosstalk Filter
Equalizer
Clock Data Recovery
Decoder
RDON RDOP RCLK
Local Loop
Line Driver
Pulse Shaper
Jitter Attenuator
Encoder
XDIN XDIP XCLK
F0084
Figure
Local Loop Signal Flow
Note: remote loop local loop selected simultaneously, device will into power down mode. Note: jitter attenuator switched optionally.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Operational Description
Operational Description
Operational Overview
TE3-LIUcan operated three principle modes, which either STS-1 mode. This basic operation mode selection stable before reset signal goes inactive. device programmable selection. Direct connection microprocessor data possible using chip select (CS) write strobe.
Device Reset
TE3-LIUis forced reset state signal input (for minimum period page 42). During reset, output stages high impedance state, internal flip-flops reset. basic device mode (DS3, STS-1 jitter attenuation) selected during reset enable internal PLLs adjust. After reset control input values cleared. default control values (driven internal pullups) activated after applied first time after reset.
Device Power Down
TE3-LIUcan into power down state reduce power consumption, active. Power down mode selected setting RL=LL=1. Receive transmit circuits switched including internal PLLs transmit line driver. Recovery from power down mode achieved clearing either and/or After recovery from power down, internal PLLs need stabilize again. REFCLK must active recover from power down mode. Internal pullup resistors switched during power down prevent open input lines from floating.
Note: switching directly from local loop remote loop vice versa, make sure that there signal overlap, which would device into power down mode unintentionally.
Transmit Line Inactive
transmitter used, switched into inactive mode setting XLT=1. During inactive state common mode voltage output XL2. transmit stopped output enabled again XLT=0 without wait time.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
Table Parameter
Electrical Characteristics
Absolute Maximum Ratings
Maximum Ratings Symbol Limit Values Unit
Ambient temperature under bias Storage temperature supply voltage (digital) supply voltage receive (analog) supply voltage transmit (analog) Voltage output with respect ground Voltage input with respect ground robustness1) HBM:
Tstg VDDR VDDX
VESD,HBM 2000
According MIL-Std 883D, method 3015.7 Ass. Standard EOS/ESD-5.1-1993.
Note: Stresses above those listed here cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
Table Parameter
Operating Range
Power Supply Range Symbol Limit Values min. max. 3.46 3.13 Unit Condition
Ambient temperature Supply voltage
Digital input voltages Ground
VDDR VDDX VDDRP VDDXP VSSR VSSX VSSRP VSSXP
5.25
Note: operating range, functions given circuit description fulfilled. pins have connected same voltage level, pins have connected ground level. Note: Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply 3.3V supply voltage.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
Table Parameter
Characteristics
Parameters Symbol Limit Values min. max. 5.25 0.45 (typ.) Unit Notes
Input voltage Input high voltage Output voltage Output high voltage Average power supply current
mA1)
typical (DS3, PRBS, JATT enabled, worst case (STS-1, JATT enabled, AIS, 3.46
(typ.)
Input leakage current Input leakage current Input pullup current Input pulldown current Transmitter leakage current
IIL11 IIL12 IIPU IIPU
(typ.) (typ.)
VDD2) VSS2)
XL1/2 VDDX, XL1/2 VSSX, XL1/2 1.50 V3), applies XL1and XL24)
Transmitter output impedance
(typ.) VDDR+0. tbd.
Differential peak voltage mark XL1/XL2) Receiver differential peak voltage mark RL1/RL2)
RL1,
Receiver input impedance
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Table Parameters (cont'd) Symbol Limit Values min. Receiver sensitivity Analog loss Signal threshold
Electrical Characteristics
Parameter (cont'd)
Unit Notes RL1,
max. tbd.
SRSH VLOS3
applies output pins except analog pins XL1/XL2 Input leakage currents pins containing internal pullup devices measured testmode which switches pullups. test against common mode voltage, parameter tested production parameter tested production
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
6.4.1
Characteristics Reset
DS3/E3 DS3/STS-1 JATT (PLLs tuned)
F0095
Figure Table
Reset Timing Reset Timing Parameter Values Limit Values min. max. 1000 Unit
Parameter pulse width DS3/E3, DS3/STS-1, JATT setup time startup time
Note: REFCLK must active during reset.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
6.4.2
Reference Clock
REFCLK
F0107
Figure Table
Reference Clock Timing REFCLK Timing Parameter Values Limit Values min. typ. 29.1 22.4 19.3 202) max. Unit
Parameter REFCLK period REFCLK period REFCLK period STS-1
REFCLK high REFCLK REFCLK rise time REFCLK fall time Clock accuracy
tested production
DS3-AIS function required, sufficient guarantee correct receive function
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
6.4.3
Jitter Attenuator Reference Clock
XTAL1
F0164
Figure
XTAL Clock Timing XTAL Timing Parameter Values Limit Values min. typ. 87.29 67.06 57.87 max. Unit
Table
Parameter XTAL1/2 period XTAL1/2 period XTAL1/2 period STS-1
XTAL1
TE3-LIUXTAL2
DS3: 14.912 STS-1: 17.280 11.456
F0245
Figure
Recommended Crystal Circuit
2001-12-05
Preliminary Data Sheet
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
+200 +150 pulling range
F0259
[ppm]
+100 -100 -150 -200 nominal value
Load Capacitance CLeff [pF]
Figure Table
Crystal Pulling Range XTAL Crystal Parameter Values Limit Values min. typ. 14.912 17.280 11.456
Parameter Crystal nominal frequency Crystal nominal frequency STS-1 Crystal nominal frequency
Unit
max.
Crystal motional capacitance Crystal shunt capacitance Crystal load capacitance CLeff Crystal resonance resistance Internal parasitic load capacitance CLint
This value includes capacitance external capacitors (CLext) plus internal (CLint) external parasitic capacitances (CLpara). value external capacitor chosen depending printed circuit board layout. typical value should adapted parasitics achieve symmetrical pulling range.
Note: Leff Lext CLint CLpara Lext
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
6.4.4
Microprocessor Control
Control Signal
F0097
Figure Table
Chip Select Timing Chip Select Timing Parameter Values Limit Values min. max. TRCLK STS-1 TRCLK STS-1 Unit
Parameter pulse width
pulse width high
Control Signal Setup Time Control Signal Hold Time
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
6.4.5
Transmit Input Timing
XCLK (XPE=0) XCLK (XPE=1) data change edge XDIP, XDIN
F0090
Figure Table
XCLK Input Timing XCLK Timing Parameter Values Limit Values min. typ. 29.1 22.4 19.3 202) max. Unit
Parameter XCLK period XCLK period XCLK period STS-1
XCLK high XCLK XDIP, XDIN setup time XDIP, XDIN hold time XDIP, XDIN, XCLK rise time XDIP, XDIN, XCLK fall time Clock accuracy
tested production
DS3-AIS function required, sufficient guarantee correct function
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
6.4.6
Receive Output Timing
RCLK (RPE=0) RCLK (RPE=1) RDOP, RDON data change edge
F0108
Figure Table
RCLK Output Timing RCLK Timing Parameter Values Limit Values min. typ. 29.11) 22.41) 19.31) max. Unit
Parameter RCLK period RCLK period RCLK period STS-1
RCLK high RCLK RDOP, RDON delay time RDOP, RDON, RCLK rise time RDOP, RDON, RCLK fall time
tested production
applies only while receiver locked valid signal RL1/RL2, e.g., case
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
6.4.7 6.4.7.1
Pulse Templates Pulse Template
(14.55 2.45)
8.65 (14.55 5.90) Nominal pulse 14.55
12.1 (14.55 2.45)
24.5
(14.55 9.95)
29.1 (14.55 14.55)
T1818860-92
FIGURE 17/G.703
Pulse mask 368-kbit/s interface
F0076
Figure Table
Pulse Shape Transmitter Output Pulse Mask1) Limit Values min. typ. 14.55 0.95 0.95 1.05 1.05 max. Unit
Parameter Nominal peak voltage mark (pulse) Peak voltage space pulse) Nominal pulse width Amplitude ratio positive negative pulses2) Pulse width ratio positive negative pulses3)
measured output port without transmission line load; sequence: center pulse interval nominal half amplitude
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
6.4.7.2
Pulse Template
Normalized Amplitude
GR-499-CORE
ANSI T1.404
-0.2 -1.0 -0.5 Time [unit intervals]
F0077
Figure Table
Pulse Shape Cross Connect Point (450 ft.) Pulse Mask (ANSI T1.404, GR-499-CORE)1) Absolute Voltage Level (100 Value) min. 0.36 max. 0.85
sequence:
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Table Pulse Mask (ANSI T1.404) Lower Curve Time -0.36 -0.36 +0.36 +0.36 Equation -0.03
Electrical Characteristics
0.18
0.03
-0.03
Upper Curve Time -0.68 -0.68 +0.36 +0.36 Equation +0.03
T0.5 0.34
0.03
0.05 0.407 -1.84 0.36
Table
Pulse Mask (GR-499-CORE) Lower Curve Time -0.85 -0.36 -0.36 +0.36 +0.36 +1.4 Upper Curve Time -0.85 -0.68 -0.68 +0.36 +0.36 +1.4 Equation +0.03 T0.5 0.34 0.03 Equation -0.03 0.18 -0.03 0.03
0.08 0.407 -1.84 0.36
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
6.4.7.3
Pulse Template STS-1
Normalized Amplitude
-0.2 -1.0 -0.5 Time [unit intervals]
F0109
Figure Table
STS-1 Pulse Shape Cross Connect Point (450 ft.) STS-1 Pulse Mask Signal Power min. max.
sequence: (+1)0(-1)0(+1)0(-1).
Table
STS-1 Pulse Mask (ANSI T1.102) Lower Curve Time -0.85 -0.38 -0.38 +0.36 +0.36 +1.4 Equation -0.03
0.18
0.03
-0.03
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
Upper Curve Time -0.85 -0.68 -0.68 +0.26 +0.26 +1.4 Equation +0.03
T0.5 0.34
0.03
0.61 -2.4 0.26
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
Table Parameter Input
Capacitances
Capacitances Symbol COUT COUT Limit Values min. capacitance1) capacitance1) max. except XL1, XL1, Unit Notes
Output capacitance1) Output
tested production
Package Characteristics
F0051
Figure Table Parameter
Thermal Behavior Package Package Characteristic Values Symbol RthJA RthJC Limit Values min. typ. max. single layer PCB, 30%/11 metallization, convection Unit Notes
Thermal Resistance1) Junction Ambient Thermal Resistance2) Junction Case Junction Temperature
RthJA junction Tambient)/Power tested production RthJC (Tjunction Tcase)/Power tested production
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Electrical Characteristics
Test Configuration
Test Level
External Load
Device under Test Timing Test Points
Drive Levels
F0206
Figure Table Parameter
Input/Output Waveforms Testing Test Conditions Symbol Test Values VDD/2 Unit Notes digital outputs except RDOP, RDON, RCLK digital outputs RDOP, RDON RCLK analog line output XL1, except RL1, except RL1, except XL1, XL1, tested production
Load Capacitance Load Capacitance Load Capacitance Input Voltage high Input Voltage Test Voltage Output Test Load Rise Times Fall Times
Note: Typical characteristics mean values expected over production spread. specified otherwise, typical characteristics apply 3.3V. Note: Capacitance values include parasitics caused board layout, transformer etc.
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Package Outlines
Package Outlines
P-MQFP-44-2 (Plastic Metric Quad Flat Package)
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information". Surface Mounted Device
Dimensions
Preliminary Data Sheet
2001-12-05
GPM05622
3452 TE3-LIU V1.3
PRELIMINARY Appendix
Appendix
Cable Characteristics
Cable characteristics defined ANSI T1.102 shown below.
Office Cable Loss (450 coaxial)
Insertion Loss [dB]
Frequency [MHz]
Office Cable Insertion Phase (450 coaxial)
Insertion Phase [deg]
Frequency [MHz]
F0105 V1.1
Figure
Cable Characteristics
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY Appendix
Application Example
following picture shows typical application circuit (excluding surge protection).
Jitter Attenuation Reference
XTAL1/2 VDDRP/VSSRP
VDDR/VSSR
DS3/STS-1/E3 Receive Line Interface
RL1/2
Receive Path
RDOP RDON RCLK
DS3/STS-1/E3 Framer/Mapper Receive Interface
TE3-LIUV1.3
DS3/STS-1/E3 Transmit Line Interface XDIP XDIN XCLK DS3/STS-1/E3 Framer/Mapper Transmit Interface
XL1/2
Transmit Path
VDDXP/VSSXP
VDDX/VSSX VDD/VSS REFCLK TEST
Reference Clock
N.C. Control Interface
F0233
Figure
Application Circuit
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY
Index
Ambient temperature ANSI Applications
Loss Signal
MIL-Std 883D
Operating Range Output Jitter
B3ZS buffer
Package P-MQFP-44-2 Power Down Power Supply Pulse Shaper Pulse Template Pulse Template Pulse Template STS-1
Cable Clock Clock Data Recovery crystal
Edge Selection External Component Values
RCLK Receive Clock Receive Data Receive Line Interface Receive Return Loss Receiver Reference Clock Remote Loop Reset
HDB3
Input Jitter international standards intrinsic jitter ITU-T
Supply voltage
JATT Jitter Attenuation Jitter Tolerance
Controller Temperature Thermal Behaviour Transmit Clock Transmit Data Transmit Line Transmit Line Interface
Line Coding Line Monitoring Local Loop
Preliminary Data Sheet
2001-12-05
3452 TE3-LIU V1.3
PRELIMINARY
wander
XCLK XTAL
Preliminary Data Sheet
2001-12-05
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Edition 2001-12-05 Published Infineon Technologies St.-Martin-Strasse

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