DP83902A ST-NIC Serial Network Interface Controller Twisted Pair
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DP83902A ST-NIC Serial Network Interface Controller Twisted Pair
DP83902A ST-NIC Serial Network Interface Controller Twisted Pair
General Description
DP83902A Serial Network Interface Controller Twisted Pair (ST-NIC) microCMOS VLSI device designed easy implementation CSMA local area networks These include Ethernet (10BASE5) Thin Ethernet (10BASE2) Twisted-pair Ethernet (10BASE-T) overall ST-NIC solution provides Media Access Control (MAC) Encode-Decode (ENDEC) with interface 10BASE-T transceiver functions accordance with IEEE standards DP83902A's 10BASE-T transceiver fully complies with IEEE standard This functional block incorporates receiver transmitter collision heartbeat loopback jabber link integrity blocks defined standard transceiver when combined with equalization resistors transmit receive filters pulse transformers provides complete physical interface from DP83902A's ENDEC module twisted pair medium integrated ENDEC module allows Manchester encoding decoding differential transceiver phase lock loop decoder Mbit Also included collision detect translator diagnostic loopback capability ENDEC module interfaces directly transceiver module also provides fully IEEE compliant (Attachment Unit Interface) connection other media transceivers (Continued)
Features
Single chip solution IEEE 10BASE-T Integrated controller ENDEC transceiver Full interface external precision components required levels loopback supported Transceiver Module Integrates transceiver electronics including Transmitter receiver Collision detect heartbeat jabber timer Link integrity test Link disable polarity detection correction Integrated smart receive squelch Reduced squelch level extended distance cable operation (100-pin version) ENDEC Module Manchester encoding decoding plus clock recovery Transmitter half full step mode Squelch receive collision pairs Lock time bits typical Decodes Manchester data with jitter Controller Module 100% DP8390 software hardware compatible Dual 16-bit channels 16-byte internal FIFO Efficient buffer management implementation Independent system network clocks Supports physical multicast broadcast address filtering Network statistics storage
System Diagram
Station
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TRI-STATE registered trademark National Semiconductor Corporation ST-NICis trademark National Semiconductor Corporation C1995 National Semiconductor Corporation 11157 RRD-B30M115 Printed
General Description (Continued)
Media Access Control function which provided Network Interface Control module (NIC) provides simple efficient packet transmission reception control means unique dual channels internal FIFO arbitration memory control logic integrated reduce board cost area overheads DP83902A provides comprehensive single chip solution 10BASE-T IEEE networks designed easy interface other transceivers interface inherent constraints CMOS processing isolation required differential signal interface 10BASE5 10BASE2 applications Capacitive inductive isolation used
Table Contents
SYSTEM DIAGRAM DESCRIPTION BLOCK DIAGRAM FUNCTIONAL DESCRIPTION TRANSMIT RECEIVE PACKET ENCAPSULATION DECAPSULATION DIRECT MEMORY ACCESS CONTROL (DMA) PACKET RECEPTION PACKET TRANSMISSION REMOTE INTERNAL REGISTERS INITIALIZATION PROCEDURES LOOPBACK DIAGNOSTICS ARBITRATION TIMING PRELIMINARY ELECTRICAL CHARACTERISTICS SWITCHING CHARACTERISTICS TIMING TEST CONDITIONS PHYSICAL DIMENSIONS
Connection Diagrams
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Order Number DP83902AV Package Number V84A
Connection Diagrams (Continued)
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Order Number DP83902AVLJ Package Number VLJ100A
Connection Diagrams (Continued)
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Order Number DP83902AVJG Package Number VJG100A
Description
PQFP PLCC AVJG Name Description INTERFACE PINS INTERRUPT Indicates that DP83902A requires attention after reception transmission completion transfers interrupt cleared writing (Interrupt Status Register) interrupts maskable WRITE ACKNOWLEDGE Issued from system DP83902A indicate that data been written external latch DP83902A will begin write cycle place data local memory PORT READ Enables data from external latch local during memory write cycle local memory (remote write operation) This allows asynchronous transfer data from system memory local memory REGISTER ADDRESS These four pins used select register read written state these inputs ignored when DP83902A slave mode high)
WACK
98-100
RA3-RA0
Description (Continued)
PQFP PLCC AVJG Name Description INTERFACE PINS (Continued) 12-23 28-31 9-15 20-23 AD0- AD15 MULTIPLEXED ADDRESS DATA Register Access with inactive returned from DP83902A pins AD0-AD7 used read write register data AD8- AD15 float during transfers pins used select direction transfer Master with BACK input asserted During memory cycle AD15 contain address During AD15 contain data (word transfer mode) During AD0-AD7 contain data AD8-AD15 contain address (byte transfer mode) Direction transfer indicated DP83902A lines ADDRESS STROBE Input with inactive latches RA0-RA3 inputs falling edge high data present RA0-RA3 will flow through latch Output When Master latches address bits (AD0-AD15) external memory during transfers CHIP SELECT Chip Select places controller slave mode access internal registers Must valid through data portion cycle used select internal register select direction data transfer MASTER WRITE STROBE (Strobe transfers) Active during write cycles buffer memory Rising edge coincides with presence valid output data TRI-STATE until BACK asserted MASTER READ STROBE (Strobe transfers) Active during read cycles buffer memory Input data must valid rising edge TRI-STATE until BACK asserted SLAVE WRITE STROBE Strobe from write internal register selected Data latched into DP83902A rising edge this input SLAVE READ STROBE Strobe from read internal register selected register data output when goes ACKNOWLEDGE Active when DP83902A grants access Used insert WAIT states until DP83902A synchronized register read write operation CLOCK This clock used establish period memory cycle Four clock cycles used cycle transfers extended BSCK increment using READY input READ ACKNOWLEDGE Indicates that system host read data placed external latch DP83902A DP83902A will begin read cycle update latch PORT WRITE Strobe used latch data from DP83902A into external latch transfer host memory during Remote Read transfers rising edge coincides with presence valid data local READY This high insert wait states during transfer DP83902A will sample this signal during transfers PORT REQUEST ADDRESS STROBE 32-BIT MODE Data Configuration Register this line programmed ADS1 used strobe addresses into external latches (A16 fixed addresses stored RSAR0 RSAR1) ADS1 will remain TRI-STATE until BACK received 16-BIT MODE Data Configuration Register this line programmed used Remote Transfers DP83902A initiates single remote read write operation asserting this this mode will standard logic output
Note This line will power TRI-STATE until Data Configuration Register programmed
ADS0
BSCK
RACK
READY ADS1
Description (Continued)
PQFP PLCC AVJG Name Description INTERFACE PINS (Continued) BACK ACKNOWLEDGE Acknowledge active high signal indicating that granted DP83902A immediate access desired BREQ should tied BACK Tying BACK will result deadlock REQUEST Request active high signal used request transfers This signal automatically generated when FIFO needs servicing RESET Reset active places DP83902A reset mode immediately packets transmitted received DP83902A until Affects Command Register Interrupt Mask Register Data Configuration Register Transmit Configuration Register DP83902A will execute reset within BSCK cycles POLARITY active high output This signal normally state When module detects seven consecutive link pulses three consecutive received packets with reversed polarity asserted TRANSMIT ENABLE TRANSMIT active high output asserted approximately whenever DP83902A transmits data either modes COLLISION active high output asserted approximately whenever DP83902A detects collision either modes FACTORY TEST INPUT Used check chip's internal functions This should tied during normal operation TWISTED PAIR TRANSMIT OUTPUTS These high drive CMOS level outputs resistively combined external chip produce differential output signal with equalization compensate Intersymbol Interference (ISI) twisted pair medium TWISTED PAIR RECEIVE INPUTS These inputs feed differential amplifier which passes valid data ENDEC module GOOD LINK LINK DISABLE This dual function both input output function latched DP83902A rising edge Reset signal chip returning normal operation after reset output this configured open drain N-channel device suitable driving will latched output removal chip reset connected left open circuit Under normal conditions (the twisted pair link broken) output will will open drain output will switched twisted pair link been detected broken recommended that color green This output will pulled high mode internal resistor approximately When this which internal pull-up resistor tied becomes input link integrity checking disabled SQUELCH SELECT This selects module input squelch thresholds When tied input squelch threshold inputs complies 10BASE-T specification When high input operates with reduced squelch levels allowing with longer lengths cable cable with higher losses this left unconnected internal pulldown causes ST-NIC's default higher squelch level This level signal buffered version oscillator suitable drive external logic EXTERNAL OSCILLATOR INPUT GROUND oscillator used this should tied ground crystal used this should tied directly crystal MODE SELECT When high same voltage idle state When Transmit positive with respect Transmitb idle state transformer's primary
BREQ
RESET
NETWORK INTERFACE PINS
TEST TXOdb TXOb TXOd RXIb GDLNK LNKDIS
SQSEL
Description (Continued)
PQFP PLCC AVJG Name Description NETWORK INTERFACE PINS (Continued) SNISEL SELECT level active high input that selects either interface module interface with ENDEC module When high selected when selected TRANSMIT OUTPUT Differential driver which sends encoded data transceiver outputs source followers which require 270X pulldown resistors RECEIVE INPUT Differential receive input pair from transceiver COLLISION INPUT Differential collision pair input from transceiver FACTORY TEST INPUT normal operation tied When enables ENDEC module tested independently DP83902A module CARRIER SENSE RECEIVE level active high signal asserted approximately whenever valid transmit receive data detected while mode receive data detected while mode
POWER SUPPLY PINS (DIGITAL) POSITIVE SUPPLY PINS NEGATIVE (GROUND) SUPPLY PINS suggested that decoupling capacitor connected between pins SUPPLY Care should taken reduce noise this supplies power analog Phase Lock Loop GROUND SUPPLY Care should taken reduce noise this supplies ground analog Phase Lock Loop RECEIVE SUPPLY Power supplies Twisted Pair Interface Receiver RECEIVE GROUND Ground Twisted Pair Interface Receiver TRANSMIT SUPPLY Power supplies Twisted Pair Interface Transmitter TRANSMIT GROUND Ground Twisted Pair Interface Transmitter RECEIVE SUPPLY Power supplies Interface Receiver RECEIVE GROUND Ground Interface Receiver TRANSMIT SUPPLY Power supplies Interface Transmitter TRANSMIT GROUND Ground Interface Transmitter CONNECTION connect these pins
POWER SUPPLY PINS (ANALOG)
CONNECTION
Block Diagram
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FIGURE
Typical Connection Twisted Pair Cable
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Recommended integrated modules Pulse Engineering PE65431 Belfuse 0556-2006-01 0556-3392-00 Valor FL1012
ST-NIC Twisted Pair Interface
Functional Description (Refer Figure
TWISTED PAIR INTERFACE (TPI) MODULE
consists five main logical functions Smart Squelch responsible determining when valid data present differential receive inputs (RXI Collision function checks simultaneous transmission reception data pins Link Detector Generator checks integrity cable connecting twisted pair MAUs Jabber disables transmitter attempts transmit longer than legal packet Driver Pre-emphasis transmits Manchester encoded data twisted pair network summing resistors transformer filter SMART SQUELCH ST-NIC implements intelligent receive squelch differential inputs ensure that impulse noise receive inputs will mistaken valid signal squelch circuitry employs combination amplitude timing measurements determine validity data twisted pair inputs There squelch levels which selectable SQSEL mode 10BASE-T compatible second reduced squelch mode diagram shows 10BASE-T mode operation smart squelch signal start packet checked smart squelch pulses exceeding squelch level (either positive negative depending upon polarity) will rejected Once this first squelch level overcome correctly opposite squelch level must then exceeded within Finally signal must exceed original squelch level within further ensure that input waveform will rejected checking procedure results loss typically three bits beginning each packet Only after these conditions have been satisfied will control signal generated indicate remainder circuitry that valid data present this time smart squelch circuitry reset Valid data considered present until either squelch level been generated time longer than indicating Packet Once good data been detected squelch levels reduced minimize effect noise causing premature Packet detection reduced squelch mode functions same 10BASE-T mode except that only lower level used both turn-on turn-off COLLISION collision detected module when receive transmit channels active simultaneously receiving when collision detected reported controller immediately however transmitting when collision detected collision reported until seven bits have been received while collision state This prevents collision being reported incorrectly noise network signal controller remains duration collision Approximately after transmission each packet signal called Signal Quality Error (SQE) consisting typically cycles generated This signal also called Heartbeat ensures continued functioning collision circuitry LINK DETECTOR GENERATOR link generator timer circuit that generates link pulse defined 10BASE-T specification that will generated transmitter section pulse which wide transmitted output every absence transmit data pulse used check integrity connection remote link detection circuit checks valid pulses from remote valid link pulses received link detector will disable transmit receive collision detection functions GDLNK output directly drive show that there good twisted pair link normal conditions will link integrity function disabled described Description Section JABBER jabber timer monitors transmitter disables transmission transmitter active greater than transmitter then disabled whole time that ENDEC module's internal transmit enable asserted This signal deasserted approximately (the unjab time) before Jabber re-enables transmit outputs TRANSMIT DRIVER transmitter consists four signals true complement Manchester encoded data (TXO these signals delayed (TXOd
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Functional Description (Continued) These four signals resistively combined with TXOdb TXOb with TXOd This known digital pre-emphasis required compensate twisted pair cable which acts like pass filter causing greater attenuation pulses Manchester encoded waveform than (100 pulses example these signals combined shown following diagram
Transmitb during idle with high (for IEEE Transmit Transmitb equal idle state This provides zero differential voltage operate with transformer coupled loads MANCHESTER DECODER decoder consists differential receiver separate Manchester decoded data stream into internal clock signals data differential input must externally terminated with resistors connected series standard transceiver drop cable used thin Ethernet applications these resistors optional prevent noise from falsely triggering decoder squelch circuit input rejects signals with levels less than Signals more negative than decoded Data becomes valid typically within times DP83902A tolerate jitter received data decoder detects frame when more mid-bit transitions detected COLLISION TRANSLATOR When mode when Ethernet transceiver (DP8392 CTI) detects collision generates signal differential collision inputs DP83902A When these inputs detected active DP83902A uses this signal back current transmission reschedule another collision differential inputs terminated same differential receive inputs squelch circuitry also similar rejecting pulses with levels less than b175
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signal with pre-emphasis shown above generated resistively combining TXOdb This signal along with complement passed transmit filter STATUS INFORMATION Status information provided ST-NIC outputs described description table These outputs suitable driving status LEDs appropriate driver circuit output normally will driven high when seven consecutive link pulses three consecutive receive packets detected with reversed polarity polarity reversal caused wiring error either cable detection polarity reversal condition latched asserted corrects this error internally will decode received data correctly eliminating need correct wiring error
CRYSTAL OSCILLATOR OPERATION
OCSILLATOR oscillator controlled parallel resonant crystal connected between external clock output oscillator divided generate transmit clock controller oscillator also provides internal clock signals encoding decoding circuits
Note When being driven external oscillator MUST grounded
Crystal Specifications Resonant Frequency Tolerance Stability Type Circuit Crystal Load Capacitor
005% 005%
ENCODER DECODER (ENDEC) MODULE
ENDEC consists three main logical blocks Manchester encoder accepts data from controller encodes data Manchester transmits differentially transceiver through differential transmit driver Manchester decoder receives Manchester data from transceiver converts data clock pulses sends controller collision translator indicates controller presence valid collision signal MANCHESTER ENCODER DIFFERENTIAL DRIVER differential transmit pair secondary transformer drives meters twisted pair cable These outputs source followers which require 270X pull-down resistors ground DP83902A allows both half-step full-step compatible with Ethernet IEEE With (for Ethernet Transmit positive with respect
Parallel Resonance
crystal connection DP83902 requires special care IEEE standard requires transmitted signal frequency accurate within Stray capacitance shift crystal's frequency range cause transmitted frequency exceed tolerance frequency marked crystal usually measured with fixed load capacitance specified crystal's data sheet typically
Functional Description (Continued)
order prevent distortion transmitted frequency total capacitance seen crystal should equal total load capacitance standard parallel set-up shown diagram below load caps should equal spec load (due capacitors acting series) less stray capacitances Thus trim capacitors required calculated follows 2XC1b(Cb1 Cd1) Where Board 2XC1b(Cb2 Cd2) Where Board value STNIC pins region ADDRESS RECOGNITION LOGIC address recognition logic compares Destination Address Field (first bytes received packet) Physical address registers stored Address Register Array bytes does match pre-programmed physical address Protocol Control Logic rejects packet multicast destination addresses filtered using hashing technique (See register description multicast address indexes that been filter array Multicast Address Register Array packet accepted otherwise rejected Protocol Control Logic Each destination address also checked which reserved broadcast address FIFO OPERATIONS Overview accommodate different rates which data comes from goes network goes comes from) system memory ST-NIC contains 16-byte FIFO buffering data between media FIFO threshold programmable When FIFO filled programmed threshold local channel transfers these bytes words) into local memory crucial that local given access within minimum latency time otherwise FIFO underrun overrun) occurs FIFO underruns overruns caused conditions latency long that FIFO filled emptied) from network before local serviced FIFO latency slowed throughput local point where slower than network data rate Mbit sec) This second condition also dependent upon clock word width (byte wide word wide) worst case condition ultimately limits overall latency which ST-NIC tolerate Beginning Receive beginning reception ST-NIC stores entire Address field each incoming packet FIFO determine whether address matches ST-NIC's Physical Address Registers maps Multicast Registers This causes FIFO accumulate bytes Furthermore there some synchronization delays Thus actual time when BREQ asserted from time Start Frame Delimiter (SFD) detected This operation affects latencies 4-byte thresholds during first receive BREQ since FIFO must filled bytes words) before issuing BREQ Receive When packet detected ENDEC module ST-NIC enters packet processing sequence emptying FIFO writing status information beginning packet ST-NIC holds onto entire sequence longest time BREQ extended occurs when packet ends just ST-NIC performs last FIFO burst ST-NIC this case performs programmed burst transfer followed flushing remaining bytes FIFO completes writing header information memory following steps occur during this sequence ST-NIC issues BREQ because FIFO threshold been reached During burst packet ends resulting BREQ extended
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(Media Access Control) MODULE
RECEIVE DESERIALIZER Receive Deserializer activated when input signal Carrier Sense asserted allow incoming bits shifted into shift register receive clock serial receive data also routed generator checker Receive Deserializer includes synch detector which detects (Start Frame Delimiter) establish where byte boundaries within serial stream located After every eight receive clocks byte wide data transferred 16-byte FIFO Receive Byte Count incremented first bytes after checked valid comparison Address Recognition Logic Address Recognition Logic does recognize packet FIFO cleared GENERATOR CHECKER During transmission logic generates local field transmitted sequence encodes fields after shifted first following last transmit byte During reception logic generates field from incoming packet This local serially compared incoming appended packet transmitting node local received match specific pattern will generated decoded indicate data errors Transmission errors result different pattern detected resulting rejection packet programmed) TRANSMIT SERIALIZER Transmit Serializer reads parallel data from FIFO serializes transmission serializer clocked transmit clock generated internally serial data also shifted into generator checker beginning each transmission Preamble Synch Generator append bits preamble synch pattern After last data byte packet been serialized 32-bit field shifted directly generator event collision Preamble Synch generators used generate 32-bit pattern
Functional Description (Continued)
ST-NIC flushes remaining bytes from FIFO ST-NIC performs internal processing prepare writing header ST-NIC writes 4-byte (2-word) header ST-NIC de-asserts BREQ FIFO Threshold Detection assure that overwriting data FIFO FIFO logic flags FIFO overrun 13th byte written into FIFO effectively shortening FIFO bytes FIFO logic also operates differently Byte Mode Word Mode Byte Mode threshold indicated when byte entered FIFO thus with 8-byte threshold ST-NIC issues Request (BREQ) when byte entered FIFO Word Mode BREQ generated until bytes have entered FIFO Thus with word threshold (equivalent 8-byte threshold) BREQ issued when 10th byte entered FIFO Beginning Transmit Before transmitting ST-NIC performs prefetch from memory load FIFO number bytes prefetched programmed FIFO threshold next BREQ issued until after ST-NIC actually begins transmitting data after Reading FIFO During normal operation FIFO must read ST-NIC will issue ACKnowledge back FIFO read FIFO should only read during loopback diagnostics PROTOCOL protocol responsible implementing IEEE protocol including collision recovery with random backoff Protocol also formats packets during transmission strips preamble synch during reception BUFFER CONTROL LOGIC Buffer Control Logic used control 16-bit channels During reception local stores packets receive buffer ring located buffer memory During transmission Local uses programmed pointer length registers transfer packet from local buffer memory FIFO second channel used slave transfer data between local buffer memory host system Local Remote internally arbitrated with Local channel having highest priority Both channels common external clock generate required timing External arbitration performed with standard request acknowledge handshake protocol
Transmit Receive Packet Encapsulation Decapsulation
standard IEEE packet consists following fields preamble Start Frame Delimiter (SFD) destination address source address length data Frame Check Sequence (FCS) typical format shown Figure packets Manchester encoded decoded ENDEC module transferred serially module using data with clock fields fixed length except data field ST-NIC generates appends preamble field during transmission Preamble fields stripped during reception (The passed through buffer memory during reception PREAMBLE START FRAME DELIMITER (SFD) Manchester encoded alternating preamble field used ENDEC acquire synchronization with incoming packet When transmitted each packet contains bits alternating preamble Some this preamble will lost packet travels through network preamble field stripped module Byte alignment performed with Start Frame Delimiter (SFD) pattern which consists consecutive ST-NIC does treat pattern byte detects only pattern This allows preceding preamble within used phase locking DESTINATION ADDRESS destination address indicates destination packet network used filter unwanted packets from reaching node There three types address formats supported ST-NIC physical multicast broadcast physical address unique address that corresponds only single node physical addresses have ``0'' These addresses compared internally stored physical address registers Each destination address must match order ST-NIC accept packet Multicast addresses begin with ``1'' ST-NIC filters multicast addresses using standard hashing algorithm that maps multicast addresses into 6-bit value This 6-bit value indexes 64-bit array that filters value address consists broadcast address indicating that packet intended nodes promiscuous mode allows reception packets destination address required match filters Physical broadcast multicast promiscuous address modes selected
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FIGURE
Transmit Receive Packet Encapsulation Decapsulation
(Continued) SOURCE ADDRESS source address physical address node that sent packet Source addresses cannot multicast broadcast addresses This field simply passed buffer memory LENGTH TYPE FIELD 2-byte length field indicates number bytes that contained data field packet This field interpreted ST-NIC DATA FIELD data field consists anywhere from 1500 bytes Messages longer than 1500 bytes need broken into multiple packets Messages shorter than bytes will require appending bring data field minimum length bytes data field padded number valid data bytes indicated length field ST-NIC does strip append bytes short packets check oversize packets FIELD Frame Check Sequence (FCS) 32-bit field calculated appended packet during transmission allow detection errors when packet received During reception error free packets result specific pattern generator Packets with improper will rejected AUTODIN (X32 polynomial used calculations
Direct Memory Access Control (DMA)
capabilities ST-NIC greatly simplify DP83902A typical configurations local channel transfers data between FIFO memory transmission packet DMAed from memory FIFO bursts Should collision occur times) packet retransmitted with processor intervention reception packets DMAed from FIFO receive buffer ring explained below) remote channel also provided ST-NIC accomplish transfers between buffer memory system memory channels alternatively combined form single 32-bit address with 16-bit data DUAL CONFIGURATION example configuration using both local remote channels shown below Network activity isolated local where ST-NIC's local channel performs burst transfers between buffer memory ST-NIC's FIFO Remote transfers data between buffer memory host memory bidirectional port Remote provides local addressing capability used slave host Host side addressing must provided host ST-NIC allows Local Remote operations interleaved SINGLE CHANNEL OPERATION desirable channels combined provide 32-bit address upper bits 32-bit address static used point kbyte word) page memory where packets received transmitted
Dual System
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Packet Reception
Local receive channel uses Buffer Ring Structure comprised series contiguous fixed length 256-byte (128 word) buffers storage received packets location Receive Buffer Ring programmed registers Page Start Page Stop Register Ethernet packets consist distribution shorter link control packets longer data packets 256-byte buffer length provides good compromise between short packets longer packets most efficiently memory addition these buffers provide memory resources storage back-to-back packets loaded networks assignment buffers storing packets controlled Buffer Management Logic ST-NIC Buffer Management Logic provides three basic functions linking receive buffers long packets recovery buffers when packet rejected recirculation buffer pages that have been read host initialization portion kbyte word) address space reserved receive buffer ring 8-bit registers Page Start Address Register (PSTART) Page Stop Address Register (PSTOP) define physical boundaries where buffers reside ST-NIC treats list buffers logical ring whenever address reaches Page Stop Address reset Page Start Address
ST-NIC Receive Buffer Ring
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Packet Reception (Continued)
INITIALIZATION BUFFER RING static registers working registers control operation Buffer Ring These Page Start Register Page Stop Register (both described previously) Current Page Register Boundary Pointer Register Current Page Register points first buffer used store packet used restore writing status Buffer Ring restoring address event Runt packet Frame Alignment error Boundary Register points first packet Ring read host local address ever reaches Boundary reception aborted Boundary Pointer also used initialize Remote removing packet advanced when packet removed simple analogy remember function these registers that Current Page Register acts Write Pointer Boundary Pointer acts Read Pointer
Note initialization Page Start Register value should loaded into both Current Page Register Boundary Pointer Register Note Page Start Register must initialized
BEGINNING RECEPTION When first packet begins arriving ST-NIC begins storing packet location pointed Current Page Register offset bytes saved this first buffer allow room storing receive status corresponding this packet
Buffer Ring Initialization
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Received Packet Enters Buffer Pages
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Packet Reception (Continued)
LINKING RECEIVE BUFFER PAGES length packet exhausts first 256-byte buffer performs forward link next buffer store remainder packet maximum length packet buffer logic will link buffers store entire packet Buffers cannot skipped when linking therefore packet will always stored contiguous buffers Before next buffer linked Buffer Management Logic performs comparisons first comparison tests equality between address next buffer contents Page Stop Register buffer address equals Page Stop Register buffer management logic will restore first buffer Receive Buffer Ring value programmed Page Start Address Register second comparison tests equality between address next buffer address contents Boundary Pointer Register values equal reception aborted Boundary Pointer Register used protect against overwriting area receive buffer ring that been read When linking buffers buffer management will never cross this pointer effectively avoiding overwrites buffer address does match either Boundary Pointer Page Stop Address link next buffer performed
Linking Receive Buffer Pages
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Check PSTOP Check Boundary
Packet Reception (Continued)
Buffer Ring Overflow Buffer Ring been filled reaches Boundary Pointer Address reception incoming packet will aborted ST-NIC Thus packets previously received still contained Ring will destroyed heavily loaded network which cause overflows Receive Buffer Ring ST-NIC disable local suspend further receptions even Boundary register advanced beyond Current register guarantee this will happen software reset must issued during Receive Buffer Ring overflows (indicated Interrupt Status Register) following procedure required recover from Receiver Buffer Ring Overflow this routine adhered ST-NIC unpredictable manner should also noted that permissible service overflow interrupt continuing empty packets from receive buffer without implementing prescribed overflow routine flow chart ST-NIC's overflow routine follows
Note necessary define variable driver which will called ``Resend''
ST-NIC once overflow routine completed step Also possible ST-NIC defer indefinitely when stopped busy network Step also alleviates this problem Step essential should omitted from overflow routine order ST-NIC operate correctly Overflow Routine Flow Chart
Read store value ST-NIC Command Register Issue STOP command ST-NIC This accomplished setting ST-NIC's Command Register Writing Command Register will stop ST-NIC Wait least Since ST-NIC will complete transmission reception that progress necessary time maximum possible duration Ethernet transmission reception waiting this achieved with some guard band added Previously recommended that Interrupt Status Register polled insure that pending transmission reception completed This reliable indicator subsequently should ignored Clear ST-NIC's Remote Byte Count registers (RBCR0 RBCR1) Read stored value from step above this value ``Resend'' variable jump step this value read ST-NIC's Interrupt Status Register either Packet Transmitted (PTX) Transmit Error (TXE) ``Resend'' variable jump step neither these bits place ``Resend'' variable jump step This step determines there transmission progress when stop command issued step there transmission progress ST-NIC's read determine whether packet recognized ST-NIC neither then packet will essentially lost retransmitted only after time-out takes place upper level software determining that packet lost driver level transmit command reissued
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Packet Reception (Continued)
Place ST-NIC either mode mode loopback This accomplished setting bits Transmit Configuration Register respectively Issue START command ST-NIC This accomplished writing Command Register This necessary activate ST-NIC's Remote channel Remove more packets from receive buffer ring Reset overwrite warning (OVW overflow) Interrupt Status Register Take ST-NIC loopback This done writing Transmit Configration Register with value contains during normal operation (Bits should both programmed ``Resend'' variable reset ``Resend'' variable reissue transmit command This done writing value Command Register ``Resend'' variable nothing needs done
Note Remote being used ST-NIC does need started before packets removed from receive buffer ring Hence step could done before step Note When ST-NIC STOP mode Missed Talley Counter disabled
Received Packet Aborted Hits Boundary
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Packet Reception (Continued)
Enabling ST-NIC Active Network After ST-NIC been initialized procedure disabling then re-enabling ST-NIC network similar handling Receive Buffer Ring overflow described previously Program Command Register page (Command Register 21H) Initialize Data Configuration Register (DCR) Clear Remote Byte Count Registers (RBCR0 RBCR1) Initialize Receive Configuration Register (RCR) Place ST-NIC LOOPBACK mode (Transmit Configuration Register 04H) Initialize Receive Buffer Ring Boundary Pointer (BNDRY) Page Start (PSTART) Page Stop (PSTOP) Clear Interrupt Status Register (ISR) writing 0FFH Initialize Interrupt Mask Register (IMR) Program Command Register page (Command Register 61H) Initialize Physical Address Registers (PAR0- PAR5) Initialize Multicast Address Registers (MAR0 MAR7) Initialize CURRent pointer ST-NIC START mode (Command Register 22H) local receive still active since ST-NIC LOOPBACK Initialize Transmit Configuration intended value ST-NIC ready transmission reception PACKET OPERATIONS packet ST-NIC determines whether received packet accepted rejected either branches routine store Buffer Header another routine that recovers buffers used store packet SUCCESSFUL RECEPTION packet successfully received restored first buffer used store packet (pointed Current Page Register) then stores Receive Status Pointer where next packet will stored (Buffer number received bytes Note that remaining bytes last buffer discarded reception next packet begins next empty 256-byte buffer boundary Current Page Register then initialized next available buffer Buffer Ring (The location next buffer been previously calculated temporarily stored internal scratchpad register
Termination Received Packet
Packet Accepted
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Packet Reception (Continued)
BUFFER RECOVERY REJECTED PACKETS packet runt packet contains Frame Alignment errors rejected buffer management logic resets back first buffer page used store packet (pointed CURR) recovering buffers that been used store rejected packet This operation will performed ST-NIC programmed accept either runt packets packets with Frame Alignment errors received always stored buffer memory after last byte received data packet Error Recovery packet rejected shown restored ST-NIC reprogramming starting address pointed Current Page Register
Termination Receive Packet
Packet Reject
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Packet Reception (Continued)
REMOVING PACKETS FROM RING Packets removed from ring using Remote external device When using Remote Send Packet command used This programs Remote automatically remove received packet pointed Boundary Pointer transfer ST-NIC moves Boundary Pointer freeing additional buffers reception Boundary Pointer also moved manually programming Boundary Register ST-NIC knows difference between empty buffer ring full buffer ring This situation seen when Boundary Pointer (BNDRY) Current Page Pointer (CURR) point same address BNDRY caught with CURR buffer empty CURR caught with BNDRY buffer full STORAGE FORMAT RECEIVED PACKETS following diagrams describe format received packets placed into memory local channel These modes selected Data Configuration Register AD15 Receive Status Receive Byte Count Byte AD15 Receive Status Receive Byte Count Byte Next Packet Pointer Receive Byte Count Byte
Data Configuration Register This format used with 680x0 type processors (Note Receive Count ordering remains same
Receive Status Next Packet Pointer Receive Byte Count Receive Byte Count Byte Byte
Data Configuration Register This format used with general 8-bit processors
Next Packet Pointer Receive Byte Count Byte
Data Configuration Register This format used with Series 32xxx 680x0 processors
Received Packet Removed Remote
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Packet Transmission
Local also used during transmission packet Three registers control transfer during transmission Transmit Page Start Address Register (TPSR) Transmit Byte Count Registers (TBCR0 When ST-NIC receives command transmit packet pointed these registers buffer memory data will moved into FIFO required during transmission ST-NIC will generate append preamble synch fields General Transmit Packet Format Transmit Byte Count TBCR0 Destination Address Source Address Type Length Data Data Bytes) Bytes Bytes Bytes
Bytes
TRANSMIT PACKET ASSEMBLY FORMAT following diagrams describe format packets must assembled prior transmission different byte ordering schemes various formats selected Data Configuration Register Destination Address Destination Address Destination Address Source Address Source Address Source Address Type Length Data
Data Configuration Register
Destination Address Destination Address Destination Address Source Address Source Address Source Address Type Length Data
TRANSMIT PACKET ASSEMBLY ST-NIC requires contiguous assembled packet with format shown transmit byte count includes Destination Address Source Address Length Field Data does include preamble When transmitting data smaller than bytes packet must padded minimum size bytes programmer responsible adding stripping bytes TRANSMISSION Prior transmission TPSR (Transmit Page Start Register) TBCR0 TBCR1 (Transmit Byte Count Registers) must initialized initiate transmission packet Command Register Transmit Status Register (TSR) cleared ST-NIC begins prefetch transmit data from memory (unless ST-NIC currently receiving) interframe timed ST-NIC will begin transmission CONDITIONS REQUIRED BEGIN TRANSMISSION order transmit packet following three conditions must Interframe Timer timed first Interframe least byte entered FIFO (This indicates that burst transfer been started collision been detected backoff timer expired typical systems ST-NIC prefetchs first burst bytes before timer expires time during which ST-NIC transmits preamble also used load FIFO
Note carrier sense asserted before byte been loaded into FIFO ST-NIC will become receiver
This format used with Series 32xxx 808xx processors Destination Address Destination Address Destination Address Source Address Source Address Source Address Type Length Data
Data Configuration Register
Destination Address Destination Address Destination Address Source Address Source Address Source Address Type Length Data
This format used with 680x0 type processors Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Source Address Source Address Source Address Source Address Source Address Source Address
Data Configuration Register
COLLISION RECOVERY During transmission Buffer Management logic monitors transmit circuitry determine collision occurred collision detected Buffer Management logic will reset FIFO restore Transmit pointers retransmission packet will (Number Collisions Register) will incremented retransmissions each result collision transmission will aborted will
Note reads zeroes excessive collisions encountered
This format used with general 8-bit processors
Note examples above will result transmission packet order bits within each byte will transmitted least significant first Destination Address
Remote
Remote channel used both assemble packets transmission remove received packets from Receive Buffer Ring also used general purpose slave channel moving blocks data commands between host memory local buffer memory There three modes operation Remote Write Remote Read Send Packet register pairs used control Remote Remote Start Address (RSAR0 RSAR1) register pair Remote Byte Count (RBCR0 RBCR1) register pair Start Address Register pair points beginning block moved while Byte Count Register pair used indicate number bytes transferred Full handshake logic provided move data between local buffer memory bidirectional port REMOTE WRITE Remote Write transfer used move block data from host into local buffer memory Remote will read data from port sequentially write local buffer memory beginning Remote Start Address Address will incremented Byte Counter will decremented after each transfer terminated when Remote Byte Count Register reaches zero REMOTE READ Remote Read transfer used move block data from local buffer memory host Remote will sequentially read data from local buffer memory beginning Remote Start Address write data port Address will incremented Byte Counter will decremented after each transfer terminated when Remote Byte Count Register reaches zero SEND PACKET COMMAND Remote channel automatically initialized transfer single packet from Receive Buffer Ring begins this transfer issuing ``Send Packet'' Command will initialized value Boundary Pointer Register Remote Byte Count Register pair (RBCR0 RBCR1) will initialized value Receive Byte Count fields found Buffer Header each packet After data transferred Boundary Pointer advanced allow buffers used receive packets Remote Read will terminate when Byte Count equals zero Remote then prepared read next packet from Receive Buffer Ring pointer crosses Page Stop Register reset Page Start Address This allows Remote remove packets that have wrapped around Receive Buffer Ring
Note order ST-NIC correctly execute Send Packet Command upper Remote Byte Count Register (RBCR1) must first loaded with Note Send Packet command cannot used with 680x0 type processors
Remote Autoinitialization from Buffer Ring
11157
Internal Registers
registers 8-bit wide mapped into four pages which selected Command Register (PS0 PS1) Pins used address registers within each page Page registers those registers which commonly accessed during ST-NIC operation while page registers used primarily initialization registers partitioned avoid having perform write read cycles access commonly used registers
REGISTER ADDRESS MAPPING
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REGISTER ADDRESS ASSIGNMENTS Page Address Assignments (PS1 Command (CR) Current Local Address (CLDA0) Current Local Address (CLDA1) Boundary Pointer (BNRY) Transmit Status Register (TSR) Number Collisions Register (NCR) FIFO (FIFO) Interrupt Status Register (ISR) Command (CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Boundary Pointer (BNRY) Transmit Page Start Address (TPSR) Transmit Byte Count Register (TBCR0) Transmit Byte Count Register (TBCR1) Interrupt Status Register (ISR)
Current Remote Remote Start Address Address (CRDA1) Register (RSAR1) Reserved Reserved Receive Status Register (RSR) Tally Counter (Frame Alignment Errors) (CNTR0) Tally Counter (CRC Errors) (CNTR1) Tally Counter Missed Packet Errors) (CNTR2) Remote Byte Count Register (RBCR0) Remote Byte Count Register (RBCR1) Receive Configuration Register (RCR) Transmit Configuration Register (TCR) Data Configuration Register (DCR) Interrupt Mask Register (IMR)
Current Remote Remote Start Address Address (CRDA0) Register (RSAR0)
Internal Registers (Continued)
Page Address Assignments (PS1 Command (CR) Physical Address Register (PAR0) Physical Address Register (PAR1) Physical Address Register (PAR2) Physical Address Register (PAR3) Physical Address Register (PAR4) Physical Address Register (PAR5) Current Page Register (CURR) Multicast Address Register (MAR0) Multicast Address Register (MAR1) Multicast Address Register (MAR2) Multicast Address Register (MAR3) Multicast Address Register (MAR4) Multicast Address Register (MAR5) Multicast Address Register (MAR6) Multicast Address Register (MAR7) Command (CR) Physical Address Register (PAR0) Physical Address Register (PAR1) Physical Address Register (PAR2) Physical Address Register (PAR3) Physical Address Register (PAR4) Physical Address Register (PAR5) Current Page Register (CURR) Multicast Address Register (MAR0) Multicast Address Register (MAR1) Multicast Address Register (MAR2) Multicast Address Register (MAR3) Multicast Address Register (MAR4) Multicast Address Register (MAR5) Multicast Address Register (MAR6) Multicast Address Register (MAR7) Page Address Assignments (PS1 Command (CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Remote Next Packet Pointer Transmit Page Start Address (TPSR) Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Receive Configuration Register (RCR) Transmit Configuration Register (TCR) Data Configuration Register (DCR) Interrupt Mask Register (IMR) Command (CR) Current Local Address (CLDA0) Current Local Address (CLDA1) Remote Next Packet Pointer Reserved Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved
Note Page registers should only accessed diagnostic purposes They should modified during normal operation Page should never modified
Internal Registers (Continued)
REGISTER DESCRIPTIONS COMMAND REGISTER (CR) (READ WRITE) Command Register used initiate transmissions enable disable Remote operations select register pages issue command microprocessor sets corresponding bit(s) (RD2 TXP) Further commands overlapped with following rules transmit command overlaps with remote operation bits must maintained remote command when setting Note remote command re-issued when giving transmit command will complete immediately remote byte count register been reinitialized remote operation overlaps transmission written with desired values ``0'' written Writing ``0'' this effect remote write overlap remote read operation vice versa Either these operations must either complete aborted before other operation start Bits time
Symbol
Description Stop Software reset command takes controller offline packets will received transmitted reception transmission progress will continue completion before entering reset state exit this state must reset must high perform software reset this should high software reset executed only when indicated being powers high
Note ST-NIC previously been start mode both bits will remain
Start This used activate ST-NIC after either power when ST-NIC been placed reset mode software command error powers Transmit Packet This must initiate transmission packet internally reset either after transmission completed aborted This should only after Transmit Byte Count Transmit Page Start registers have been programmed Remote Command These three encoded bits control operation Remote channel abort Remote command progress Remote Byte Count Registers should cleared when Remote been aborted Remote Start Addresses restored starting address Remote aborted Allowed Remote Read Remote Write (Note Send Packet Abort Complete Remote (Note
Note remote operation aborted remote byte count decremented zero will remain high read acknowledge (RACK) write acknowledge (WACK) will reset Note proper operation Remote Write there steps which must performed before using Remote Write steps follows Write non-zero value into RBCR0 bits III) RBCR0 RSAR0 Issue Remote Write Command (RD2
Page Select These encoded bits select which register page accessed with addresses Register Page Register Page Register Page Reserved
Internal Registers (Continued)
REGISTER DESCRIPTIONS (Continued) INTERRUPT STATUS REGISTER (ISR) (READ WRITE) This register accessed host processor determine cause interrupt interrupt masked Interrupt Mask Register (IMR) Individual interrupt bits cleared writing ``1'' into corresponding signal active long unmasked signal will until unmasked bits this register have been cleared must cleared after power writing with Symbol
Description Packet Received Indicates packet received with errors Packet Transmitted Indicates packet transmitted with errors Receive Error Indicates that packet received with more following errors Error Frame Alignment Error FIFO Overrun Missed Packet Transmit Error when packet transmitted with more following errors Excessive Collisions FIFO Underrun Overwrite Warning when receive buffer ring storage resources have been exhausted (Local reached Boundary Pointer) Counter Overflow when more Network Tally Counters been Remote Complete when Remote operation been completed Reset Status when ST-NIC enters reset state cleared when Start Command issued This also when Receive Buffer Ring overflow occurs cleared when more packets have been removed from ring Writing this effect
Note This does generate interrupt merely status indicator
Internal Registers (Continued)
REGISTER DESCRIPTIONS (Continued) INTERRUPT MASK REGISTER (IMR) (WRITE) Interrupt Mask Register used mask interrupts Each interrupt mask corresponds Interrupt Status Register (ISR) interrupt mask interrupt will issued whenever corresponding interrupt will occur when powers zeroes RXEE PTXE PRXE
RDCE CNTE OVWE TXEE Symbol PRXE Packet Received Interrupt Enable Interrupt Disabled Enables Interrupt when packet received
Description
PTXE
Packet Transmitted Interrupt Enable Interrupt Disabled Enables Interrupt when packet transmitted Receive Error Interrupt Enable Interrupt Disabled Enables Interrupt when packet received with error Transmit Error Interrupt Enable Interrupt Disabled Enables Interrupt when packet transmission results error Overwrite Warning Interrupt Enable Interrupt Disabled Enables Interrupt when Buffer Management Logic lacks sufficient buffers store incoming packet Counter Overflow Interrupt Enable Interrupt Disabled Enables Interrupt when more Network Statistics counters been Complete Interrupt Enable Interrupt Disabled Enables Interrupt when Remote transfer been completed Reserved
RXEE
TXEE
OVWE
CNTE
RDCE
Reserved
Internal Registers (Continued)
REGISTER DESCRIPTIONS (Continued) DATA CONFIGURATION REGISTER (DCR) (WRITE) This Register used program ST-NIC 16-bit memory interface select byte ordering 16-bit applications establish FIFO thresholds must initialized prior loading Remote Byte Count Registers power Symbol Word Transfer Select Selects byte-wide transfers Selects word-wide transfers establishes byte word transfers both Remote Local transfers
Note When word-wide mode selected words addressable remains
Description
Byte Order Select byte placed AD15-AD8 byte (32xxx 80x86) byte placed AD7-AD0 byte AD15 (680x0) Ignored when
Long Address Select Dual 16-bit mode Single 32-bit mode When high contents Remote registers RSAR0 issued Power high
Loopback Select Loopback mode selected Bits must also programmed Loopback operation Normal Operation Auto-Initialize Remote Send Command executed packets removed from Buffer Ring under program control Send Command executed Remote auto-initialized remove packets from Buffer Ring
Note Send Command cannot used with 680x0 byte processors
FIFO Threshold Select Encoded FIFO threshold Establishes point which requested when filling emptying FIFO During reception FIFO threshold indicates number bytes words) FIFO filled serially from network before request (BREQ) asserted
Note FIFO threshold setting determines burst length
Receive Thresholds Word Wide Byte Wide Word Bytes Words Bytes Words Bytes Words Bytes During transmission FIFO threshold indicates number bytes words) FIFO filled from Local before BREQ asserted Thus transmission threshold bytes minus received threshold
Internal Registers (Continued)
REGISTER DESCRIPTIONS (Continued) TRANSMIT CONFIGURATION REGISTER (TCR) (WRITE) transmit configuration establishes actions transmitter section ST-NIC during transmission packet network which select loopback mode power OFST Symbol
Description Inhibit appended transmitter inhibited transmitter loopback mode enabled disabled test logic Encoded Loopback Control These encoded configuration bits type loopback that performed Note that loopback mode places ENDEC Module loopback mode that must zero loopback operation Mode Normal Operation (LPBK Mode Internal Module Loopback (LPBK Mode Internal ENDEC Module Loopback (LPBK Mode External Loopback (LPBK Auto Transmit Disable This allows another station disable ST-NIC's transmitter transmission particular multicast packet transmitter re-enabled resetting this reception second particular multicast packet Reception multicast address hashing disables transmitter reception multicast address hashing enables transmitter Collision Offset Enable This modifies backoff algorithm allow prioritization nodes Backoff Logic implements normal algorithm Forces Backoff algorithm modification 2min(3 slot times first three collisions then follows standard backoff (For first three collisions station higher average backoff delay making priority mode Reserved Reserved Reserved
OFST
Reserved Reserved Reserved
Internal Registers (Continued)
REGISTER DESCRIPTIONS (Continued) TRANSMIT STATUS REGISTER (TSR) (READ) This register records events that occur media during transmission packet cleared when next transmission initiated host bits remain unless event that corresponds particular occurs during transmission Each transmission should followed read this register contents this register specified until after first transmission Symbol Reserved Description Packet Transmitted Indicates transmission without error excessive collisions FIFO underrun) (ABT ``0'' ``0'') Reserved Transmit Collided Indicates that transmission collided least once with another station network number collisions recorded Number Collisions Registers (NCR) Transmit Aborted Indicates ST-NIC aborted transmission because excessive collisions (Total number transmissions including original transmission attempt equals Carrier Sense Lost This when carrier lost during transmission packet Transmission aborted loss carrier FIFO Underrun ST-NIC cannot gain access before FIFO empties this Transmission packet will aborted Heartbeat Failure transceiver transmit collision signal after transmission packet will this Collision Detect (CD) heartbeat signal must commence during first Interframe following transmission certain collisions Heartbeat will even though transceiver performing heartbeat test Window Collision Indicates that collision occurred after slot time Transmissions rescheduled normal collisions
Internal Registers (Continued)
REGISTER DESCRIPTIONS (Continued) RECEIVE CONFIGURATION REGISTER (RCR) (WRITE) This register determines operation ST-NIC during reception packet used program what types packets accept Symbol
Description Save Errored Packets Packets with receive errors rejected Packets with receive errors accepted Receive errors Frame Alignment errors Accept Runt Packets This allows receiver accept packets that smaller than bytes packet must least bytes long accepted runt Packets with fewer than bytes rejected Packets with fewer than bytes accepted Accept Broadcast Enables receiver accept packet with destination address Packets with broadcast destination address rejected Packets with broadcast destination address accepted Accept Multicast Enables receiver accept packet with multicast address multicast addresses must pass hashing array Packets with multicast destination address checked Packets with multicast destination address checked Promiscuous Physical Enables receiver accept packets with physical address Physical address node must match station address programmed PAR0 PAR5 packets with physical addresses accepted Monitor Mode Enables receiver check addresses incoming packets without buffering memory Missed Packet Tally counter will incremented each recognized packet Packets buffered memory Packets checked address match good Frame Alignment buffered memory Reserved Reserved
Reserved Reserved
Note ``OR'd'' together ST-NIC will accept broadcast multicast addresses well physical address establish full promiscuous mode bits should addition multicast hashing array must order accept multicast addresses
Internal Registers (Continued)
REGISTER DESCRIPTIONS (Continued) RECEIVE STATUS REGISTER (RSR) (READ) This register records status received packet including information errors type address match either physical multicast contents this register written buffer memory after reception good packet packets with errors saved receive status written memory head erroneous packet erroneous packet received packets with errors rejected will written memory contents will cleared when next packet arrives errors Frame Alignment errors missed packets counted internally ST-NIC which relinguishes Host from reading real time record errors Network Management Functions contents this register specified until after first reception Symbol
Description Packet Received Intact Indicates packet received without error (Bits zero received packet Error Indicates packet received with error Increments Tally Counter (CNTR1) This will also Frame Alignment errors Frame Alignment Error Indicates that incoming packet byte boundary match last byte boundary Increments Tally Counter (CNTR0) FIFO Overrun This when FIFO serviced causing overflow during reception Reception packet will aborted Missed Packet when packet intended node cannot accepted ST-NIC because lack receive buffers controller monitor mode buffer packet memory Increments Tally Counter (CNTR2) Physical Multicast Address Indicates whether received packet physical multicast address type Physical Address Match Multicast Physical Address Match Receiver Disabled when receiver disabled entering Monitor mode Reset when receiver re-enabled when exiting Monitor mode Deferring when internal Carrier Sense Collision signals generated ENDEC module transceiver asserted line result jabber this will stay indicating jabber condition
Note Following coding applies bits
Type Error Error (Good Dribble Bits) Error Illegal Will Occur Frame Alignment Error Error
Internal Registers (Continued)
REGISTERS Registers
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Registers partitioned into groups Transmit Receive Remote Registers Transmit registers used initialize Local Channel transmission packets while Receive Registers used initialize Local Channel packet Reception Page Stop Page Start Current Boundary Registers used Buffer Management Logic supervise Receive Buffer Ring Remote Registers used initialize Remote
Note figure above registers shown bits wide Although some registers 16-bit internal registers registers accessed 8-bit registers Thus 16-bit Transmit Byte Count Register broken into 8-bit registers TBCR0 TBCR1 Also TPSR PSTART PSTOP CURR BNRY only check control upper bits address information Thus they shifted positions 15-8 diagram above
Assignment TPSR
(A7-A0 Initialized Zero)
TRANSMIT BYTE COUNT REGISTER (TBCR0 TBCR1) These registers indicate length packet transmitted bytes count must include number bytes source destination length data fields maximum number transmit bytes allowed Kbytes ST-NIC will truncate transmissions longer than 1500 bytes assignment shown below TBCR1 TBCR0
TRANSMIT REGISTERS TRANSMIT PAGE START REGISTER (TPSR) This register points assembled packet transmitted Only eight higher order addresses specified since transmit packets assembled 256-byte page boundaries assignment shown below values placed bits will used initialize higher order address -A15) Local transmission lower order bits (A7-A0) initialized zero
Internal Registers (Continued)
LOCAL RECEIVE REGISTERS PAGE START STOP REGISTERS (PSTART PSTOP) Page Start Page Stop Registers program starting stopping address Receive Buffer Ring Since ST-NIC uses fixed 256-byte buffers aligned page boundaries only upper bits start stop address specified PSTART PSTOP Assignment PSTART PSTOP REMOTE BYTE COUNT REGISTERS (RBCR0
RBCR1 BC15 BC14 BC13 BC12 BC11 BC10
RBCR0
Note RSAR0 programs start address bits A0-A7 RSAR1 programs start address bits A8-A15 Address incremented word transfers byte transfers Byte Count decremented word transfers byte transfers RBCR0 programs byte count RBCR1 programs byte count
BOUNDARY (BNRY) REGISTER This register used prevent overflow Receive Buffer Ring Buffer management compares contents this register next buffer address when linking buffers together contents this register match next buffer address Local operation aborted BNRY
CURRENT REMOTE ADDRESS (CRDA0 CRDA1) Current Remote Registers contain current address Remote assignment shown below CRDA1 CRDA0
CURRENT PAGE REGISTER (CURR) This register used internally Buffer Management Logic backup register reception CURR contains address first buffer used packet reception used restore pointers event receive errors This register initialized same value PSTART should written again unless controller Reset CURR
PHYSICAL ADDRESS REGISTERS (PAR0 PAR5) physical address registers used compare destination address incoming packets rejecting accepting packets Comparisons performed bytewide basis assignment shown below relates sequence PAR0 PAR5 sequence received packet
CURRENT LOCAL REGISTER (CLDA0 These registers accessed determine current local address CLDA1
PAR0
PAR1 DA15 DA14 DA13 DA12 DA11 DA10
PAR2 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 PAR3 DA31 DA30 DA29 DA28 DA27 DA26 DA25 DA24 PAR4 DA39 DA38 DA37 DA36 DA35 DA34 DA33 DA32
PAR5 DA47 DA46 DA45 DA44 DA43 DA42 DA41 DA40 Destination Address
Note Preamble Synch Physical Multicast
CLDA0
REMOTE REGISTERS REMOTE START ADDRESS REGISTERS (RSAR0 Remote operations programmed Remote Start Address (RSAR0 Remote Byte Count (RBCR0 registers Remote Start Address used point start block data transferred Remote Byte Count used indicate length block bytes) RSAR1
Source
DA46 DA47
MULTICAST ADDRESS REGISTERS (MAR0 MAR7) multicast address registers provide filtering multicast addresses hashed logic destination addresses through logic last destination address enters most signifi-
RSAR0
Internal Registers (Continued)
cant bits generator latched These bits then decoded decode index unique filter (FB0 multicast address registers filter selected multicast packet accepted system designer would program determine which filter bits multicast registers multicast filter bits that correspond multicast address accepted node then accept multicast packets registers ones
Note Although hashing algorithm does guarantee perfect filtering multicast address will perfectly filter multicast addresses these addresses chosen into unique locations multicast filter
NETWORK TALLY COUNTERS Three 8-bit counters provided monitoring number errors Frame Alignment Errors Missed Packets maximum count reached counter (C0H) These registers will cleared when read count recorded binary each Tally Register Frame Alignment Error Tally (CNTR0) This counter increments every time packet received with Frame Alignment Error packet must have been recognized address recognition logic counter cleared after read processor
CNTR0 Error Tally (CNTR1) This counter incremented every time packet received with error packet must first recognized address recognition logic counter cleared after read processor
CNTR1 Frames Lost Tally Register (CNTR2) This counter incremented packet cannot received lack buffer resources monitor mode this counter will count number packets that pass address recognition logic
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MAR0
MAR1 FB15 FB14 FB13 FB12 FB11 FB10
MAR2 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16 MAR3 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24 MAR4 FB39 FB38 FB37 FB36 FB35 FB34 FB33 FB32 MAR5 FB47 FB46 FB45 FB44 FB43 FB42 FB41 FB40 MAR6 FB55 FB54 FB53 FB52 FB51 FB50 FB49 FB48 MAR7 FB63 FB62 FB61 FB60 FB59 FB58 FB57 FB56 address found hash value (20H) then FB32 MAR4 should initialized ``1'' This will cause ST-NIC accept multicast packet with address
CNTR2 FIFO This 8-bit register that allows examine contents FIFO after loopback FIFO will contain last data bytes transmitted loopback packet Sequential reads from FIFO will advance pointer FIFO allow reading bytes
FIFO
Note FIFO should only read when ST-NIC been programmed loopback mode
NUMBER COLLISIONS (NCR) This register contains number collisions node experiences when attempting transmit packet collisions experienced during transmission attempt will contents will zero there excessive collisions will contents will zero cleared after
Initialization Procedures
ST-NIC must initialized prior transmission reception packets from network Power reset applied ST-NIC's reset This clears sets following bits Register Command Register (CR) Interrupt Status (ISR) Interrupt Mask (IMR) Data Control (DCR) Transmit Config (TCR) Bits Reset Bits Bits
Loopback Diagnostics
Three forms local loopback provided ST-NIC user ability loopback through deserializer controller through ENDEC module Transceiver Because half duplex architecture ST-NIC loopback testing special mode operation with following restrictions Restrictions During Loopback FIFO split into halves half used transmission other reception Only 8-bit fields fetched from memory tests required 16-bit systems verify integrity entire data path During loopback maximum latency from assertion BREQ BACK Systems that wish loopback test meet this latency limit loopback bytes without experiencing underflow Only last bytes loopback packet retained FIFO last bytes read through FIFO register which will advance through FIFO allow reading receive packet sequentially Destination Address Bytes) Station Physical Address Source Address Length Data
ST-NIC remains reset state until Start Command issued This guarantees that packets transmitted received that ST-NIC remains slave until appropriate internal registers have been programmed After initialization command register reset packets received transmitted Initialization Sequence following initialization procedure mandatory Program Command Register Page (Command Register 21H) Initialize Data Configuration Register (DCR) Clear Remote Byte Count Registers (RBCR0 RBCR1) Initialize Receive Configuration Register (RCR) Place ST-NIC LOOPBACK mode (Transmit Configuration Register 04H) Initialize Receive Buffer Ring Boundary Pointer (BNDRY) Page Start (PSTART) Page Stop (PSTOP) Clear Interrupt Status Register (ISR) writing 0FFH Initialize Interrupt Mask Register (IMR) Program Command Register page (Command Register 61H) Initialize Physical Address Registers (PAR0 PAR5) Initialize Multicast Address Registers (MAR0 MAR5) III) Initialize CURRent pointer ST-NIC START mode (Command Register 22H) Initialize Transmit Configuration Register intended value ST-NIC ready transmission reception Before receiving packets user must specify location Receive Buffer Ring This programmed Page Start Page Stop Registers addition Boundary Current Page Register must initialized value Page Start Register These registers will modified during reception packets
Bytes
1500 Bytes
Appended ST-NIC ``0''
When word-wide mode with Byte Order Select loopback packet must assembled even byte location shown below (Loopback only operates with byte wide transfers
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When word-wide mode with Byte Order Select following format must used loopback packet
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Note When using loopback word mode bytes must programmed TBCR0 Where actual number bytes assembled even location
Loopback Diagnostics (Continued)
initiate loopback user first assembles loopback packet then selects type loopback using Transmit Configuration register bits transmit configuration register must also enable disable generation during transmission user then issues normal transmit command send packet During loopback receiver checks address match receiver will also check last bytes loopback packet buffered read FIFO using FIFO read port Loopback Modes MODE Loopback through Module (LB1 this loopback used Modules's serializer connected deserializer MODE Loopback through ENDEC Module (LB1 loopback performed through ST-NIC provides control (LPBK) that forces ENDEC module loopback signals MODE Loopback cable (LB1 Packets transmitted cable loopback mode check transmit receive paths cable itself
Note Collision Carrier Sense generated ENDEC module masked module possible directly between loopback modes necessary return normal operation (00H) when changing modes
alignment 64-byte packet shown below FIFO Location FIFO Contents Lower Byte Count Upper Byte Count Upper Byte Count Last Byte CRC1 CRC2 CRC3 CRC4 First Byte Read Second Byte Read
Last Byte Read
following alignment FIFO packet length should Bytes Note that will appended transmitter appended transmitter four bytes bytes correspond FIFO Location FIFO Contents Byte Byte (CRC1) Byte (CRC2) Byte (CRC3) Byte (CRC4) Lower Byte Count Upper Byte Count Upper Byte Count First Byte Read Second Byte Read
Reading Loopback Packet last bytes received packet examined consecutive reads FIFO register FIFO pointer incremented after rising edge CPU's read strobe internally synchronizing advancing pointer This take four clock cycles pointer been incremented time reads FIFO register again ST-NIC will insert wait states
Note FIFO only read during Loopback Reading FIFO other time will cause ST-NIC malfunction
Last Byte Read
Alignment Received Packet FIFO Reception packet FIFO begins location zero after FIFO pointer reaches last location FIFO pointer wraps FIFO overwriting previously received data This process continued until last byte received ST-NIC then appends received byte count next locations FIFO contents Upper Byte Count also copied next FIFO location number bytes used loopback packet determines alignment packet FIFO
LOOPBACK TESTS Loopback capabilities provided allow certain tests performed validate operation DP83902A STNIC prior transmitting receiving packets live network Typically these tests performed during power node diagnostic provides support verify following Verify integrity data path Received data checked against transmitted data Verify logic's capability generate good transmit verify receive (good CRC)
Loopback Diagnostics (Continued)
Verify that Address Recognition Logic Recognize address match packets Reject packets that fail match address LOOPBACK OPERATION ST-NIC Loopback modified form transmission using only half FIFO This places certain restrictions loopback testing When loopback mode selected FIFO split packet should assembled memory with programming TPSR TBCR0 TBCR1 registers When transmit command issued following operations occur Transmitter Actions Data transferred from memory until FIFO filled each transfer TBCR0 TBCR1 decremented (Subsequent burst transfers initiated when number bytes FIFO drops below programmed threshold ST-NIC generates bits preamble followed 8-bit synch pattern Data transferred from FIFO serializer calculated ST-NIC last byte transmitted last byte from FIFO (Allows software appended) ST-NIC calculates appends four bytes Transmission Receiver Actions Wait synch preamble stripped Store packet FIFO increment receive byte count each incoming byte receiver checks incoming packet errors receiver does check errors error always (for address matching packets) receive receive byte count written into FIFO receive status register updated typically even address does match errors forced packet must match address filters order error EXAMPLES following examples show what results expected from properly operating ST-NIC during loopback restrictions results each type loopback listed reference loopback tests divided into sets tests verify data path generation byte count through three paths second tests uses internal loopback verify receiver's checking address recognition tests programmed Path ST-NIC Internal Path ST-NIC Internal (Note
Note since generated external encoder decoder
Path ST-NIC External
(Note
(Note
Note should however could also contain variety other values depending whether collisions were encountered packet deferred Note will contain packet transmittable Note During external loopback ST-NIC exposed network traffic therefore possible contents both Receive portion FIFO corrupted other packet network Thus live network contents FIFO should depended ST-NIC will still abide standard CSMA protocol external loopback mode network will disturbed loopback packet Note values
ADDRESS RECOGNITION next three tests exercise address recognition logic These tests should performed using internal loopback only that ST-NIC isolated from interference from network These tests also require capability generate software address recognition logic cannot directly tested bits only address packet matches address filters errors expected they packet been rejected basis address mismatch following sequence packets will test address recognition logic should should with software generated Packet Contents Test Test Test Test Address Matching Matching Non-Matching Good Results (Note (Note
Note Status will read multicast address used Note Status will read multicast address used Note test test address found match since flagged Test proves that address recognition logic distinguish address does notify receiving proven work test test Note values
(Note (Note (Note
Note Since carrier sense collision detect generated ENDEC module they blocked during loopback Carrier heartbeat seen bits Note errors always indicated receiver appended transmitter Note Only only status written memory loopback this action does occur remains loopback modes Note values
NETWORK MANAGEMENT FUNCTIONS Network management capabilities required maintenance planning local area network ST-NIC supports minimum requirement network management hardware remaining requirements with software counts There three events that software alone track during reception packets errors Frame Alignment errors missed packets
Loopback Diagnostics (Continued)
Since errored packets rejected status associated with these packets lost unless access Receive Status Register before next packer arrives situations where another packet arrives very quickly have opportunity this ST-NIC counts number packets with errors Frame Alignment errors 8-Bit counters have been selected reduce overhead counters will generate interrupts whenever their MSBs that software routine accumulate network statistics reset counter before overflow occurs counters sticky that when they reach count (C0H) counting halted additional counter provided count number packets STNIC misses buffer overflow being offline structure counters shown below Additional information required network management available Receive Transmit Status Registers Transmit status available after each transmission information regarding events during transmission Typically following statistics might gathered software Traffic Frames Sent Frames Received Multicast Frames Received Packets Lost Lack Resources Retries Packet Errors Errors Alignment Errors Excessive Collisions Packet with Length Errors Heartbeat Failure
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Arbitration Timing
ST-NIC operates three possible modes
MASTER (WHILE PERFORMING DMA) SLAVE (WHILE BEING ACCESSED CPU) IDLE
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Upon power-up ST-NIC indeterminate state After receiving hardware reset ST-NIC slave Reset State receiver transmitter both disabled this state reset state re-entered under three conditions soft reset (Stop Command) hard reset (RESET input) error that shuts down receiver transmitter (FIFO underflow overflow) After initialization registers ST-NIC issued Start command ST-NIC enters Idle state Until required ST-NIC remains idle state idle state exited request from FIFO case receiver transmit from Remote case Remote
operation After acquiring BREQ BACK handshake Remote Local transfer completed ST-NIC re-enters idle state TRANSFERS TIMING programmed following types transfers 16-Bit Address 8-bit Data Transfer 16-Bit Address 16-bit Data Transfer 32-Bit Address 8-bit Data Transfer 32-Bit Address 16-bit Data Transfer transfers BSCK timing 16-Bit Address modes require BSCK cycles shown below
16-Bit Address 8-Bit Data
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Arbitration Timing (Continued)
16-Bit Address 16-Bit Data
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32-Bit Address 8-Bit Data
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32-Bit Address 16-Bit Data
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Note 32-bit address mode ADS1 TRI-STATE after first T1-T4 states thus pull-down resistor required 32-bit address
Arbitration Timing (Continued)
When 32-bit mode four additional BSCK cycles required burst first cycle each burst used output upper 16-bit addresses This 16-bit address programmed RSAR0 RSAR1 points page system memory transmitted received packets constrained reside within this page FIFO BURST CONTROL Local transfers burst transfers once requests acknowledged will transfer exact burst bytes programmed Data Configuration Register (DCR) then relinquish there remaining bytes FIFO next burst will initiated until FIFO threshold exceeded BACK removed during transfer burst transfer will aborted (DROPPING BACK DURING CYCLE RECOMMENDED
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where Words Bytes when byte mode
INTERLEAVED LOCAL OPERATION remote transfer initiated progress when packet being received transmitted Remote transfer will interrupted higher priority Local
transfers When Local transfer completed Remote will rearbitrate continue transfers This illustrated below
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Note that FIFO requires service while remote progress BREQ dropped Local burst appended Remote Transfer When switching from local transfer remote transfer however BREQ dropped raised again This allows other devices fairly contend FIFO OPERATIONS Overview accommodate different rates which data comes from goes network goes comes from) system memory ST-NIC contains 16-byte FIFO buffering data between media FIFO threshold programmable allowing filling emptying) FIFO different rates When FIFO filled programmed threshold local channel transfers these bytes words) into local memory crucial that local given access within minimum latency time otherwise FIFO underrun overrun) occurs understand FIFO underruns overruns there causes which produce this condition
latency long that FIFO filled emptied) from network before local serviced FIFO latency data rate slowed throughput local point where slower than network data rate This second condition also dependent upon clock word width (byte wide word wide) worst case condition ultimately limits overall latency which ST-NIC tolerate FIFO Underrun Transmit Enable During transmission FIFO underrun occurs Transmit enable (TXE) output remain high (active) Generally this will cause very large packet transmitted onto network jabber feature transceiver will terminate transmission reset prevent this problem properly designed system will allow FIFO underruns giving ST-NIC acknowledge within time shown maximum latency curves shown described later FIFO Beginning Receive beginning reception ST-NIC stores entire Address field each incoming packet FIFO deter-
Arbitration Timing (Continued)
mine whether packet matches Physical Address Registers maps Multicast Registers This causes FIFO accumulate bytes Furthermore there some synchronization delays Thus actual time that BREQ asserted from time Start Frame Delimiter (SFD) detected This operation affects latencies 4-byte thresholds during first receive BREQ since FIFO must filled bytes words) before issuing BREQ FIFO Operation Receive When Carrier Sense goes ST-NIC enters packet processing sequence emptying FIFO writing status information beginning packet Figure ST-NIC holds onto entire sequence longest time BREQ extended occurs when packet ends just ST-NIC performs last FIFO burst ST-NIC this case performs programmed burst transfer followed flushing remaining bytes FIFO completes writing header information memory following steps occur during this sequence ST-NIC issues BREQ because FIFO threshold been reached During burst packet ends resulting BREQ extended ST-NIC flushes remaining bytes from FIFO ST-NIC performs internal processing prepare writing header ST-NIC writes 4-byte (2-word) header ST-NIC deasserts BREQ Packet Processing (EOPP) times have been tabulated table below Mode Byte Threshold Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Clock EOPP
Byte
Word
Word
Packet Processing Times Various FIFO Thresholds Clocks Transfer Modes Threshold Detection (Bus Latency) assure that overwriting data FIFO occurs FIFO logic flags FIFO overrun 13th byte written into FIFO effectively shortening FIFO bytes FIFO logic also operates differently Byte Mode Word Mode Byte Mode threshold indicated when byte entered FIFO thus with 8-byte threshold ST-NIC issues Request (BREQ) when byte entered FIFO Word Mode BREQ generated until bytes have entered FIFO Thus with 4-word threshold (equivalent 8-byte threshold) BREQ issued when 10th byte entered FIFO graphs following indicate maximum allowable latency Word Byte transfer modes
Packet Processing
11157
Arbitration Timing (Continued)
FIFO Beginning Transmit Before transmitting ST-NIC performs prefetch from memory load FIFO number bytes prefetched programmed FIFO threshold next BREQ issued until after ST-NIC actually begins transmitting data after Transmit Prefetch diagram illustrates this process
Transmit Prefetch Timing
11157
Maximum Latency Byte Mode
Maximum Latency Word Mode
11157
11157
Arbitration Timing (Continued)
REMOTE DMA-BIDIRECTIONAL PORT CONTROL Remote transfers data between local buffer memory bidirectional port (memory transfer) This transfer arbited byte byte basis versus burst transfer used Local transfers This bidirectional port also read written host transfers through this port asynchronous time transfers limited direction either from port local buffer memory (Remote Write) from local buffer memory port (Remote Read) Handshake Signals Remote Transfers REMOTE READ TIMING reads byte word from local buffer memory writes byte word into latch increments address decrements byte count (RBCR0 Request Line (PRQ) asserted inform system that byte available system reads port read strobe (RACK) used acknowledge Remote goes back step Steps repeated until remote complete Note that order Remote transfer byte from memory latch must arbitrate access local BREQ BACK handshake After each byte word transferred latch BREQ dropped Local progress Remote held until local complete
11157-28
11157
Arbitration Timing (Continued)
REMOTE WRITE TIMING Remote Write operation transfers data from port local buffer ST-NIC initiates transfer requesting byte word system transfers byte-word latch This write strobe detected ST-NIC removed removing Remote holds further transfers into latch until current byte word been transferred from latch reasserted next transfer begin ST-NIC asserts System writes byte word into latch ST-NIC removes Remote reads contents port writes byte word local buffer memory increments address decrements byte count (RBCR0 back step Steps repeated until remote complete
11157
REMOTE WRITE SPECIAL CONSIDERATIONS Setting Using Remote Read Under certain conditions ST-NIC state machine issue before first transfer Remote Write Command this occurs this could cause data corruption cause remote count different from main count causing system ``lock up'' prevent this condition when implementing Remote Write Remote Write command should first preceded Remote Read command insure that signal asserted before ST-NIC starts port read cycle reason this that state machine that asserts runs independently state machine that controls signals machine assumes that asserted actually remedy this situation single Remote Read cycle should inserted before actual Write Command given This will ensure that asserted when Remote Write subsequently executed This single Remote Read cycle called ``dummy Remote Read'' order dummy Remote Read cycle operate correctly Start Address should programmed known safe location buffer memory space Remote Byte count should programmed value greater than This will ensure that
master read cycle performed safely eliminating possibility data corruption Remote Write with High Speed Buses When implementing Remote Write solution with high speed buses CPU's timing cause system hang Therefore additional considerations required problem occurs when system execute dummy Remote Read then start Remote Write before ST-NIC chance execute Remote Read this happens signal will Remote Byte Count Remote Start Address Remote Write operation could corrupted This shown hatched waveforms following timing diagram execution Remote Read delayed local operations (particularly during end-of-packet processing) ensure dummy Remote Read does execute delay must inserted between writing Remote Read Command starting write Remote Write Start Address (This time designated next figure delay arrows recommended method avoid this problem after Remote Read command given poll both bytes Current Remote Address Registers When address incremented been Software should recognize this then start Remote Write
Arbitration Timing (Continued)
additional caution high speed systems that polling must follow guidelines specified Time Between Chip Selects section That there must least clocks between chip selects (For example when BSCK then this time should general flow executing Remote Write Remote Byte Count value Remote Start Address unused (one location before transmit start address usually safe location) Issue ``dummy'' Remote Read command Read Current Remote Address (CRDA) (both bytes) Compare previous CRDA value different Delay jump Remote Write command setting Remote Byte Count Remote Start Address (note that Remote Byte count step transmit byte count plus Remote Start Address less these will incremented correct values Issue Remote Write command
11157
Note dashed lines indicate incorrect timing described text
Timing Diagram Dummy Remote Read
Arbitration Timing (Continued)
SLAVE MODE TIMING When ST-NIC becomes slave then read write internal registers register accesses byte wide timing register access shown below host accesses internal registers with four address lines RA0-RA3 strobes ADS0 used latch address when interfacing multiplexed address data Since ST-NIC local master when host attempts read write controller line used hold until ST-NIC leaves master mode Some number BSCK cycles also required allow ST-NIC synchronize read write cycles
Write Register
11157
Read from Register
11157
TIME BETWEEN CHIP SELECTS ST-NIC requires that successive chip selects closer than clocks (BSCK) together condition violated ST-NIC glitch CPUs that operate from pipelined instructions 386) have cache
486) execute consecutive cycles very quickly solution delay execution consecutive cycles either breaking pipeline forcing access outside cache
Time between Chip Selects
11157
Preliminary Electrical Characteristics Absolute Maximum Ratings
Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Supply Voltage (VCC)
Input Voltage (VIN) Output Voltage (VOUT) Storage Temperature Range (TSTG) Power Dissipation (PD) Lead Temp (TL) (Soldering Rating (RZAP CZAP ZAP) Clamp Diode Current
Note Absolute Maximum ratings those values beyond which safety device cannot guaranteed They meant imply that device should operated these limits Note specifications this datasheet valid only mandatory isolation employed differential signals taken exist side isolation
Preliminary Specifications
Symbol VIH2 VIL2 VLOL IINSEL Parameter Minimum High Level Output Voltage (Notes Minimum Level Output Voltage (Notes Minimum High Level Input Voltage (Note Minimum High Level Input Voltage RACK WACK (Note Maximum Level Input Voltage (Note Maximum Level Input Voltage RACK WACK (Note Good Link Output Voltage Input Current Input Current Minimum TRI-STATE Output Leakage Current (Note Average Supply Current (Note
unless otherwise specified Conditions Units
VOUT Clock IOUT
2000
Note These levels tested dynamically using limited amount functional test patterns please refer test load Note Limited functional test patterns performed these input levels majority functional tests performed levels Note This measured with bypass capacitor between Note drive CMOS compatible limits tested directly Detailed device characterization validates that this specification guaranteed testing high drive compatible specification Note RA0-RA3 WACK BREQ pins used outputs test mode result tested they TRI-STATE input outputs these pins input leakage specification
Preliminary Electrical Characteristics (Continued) Preliminary Specifications
Symbol Parameter INTERFACE PINS Diff Output Voltage Diff Output Voltage Imbalance (Note Undershoot Voltage (Note Diff Squelch Threshold (Note Diff Input Common Mode Voltage (Note Termination 270X from Each Termination 270X from Each Termination 270X from Each
1200
unless otherwise specified (Continued) Units
Conditions
Typical Typical
OSCILLATOR PINS IOSC Input High Voltage Input Voltage Input Current Input Current Connected Oscillator Grounded Connected Oscillator Grounded Grounded Grounded (Driven Mode)
TWISTED PAIR INTERFACE PINS (TXO TXOd RTOL RTOH VSRON1 VSRON2 VSROFF VDIFF TXOd Level Output Resistance TXOd High Level Output Resistance Receive Threshold Turn-On Voltage (10BASE-T) Receive Threshold Turn-On Voltage (Reduced Level) Receive Threshold Turn-Off Voltage (Note Differential Mode Input Voltage Range (Note
VSRON
Note This parameter guaranteed design tested
Switching Characteristics Specs DP83902A Note
Timing Preliminary
Register Read (Latched Using ADS0)
11157
Symbol aswi ackdv rackl rackh rsrsl
Parameter Register Select Setup ADS0 Register Select Hold from ADS0 Address Strobe Width Acknowledge Data Valid Read Strobe Data TRI-STATE (Note Read Strobe (Notes Read Strobe High Register Select Slave Read Latched RS0-3
Units
bcyc
Note generated until ST-NIC synchronized register access ST-NIC will insert integral number Clock cycles until synchronized Dual systems additional cycles will used local remote complete Wait states must issued until asserted Note asserted before after asserted after rackl referenced from falling edge de-asserted concurrently with after de-asserted Note These limits include delay inherent test method These signals typically turn within enabling other devices drive these lines with contention
Switching Characteristics Specs DP83902A Note
Timing Preliminary (Continued)
Register Read (Non-Latched ADS0
11157
Symbol rsrs rsrh ackdv rackl rackh
Parameter Register Select Read Setup (Notes Register Select Hold from Read Valid Data Read Strobe Data TRI-STATE (Note Read Strobe (Note Read Strobe High
Units
bcyc
Note rsrs includes flow-through time latch Note These limits include delay inherent test method These signals typically turn within enabling other devices drive these lines with contention Note asserted before after RA0-3 since address decode begins when asserted asserted after RA0-3 rackl referenced from falling edge
Switching Characteristics Specs DP83902A Note
Timing Preliminary (Continued)
Register Write (Latched Using ADS0)
11157
Symbol aswi rwds rwdh wackh wackl rswsl
Parameter Register Select Setup ADS0 Register Select Hold from ADS0 Address Strobe Width Register Write Data Setup Register Write Data Hold Write Strobe Width from Write Strobe High High Write (Notes Register Select Write Strobe
Units
bcyc
Note generated until ST-NIC synchronized register access Dual Systems additional cycles will used local Remote complete Note asserted before after asserted after wackl referenced from falling edge
Switching Characteristics Specs DP83902A Note
Timing Preliminary (Continued)
Register Write (Non-Latched ADS0
11157
Symbol rsws rswh rwds rwdh wackl wackh
Parameter Register Select Write Setup (Note Register Select Hold from Write Register Write Data Setup Register Write Data Hold Write (Note Write High High Write Width from
Units
bcyc
Note Assumes ADS0 high when RA0-3 changing Note generated until ST-NIC synchronized register access Dual systems additional cycles will used local remote complete
Switching Characteristics Specs DP83902A Note
Control Arbitration
Timing Preliminary (Continued)
11157
Symbol brqhl brqhr brql backs bccte bcctr
Parameter Clock Request High Local Clock Request High Remote Request from Clock Acknowledge Setup Clock (Note Clock Control Enable Clock Control Release (Notes
Units
Note BACK must setup before after BREQ asserted Missed setup will slip beginning four clocks Latency will influence allowable FIFO threshold Note During remote transfers only single transfer performed During local operations burst mode transfers performed Note These limits include delay inherent test method These signals typically turn within enabling other devices drive these lines with contention
Switching Characteristics Specs DP83902A Note
Address Generation
Timing Preliminary (Continued)
11157
Symbol bcyc bcash bcasl aswo bcadv bcadz
Parameter Clock Cycle Time (Note Clock High Time Clock Time Clock Address Strobe High Clock Address Strobe Address Strobe Width Clock Address Valid Clock Address TRI-STATE (Note Address Setup ADS0 Address Hold from ADS0
Units
Note Cycles only issued first transfer burst when 32-bit mode been selected Note rate clock must high enough support transfers from FIFO rate greater than serial network transfers from FIFO Note These limits include delay inherent test method These signals typically turn within enabling other devices drive these lines with contention
Switching Characteristics Specs DP83902A Note
Memory Read
Timing Preliminary (Continued)
11157
Symbol bcrl bcrh asds dsada avrh
Parameter Clock Read Strobe Clock Read Strobe High Data Setup Read Strobe High Data Hold from Read Strobe High Read Strobe Width Memory Read High Address TRI-STATE (Notes Address Strobe Data Strobe Data Strobe Address Active Address Valid Read Strobe High
Units
bcyc bcyc bcyc
Note During burst A8-A15 TRI-STATE byte wide transfers selected last transfer A8-A15 TRI-STATE shown above Note These limits include delay inherent test method These signals typically turn within enabling other devices drive these lines with contention
Switching Characteristics Specs DP83902A Note
Memory Write
Timing Preliminary (Continued)
11157
Symbol bcwl bcwh asds aswd
Parameter Clock Write Strobe Clock Write Strobe High Data Setup High Data Hold from Write Strobe Address TRI-STATE (Notes Address Strobe Data Strobe Address Strobe Write Data Valid
Units
bcyc
Note When using byte mode transfers A8-A15 only TRI-STATE last transfer timing only valid last transfer burst Note These limits include delay inherent test method These signals typically turn within enabling other devices drive these lines with contention
Switching Characteristics Specs DP83902A Note
Wait State Insertion
Timing Preliminary (Continued)
11157
Symbol
Parameter External Wait Setup 0Clock (Note External Wait Release Time (Note
Units
Note addition wait states affects count deserialized bytes limited number clock cycles depending clock network rates allowable wait states found table below (Assumes Mbit data rate
BSCK (MHz)
Wait States Word Transfer
number allowable wait states byte mode calculated using W(byte mode)
Byte Transfer
tbsck
Number Wait States Network Clock Period BSCK Period tbsck number allowable wait states word mode calculated using
W(word mode)
tbsck
Table assumes network clock
Switching Characteristics Specs DP83902A Note
Timing Preliminary (Continued)
Remote (Read Send Command)
11157
Symbol bpwrl bpwrh prqh prql rakw
Parameter Clock Port Write Clock Port Write High Port Write High Port Request High (Note Port Request from Read Acknowledge High Remote Acknowledge Read Strobe Pulse Width
Units
Note Start next transfer dependent where RACK generated relative BSCK whether local pending
Switching Characteristics Specs DP83902A Note
Timing Preliminary (Continued)
Remote (Read Send Command) Recovery Time
11157
Symbol bpwrl bpwrh prqh prql rakw rhpwh
Parameter Clock Port Write Clock Port Write High Port Write High Port Request High (Note Port Request from Read Acknowledge High Remote Acknowledge Read Strobe Pulse Width Read Acknowledge High Next Port Write Cycle (Notes
Units BSCK
Note Start next transfer dependent where RACK generated relative BSCK whether local pending Note This measured value guaranteed design Note RACK must high minimum BSCK Note Assumes local interleave immediate BACK
Switching Characteristics Specs DP83902A Note
Remote (Write Cycle)
Timing Preliminary (Continued)
11157
Symbol bprqh wprql wackw bprdl bprdh
Parameter Clock Port Request High (Note WACK Port Request WACK Pulse Width Clock Port Read (Note Clock Port Read High
Units
Note first port request issued response remote write command subsequently issued clock cycles following completion remote cycles Note start remote write following WACK dependent where WACK issued relative BSCK whether local pending
Switching Characteristics Specs DP83902A Note
Timing Preliminary (Continued)
Remote (Write Cycle) Recovery Time
11157
Symbol bprqh wprql wackw bprdl bprdh wprq
Parameter Clock Port Request High (Note WACK Port Request WACK Pulse Width Clock Port Read (Note Clock Port Read High Remote Write Port Request Port Request Time (Notes
Units
BSCK
Note first port request issued response remote write command subsequently issued clock cycles following completion remote cycles Note start remote write following WACK dependent where WACK issued relative BSCK whether local pending Note Assuming wackw BSCK local interleave immediate BACK WACK goes high before Note WACK must high minimum BSCK Note This measured value guaranteed design
Reset Timing
11157
Symbol rstw
Parameter Reset Pulse Width (Note
Units BSCK Cycles Cycles (Note
Note RESET pulse requires that BSCK stable power RESET should raised until BSCK have become stable Several registers affected RESET Consult register descriptions details Note slower BSCK clocks will determine minimum time RESET signal BSCK then RESET BSCK BSCK then RESET
Switching Characteristics Specs DP83902A Note
Timing Preliminary (Continued)
Transmit Timing (End Packet)
11157
Symbol tTOh tTOl
Parameter Transmit Output High before Idle (Half Step) Transmit Output Idle Time (Half Step)
Units
8000
Receive Packet Timing
11157
Symbol teop1 teop0
Parameter Receive Packet Hold Time after Logic ``1'' (Note Receive Packet Hold Time after Logic ``0'' (Note
Units
Note This parameter guaranteed design tested
Switching Characteristics Specs DP83902A Note
Link Pulse Timing
Timing Preliminary (Continued)
11157
Symbol tipw
Parameter Time between Link Output Pulses Link Integrity Output Pulse Width
Units
Transmit Packet Timing
11157
Symbol tdel toff toffd
Parameter Pre-Emphasis Output Delay (TXO TXOd (Note Transmit Hold Time Packet (TXO (Note Transmit Hold Time Packet (TXOd (Note
Units
Note This parameter guaranteed design tested
Timing Test Conditions
specifications valid only mandatory isolation employed differential signals taken side pulse transformer Input Pulse Levels (TTL CMOS) Input Rise Fall Times (TTL CMOS) Input Output Reference Levels (TTL CMOS) 1315 Input Pulse Levels (Diff Input Output Reference Levels (Diff TRI-STATE Reference Levels Output Load (See Figure Below) Point Differential Float (DV)
Capacitance
Symbol COUT Parameter Input Capacitance Output Capacitance
Units
DERATING FACTOR Output timing measured with purely capacitive load following correction factor used other loads Transmit Test Load
11157
Note above diagram signals taken from side isolation (pulse transformer) pulse transformer used testing Pulse Engineering PE64103
11157
Note includes scope capacitance Note Open timing tests push pull outputs test test High Impedance active active High Impedance measurements High Impedance active high active high High Impedance measurements
Physical Dimensions inches (millimeters)
Plastic Chip Carrier Order Number DP83902AV Package Number V84A
Quad Flat Pack Order Number DP83902AVF Package Number VF100B
Physical Dimensions inches (millimeters) (Continued)
Plastic Quad Flatpack (VJG) Order Number DP83902AVJG Package Number VJG100A
DP83902A ST-NIC Serial Network Interface Controller Twisted Pair
Physical Dimensions inches (millimeters) (Continued)
Order Number DP83902AVLC Package Number VLC100B
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