ZBT® SRAM High frequency percent utilization Fast cycle times: 6n

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ZBT® SRAM High frequency percent utilization Fast cycle times: 6n

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4Mb: 256K 128K 32/36 PIPELINED SRAM
ZBT® SRAM
High frequency percent utilization Fast cycle times: 6ns, 7.5ns 10ns Single +3.3V power supply (VDD) Separate +3.3V +2.5V isolated output buffer supply (VDDQ) Advanced control logic minimum control signal interface Individual BYTE WRITE controls tied Single R/W# (read/write) control CKE# enable clock suspend operations Three chip enables simple depth expansion Clock-controlled registered addresses, data I/Os control signals Internally self-timed, fully coherent WRITE Internally self-timed, registered outputs eliminate need control SNOOZE MODE reduced-power standby Common data inputs data outputs Linear interleaved burst modes Burst feature (optional) Pin/function compatibility with 2Mb, 8Mb, 16Mb SRAM family Automatic power-down 165-pin FBGA package 100-pin TQFP package 119-pin package
MT55L256L18P1, MT55L256V18P1, MT55L128L32P1, MT55L128V32P1, MT55L128L36P1, MT55L128V36P1
3.3V VDD, 3.3V 2.5V
100-Pin TQFP1
165-Pin FBGA
(Preliminary Package Data)
OPTIONS
Timing (Access/Cycle/MHz) 3.5ns/6ns/166 4.2ns/7.5ns/133 5ns/10ns/100 Configurations 3.3V 256K 128K 128K 2.5V 256K 128K 128K Package 100-pin TQFP 165-pin FBGA 119-pin, 14mm 22mm Operating Temperature Range Commercial (0°C +70°C) Industrial (-40°C +85°C)**
Part Number Example:
MARKING
-7.5 MT55L256L18P1 MT55L128L32P1 MT55L128L36P1 MT55L256V18P1 MT55L128V32P1 MT55L128V36P1 None
NOTE: JEDEC-standard MS-026 (LQFP). JEDEC-standard MS-028 (PBGA).
119-Pin BGA2
MT55L256L18P1T-10
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Part Marking Guide FBGA devices found Micron's Industrial temperature range offered specific speed grades configurations. Contact factory more information.
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
FUNCTIONAL BLOCK DIAGRAM 256K
SA0, SA1, MODE CKE#
ADDRESS REGISTER
SA1' SA0' BURST LOGIC
ADV/LD#
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
ADV/LD# BWa# BWb# R/W#
WRITE REGISTRY DATA COHERENCY CONTROL LOGIC
256K
WRITE DRIVERS
MEMORY ARRAY
DQPa DQPb
INPUT REGISTER
INPUT REGISTER
CE2#
READ LOGIC
FUNCTIONAL BLOCK DIAGRAM 128K 32/36
SA0, SA1,
MODE CKE#
ADDRESS REGISTER
SA1' SA0' BURST LOGIC
ADV/LD# WRITE ADDRESS REGISTER WRITE ADDRESS REGISTER
ADV/LD# BWa# BWb# BWc# BWd# R/W#
WRITE REGISTRY DATA COHERENCY CONTROL LOGIC WRITE DRIVERS
128K (x32) 128K (x36) MEMORY ARRAY
DQPa DQPb DQPc DQPd
INPUT REGISTER
INPUT REGISTER
CE2#
READ LOGIC
NOTE: Functional block diagrams illustrate simplified device operation. truth tables, descriptions, timing diagrams detailed information.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
GENERAL DESCRIPTION
Micron® Zero Turnaround(ZBT®) SRAM family employs high-speed, low-power CMOS designs using advanced CMOS process. Micron's SRAMs integrate 256K 128K 128K SRAM core with advanced synchronous peripheral circuitry 2-bit burst counter. These SRAMs optimized percent utilization, eliminating turnaround cycles when transitioning from READ WRITE, vice versa. synchronous inputs pass through registers controlled positive-edge-triggered single clock input (CLK). synchronous inputs include addresses, data inputs, chip enable (CE#), additional chip enables easy depth expansion (CE2, CE2#), cycle start input (ADV/LD#), synchronous clock enable (CKE#), byte write enables (BWa#, BWb#, BWc#, BWd#) read/write (R/W#). Asynchronous inputs include output enable (OE#, which tied control signal minimization), clock (CLK) snooze enable (ZZ, which tied unused). There also burst mode (MODE) that selects between interleaved linear burst modes. MODE tied HIGH, left unconnected burst unused. data-out (Q), enabled OE#, registered rising edge CLK. WRITE cycles from four bytes wide controlled write control inputs. READ, WRITE DESELECT cycles initiated ADV/LD# input. Subsequent burst addresses internally generated controlled burst advance (ADV/LD#). burst mode optional. allowable give address each individual READ WRITE cycle. BURST cycles wrap around after fourth access from base address. allow continuous, percent data bus, pipelined SRAM uses LATE LATE WRITE cycle. example, WRITE cycle begins clock cycle one, address present rising edge one. BYTE WRITEs need asserted same cycle address. data associated with address required cycles later, rising edge clock cycle three. Address write control registered on-chip simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes written. During BYTE WRITE cycle, BWa# controls pins; BWb# controls pins; BWc# controls pins; BWd# controls pins. Cycle types only defined when address loaded, i.e., when ADV/LD# LOW. Parity/ECC bits only available versions. Micron's SRAMs operate from +3.3V power supply, inputs outputs LVTTLcompatible. Users choose either 2.5V 3.3V version. device ideally suited systems requiring high bandwidth zero turnaround delays. Please refer Micron's site (www.micron.com/ products/datasheets/zbtds.html) latest data sheet.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
TQFP ASSIGNMENT TABLE
VDDQ VDDQ VDDQ VDDQ MODE (LBO#) VDDQ VDDQ VDDQ VDDQ ADV/LD# (G#) CKE# R/W# CE2# BWa# BWb# BWc# BWc# BWd# BWd#
Pins reserved address expansion, 16Mb respectively.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
ASSIGNMENT (TOP VIEW) 100-PIN TQFP
VDDQ VDDQ VDDQ VDDQ
NF** NF** ADV/LD# (G#) CKE# R/W# CE2# BWa# BWb#
MODE (LBO#)
NF** NF** ADV/LD# (G#) CKE# R/W# CE2# BWa# BWb# BWc# BWd#
NC/DQb* VDDQ VDDQ VDDQ VDDQ NC/DQa*
VDDQ VDDQ VDDQ VDDQ
x32/x36
MODE (LBO#)
Connect (NC) used version. Parity (DQPx) used version. **Pins reserved address expansion, 16Mb respectively.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
NC/DQc* VDDQ VDDQ VDDQ VDDQ NC/DQd*
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
TQFP DESCRIPTIONS
32-35, 44-50, 80-82, x32/x36 32-35, 44-50, SYMBOL TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs registered must meet setup hold times around rising edge CLK. Pins reserved address bits higher-density 16Mb SRAMs, respectively. least significant bits (LSB) address field internal burst counter burst desired. Synchronous Byte Write Enables: These active inputs allow individual bytes written when WRITE cycle active must meet setup hold times around rising edge CLK. BYTE WRITEs need asserted same cycle address. associated with addresses apply subsequent data. BWa# controls pins; BWb# controls pins; BWc# controls pins; BWd# controls pins. Clock: This signal registers address, data, chip enables, byte write enables burst control inputs rising edge. synchronous inputs must meet setup hold times around clock's rising edge. Synchronous Chip Enable: This active input used enable device sampled only when external address loaded (ADV/LD# LOW). Synchronous Chip Enable: This active input used enable device sampled only when external address loaded (ADV/LD# LOW). This input used memory depth expansion. Synchronous Chip Enable: This active HIGH input used enable device sampled only when external address loaded (ADV/LD# LOW). This input used memory depth expansion. Output Enable: This active LOW, asynchronous input enables data output drivers. JEDECstandard term OE#. Synchronous Address Advance/Load: When HIGH, this input used advance internal burst counter, controlling burst access after external address loaded. When ADV/LD# HIGH, R/W# ignored. ADV/LD# clocks address rising edge. Synchronous Clock Enable: This active input permits propagate throughout device. When CKE# HIGH, device ignores input effectively internally extends previous cycle. This input must meet setup hold times around rising edge CLK. Snooze Enable: This active HIGH, asynchronous input causes device enter low-power standby mode which data memory array retained. When active, other inputs ignored.
BWa# BWb# BWc# BWd#
Input
Input
Input
CE2#
Input
Input
(G#)
Input
ADV/LD# Input
CKE#
Input
Input
(continued next page)
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
TQFP DESCRIPTIONS (continued)
x32/x36 SYMBOL TYPE R/W# Input DESCRIPTION Read/Write: This input determines cycle type when ADV/LD# only means determining READs WRITEs. READ cycles converted into WRITEs (and vice versa) other than loading address. this permits BYTE WRITE operations must meet setup hold times around rising edge CLK. Full bus-width WRITEs occur byte write enables LOW. Input/ SRAM Data I/Os: Byte pins; Byte Output pins; Byte pins; Byte pins. Input data must meet setup hold times around rising edge CLK.
72-74 22-24
56-59, 72-75, 6-9, 22-25,
NC/DQa NC/DQb NC/DQc NC/DQd MODE Input (LBO#)
Connect/Data Bits: version, these pins connect (NC) left floating connected minimize thermal impedance. version, these bits DQs. Mode: This input selects burst sequence. this selects linear burst. HIGH this selects interleaved burst. alter input state while device operating. LBO# JEDEC-standard term MODE. Connect: These pins left floating connected minimize thermal impedance.
1-3, 28-30, 51-53,
VDDQ
Supply Supply Supply
Function: These internally connected will have capacitance input pins. allowable leave these pins unconnected driven signals. Reserved address expansion, becomes density becomes 16Mb density. Use: These signals either unconnected wired minimize thermal impedance. Power Supply: Electrical Characteristics Operating Conditions range. Isolated Output Buffer Supply: Electrical Characteristics Operating Conditions range. Ground: GND.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
LAYOUT (TOP VIEW) 165-PIN FBGA
x32/x36
DQPb MODE (LBO#) VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQPa BWa# R/W# (G#) BWb# CE2# CKE# ADV/LD#
BWc# BWb# CE2# CKE# ADV/LD#
BWd# BWa# R/W# (G#)
NC/DQPc
VDDQ VDDQ
NC/DQPb
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
NC/DQPd
VDDQ VDDQ
NC/DQPa
MODE (LBO#)
VIEW
VIEW
Connect (NC) used version. Parity (DQPx) used version. NOTE: Pins reserved address expansion; 8Mb, 16Mb respectively.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
FBGA DESCRIPTIONS
x32/x36 SYMBOL TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs registered must meet setup hold times around rising edge CLK. 10A, 10A, 10B, 10P, 10B, 10P, 10R, 11A, 10R,
BWa# BWb# BWc# BWd#
Input
Synchronous Byte Write Enables: These active inputs allow individual bytes written must meet setup hold times around rising edge CLK. byte write enable WRITE cycle HIGH READ cycle. version, BWa# controls DQas DQPa; BWb# controls DQbs DQPb. versions, BWa# controls DQas DQPa; BWb# controls DQbs DQPb; BWc# controls DQcs DQPc; BWd# controls DQds DQPd. Parity only available versions. Clock: This signal registers address, data, chip enable, byte write enables, burst control inputs rising edge. synchronous inputs must meet setup hold times around clock's rising edge. Synchronous Chip Enable: This active input used enable device. sampled only when external address loaded. Synchronous Chip Enable: This active input used enable device sampled only when external address loaded. Synchronous Clock Enable: This active input permits propagate throughout device. When CKE# HIGH, device ignores input effectively internally extends previous cycle. This input must meet setup hold times around rising edge CLK. Snooze Enable: This active HIGH, asynchronous input causes device enter low-power standby mode which data memory array retained. When active, other inputs ignored. Read/Write: This input determines cycle type when ADV/LD# only means determining READs WRITEs. READ cycles converted into WRITEs (and vice versa) other than loading address. this permits BYTE WRITE operations must meet setup hold times around rising edge CLK. Full bus-width WRITEs occur byte write enables LOW. Synchronous Chip Enable: This active HIGH input used enable device sampled only when external address loaded. Output Enable: This active LOW, asynchronous input enables data output drivers.
Input
Input
CE2#
Input
CKE#
Input
Input
R/W#
Input
Input
OE#(G#)
Input
(continued next page)
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
FBGA DESCRIPTIONS (continued)
x32/x36 SYMBOL ADV/LD# TYPE DESCRIPTION Input Synchronous Address Advance/Load: When HIGH, this input used advance internal burst counter, controlling burst access after external address loaded. When ADV/LD# HIGH, R/W# ignored. ADV/LD# clocks address rising edge. Input Mode: This input selects burst sequence. this input selects "linear burst." HIGH this input selects "interleaved burst." alter input state while device operating.
MODE (LB0#)
10J, 10K, 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11K, 11L, 10D, 10E, 10F, 10G, 11D, 11E, 11F,
Input/ SRAM Data I/Os: version, Byte associated DQa's; Output Byte associated with DQb's. versions, Byte associated with DQa's; Byte associated with DQb's; Byte associated with DQc's; Byte associated with DQd's. Input data must meet setup hold times around rising edge CLK.
NC/DQPa NC/DQPb NC/DQPc NC/DQPd
Connect/Parity Data I/Os: version, these Connect (NC). version, Byte parity DQPa; Byte parity DQPb. version, Byte parity DQPa; Byte parity DQPb; Byte parity DQPc; Byte parity DQPd.
Supply Power Supply: Electrical Characteristics Operating Conditions range.
VDDQ
Supply Isolated Output Buffer Supply: Electrical Characteristics Operating Conditions range.
(continued next page)
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
FBGA DESCRIPTIONS (continued)
x32/x36 SYMBOL TYPE Supply Ground: GND. DESCRIPTION 10C, 10D, 10E, 10F, 10G, 10H, 10N, 11B, 11J, 11K, 11L, 11M, 11N, 10C, 10H, 10N, 11A, 11B,
Use: These signals either unconnected wired improve package heat dissipation. Connect: These signals internally connected connected ground improve package heat dissipation. Pins reserved address expansion; 8Mb, 16Mb respectively.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
LAYOUT (TOP VIEW) 119-PIN
x32/x36
VDDQ VDDQ VDDQ VDDQ VDDQ VIEW VDDQ MODE (LBO#) CKE# VDDQ BWa# VDDQ R/W# BWb# OE#(G#) VDDQ ADV/LD# CE2# VDDQ
VDDQ NC/DQc VDDQ VDDQ VDDQ NF/DQPd VDDQ VIEW VDDQ MODE (LBO#) NC/DQPa CKE# VDDQ BWd# BWa# VDDQ R/W# BWc# BWb# OE#(G#) VDDQ NC/DQb ADV/LD# CE2# VDDQ
NOTE: Pins reserved address expansion, 16Mb respectively. Connect (NC) used version. Parity (DQPx) used version. Pins have connected directly input voltage VIH.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
DESCRIPTIONS
x32/x36 SYMBOL TYPE DESCRIPTION Input Synchronous Address Inputs: These inputs registered must meet setup hold times around rising edge CLK.
BWa# BWb# BWc# BWd#
Input Synchronous Byte Write Enables: These active inputs allow individual bytes written must meet setup hold times around rising edge CLK. byte write enable WRITE cycle HIGH READ cycle. version, BWa# controls DQa's DQPa; BWb# controls DQb's DQPb. versions, BWa# controls DQa's DQPa; BWb# controls DQb's DQPb; BWc# controls DQc's DQPc; BWd# controls DQd's DQPd. Parity only available versions. Input Synchronous Clock Enable: This active input permits propagate throughout device. When CKE# HIGH, device ignores input effectively internally extends previous cycle. This input must meet setup hold times around rising edge CLK. Input Read/Write: This input determines cycle type when ADV/ only means determining READs WRITEs. READ cycles converted into WRITEs (and vice versa) other than loading address. this permits BYTE WRITE operations must meet setup hold times around rising edge CLK. Full bus-width WRITEs occur byte write enables LOW. Input Clock: This signal registers address, data, chip enable, byte write enables burst control inputs rising edge. synchronous inputs must meet setup hold times around clock's rising edge. Input Synchronous Chip Enable: This active input used enable device conditions internal ADSP#. sampled only when external address loaded. Input Synchronous Chip Enable: This active input used enable device sampled only when external address loaded. Input Snooze Enable: This active HIGH, asynchronous input causes device enter low-power standby mode which data memory array retained. When active, other inputs ignored. Input Synchronous Chip Enable: This active HIGH input used enable device sampled only when external address loaded. (continued next page)
CKE#
R/W#
CE2#
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
DESCRIPTIONS (continued)
x32/x36 SYMBOL TYPE DESCRIPTION Input Output Enable: This active LOW, asynchronous input enables data output drivers. ADV#/LD# Input Synchronous Address Advance/Load: When HIGH, this input used advance internal burst counter, controlling burst access after external addressis loaded. When ADV#/LD# HIGH, R/W# ignored. ADV#/LD# clocks address rising edge. MODE Input Mode: This input selects burst sequence. this input selects "linear burst." HIGH this input selects "interleaved burst." alter input state while device operating. Input Function: These pins internally connected will have capacitance input pins. allowable leave these pins unconnected driven signals. These pins reserved address expansion; becomes density becomes 16Mb density. Input/ SRAM Data I/Os: version, Byte DQa's; Byte Output DQb's. versions, Byte DQa's; Byte DQb's; Byte DQc's; Byte DQd's. Input data must meet setup hold times around rising edge CLK.
NC/DQPa NC/DQPb NC/DQPc NC/DQPd
Connect/Parity Data I/Os: version, these Connect (NC). version, Byte parity DQPa; Byte parity DQPb. version, Byte parity DQPa; Byte parity DQPb; Byte parity DQPc; Byte parity DQPd.
Supply Power Supply: Electrical Characteristics Operating Conditions range. Supply Isolated Output Buffer Supply: Electrical Characteristics Operating Conditions range.
Supply Ground: GND.
(continued next page)
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
DESCRIPTIONS (continued)
x32/x36 DESCRIPTION Use: These signals either unconnected wired improve package heat dissipation. Connect: These signals internally connected connected ground improve package heat dissipation.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE HIGH)
FIRST ADDRESS (EXTERNAL) X.X00 X.X01 X.X10 X.X11 SECOND ADDRESS (INTERNAL) X.X01 X.X00 X.X11 X.X10 THIRD ADDRESS (INTERNAL) X.X10 X.X11 X.X00 X.X01 FOURTH ADDRESS (INTERNAL) X.X11 X.X10 X.X01 X.X00
LINEAR BURST ADDRESS TABLE (MODE LOW)
FIRST ADDRESS (EXTERNAL) X.X00 X.X01 X.X10 X.X11 SECOND ADDRESS (INTERNAL) X.X01 X.X10 X.X11 X.X00 THIRD ADDRESS (INTERNAL) X.X10 X.X11 X.X00 X.X01 FOURTH ADDRESS (INTERNAL) X.X11 X.X00 X.X01 X.X10
PARTIAL TRUTH TABLE READ/WRITE COMMANDS (x18)
FUNCTION READ WRITE Byte WRITE Byte WRITE Bytes WRITE ABORT/NOP R/W# BWa# BWb#
NOTE: Using R/W# BYTE WRITE(s), more bytes written.
PARTIAL TRUTH TABLE READ/WRITE COMMANDS (x32/x36)
FUNCTION READ WRITE Byte WRITE Byte WRITE Byte WRITE Byte WRITE Bytes WRITE ABORT/NOP R/W# BWa# BWb# BWc# BWd#
NOTE: Using R/W# BYTE WRITE(s), more bytes written.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
State Diagram SRAM
BURST DESELECT
WRITE READ
READ
BEGIN READ
BEGIN WRITE
WRITE
READ
BURST
BURST BURST READ
BURST
WRITE
BURST WRITE
BURST
KEY:
COMMAND READ WRITE BURST
OPERATION DESELECT READ WRITE BURST READ, BURST WRITE CONTINUE DESELECT
NOTE: STALL IGNORE CLOCK EDGE cycle shown above diagram. This because CKE# HIGH only blocks clock (CLK) input does change state device. States change rising edge clock (CLK).
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
TRUTH TABLE
(Notes 5-10) OPERATION DESELECT Cycle DESELECT Cycle DESELECT Cycle CONTINUE DESELECT Cycle READ Cycle (Begin Burst) READ Cycle (Continue Burst) NOP/DUMMY READ (Begin Burst) DUMMY READ (Continue Burst) WRITE Cycle (Begin Burst) WRITE Cycle (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SNOOZE MODE ADDRESS USED CE2# None None None None External Next External Next External Next None Next Current None ADV/ R/W# CKE# NOTES High-Z High-Z High-Z High-Z
High-Z High-Z
High-Z High-Z High-Z
NOTE: CONTINUE BURST cycles, whether READ WRITE, same control inputs. type cycle performed (READ WRITE) chosen initial BEGIN BURST cycle. CONTINUE DESELECT cycle only entered DESELECT cycle executed first. DUMMY READ WRITE ABORT cycles considered NOPs because device performs external operation. WRITE ABORT means WRITE command given, operation performed. wired minimize number control signals SRAM. device will automatically turn output drivers during WRITE cycle. Some users when turn-on turn-off times meet their requirements. IGNORE CLOCK EDGE command occurs during READ operation, will remain active (Low-Z). occurs during WRITE cycle, will remain High-Z. WRITE operations will performed during IGNORE CLOCK EDGE cycle. means "Don't Care." means logic HIGH. means logic LOW. means byte write signals (BWa#, BWb#, BWc# BWd#) HIGH. means more byte write signals LOW. BWa# enables WRITEs Byte (DQas); BWb# enables WRITEs Byte (DQbs); BWc# enables WRITEs Byte (DQcs); BWd# enables WRITEs Byte (DQds). inputs except must meet setup hold times around rising edge (LOW HIGH) CLK. Wait states inserted setting CKE# HIGH. This device contains circuitry that will ensure that outputs will High-Z during power-up. device incorporates 2-bit burst counter. Address wraps initial address every fourth burst cycle. address counter incremented CONTINUE BURST cycles.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage Supply Relative -0.5V +4.6V Voltage VDDQ Supply Relative -0.5V -0.5V VDDQ 0.5V Storage Temperature (plastic) -55°C +150°C Junction Temperature** +150°C Short Circuit Output Current 100mA *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature airflow. Micron Technical Note TN-05-14 more information.
3.3V ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(0°C +70°C; VDD, VDDQ 3.3V ±0.165 unless otherwise noted) DESCRIPTION Input High (Logic Voltage Input High (Logic Voltage Input (Logic Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Supply Voltage Isolated Output Buffer Supply CONDITIONS pins Output(s) disabled, -4.0mA 8.0mA SYMBOL VDDQ -0.3 -1.0 -1.0 3.135 3.135 3.465 UNITS NOTES
NOTE: voltages referenced (GND). Overshoot: +4.6V tKHKH/2 20mA Undershoot: -0.7V tKHKH/2 20mA Power-up: +3.465V 3.135V 200ms MODE internal pull-up, input leakage ±10µA. load used VOH, testing shown Figure load current higher than shown values. curves available upon request. VDDQ should never exceed VDD. VDDQ externally wired together same power supply 3.3V operation.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
2.5V ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(0°C +70°C; +3.3V ±0.165V; VDDQ +2.5V +0.4V/-0.125V unless otherwise noted) DESCRIPTION Input High (Logic Voltage Input (Logic Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Supply Voltage Isolated Output Buffer Supply CONDITIONS Data (DQx) Inputs Output(s) disabled, VDDQ (DQx) -2.0mA -1.0mA 2.0mA 1.0mA SYMBOL VIHQ VDDQ -0.3 -1.0 -1.0 3.135 2.375 UNITS VDDQ NOTES
TQFP CAPACITANCE
DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS 25°C; 3.3V SYMBOL UNITS NOTES
CAPACITANCE
DESCRIPTION Address/Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS 25°C; 3.3V SYMBOL UNITS NOTES
FBGA CAPACITANCE
DESCRIPTION Address/Control Input Capacitance Output Capacitance Clock Capacitance
NOTE: voltages referenced (GND). Overshoot: +4.6V tKHKH/2 20mA Undershoot: -0.7V tKHKH/2 20mA Power-up: +3.465V 3.135V 200ms MODE internal pull-up, input leakage ±10µA. This parameter sampled.
CONDITIONS 25°C;
SYMBOL
UNITS
NOTES
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
OPERATING CONDITIONS MAXIMUM LIMITS
(Note (0°C +70°C; +3.3V ±0.165V unless otherwise noted) DESCRIPTION Power Supply Current: Operating Power Supply Current: Idle CONDITIONS Device selected; inputs VIH; Cycle time (MIN); MAX; Outputs open Device selected; MAX; CKE# VIH; inputs 0.2; Cycle time (MIN) Device deselected; MAX; inputs 0.2; inputs static; frequency Device deselected; MAX; inputs VIH; inputs static; frequency Device deselected; MAX; ADV/LD# VIH; inputs 0.2; Cycle time (MIN) SYMBOL -7.5 UNITS NOTES
IDD1
CMOS Standby
ISB2
Standby
ISB3
Clock Running
ISB4 ISB2Z
SNOOZE MODE
NOTE: VDDQ +3.3V ±0.165V 3.3V configuration; VDDQ +2.5V +0.4V/-0.125V 2.5V configuration. specified with output current increases with faster cycle times. IDDQ increases with faster cycle times greater output loading. "Device deselected" means device deselected cycle defined truth table. "Device selected" means device active (not deselected mode). Typical values measured 3.3V, 25°C 10ns cycle time. This parameter sampled. Preliminary package data.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
TQFP THERMAL RESISTANCE
DESCRIPTION Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) CONDITIONS Test conditions follow standard test methods procedures measuring thermal impedance, EIA/JESD51. SYMBOL UNITS NOTES °C/W °C/W
TQFP THERMAL RESISTANCE
DESCRIPTION Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) CONDITIONS Test conditions follow standard test methods procedures measuring thermal impedance, EIA/JESD51. SYMBOL UNITS NOTES °C/W °C/W
THERMAL RESISTANCE
DESCRIPTION Junction Ambient (Airflow 1m/s) Junction Case (Top) Junction Pins (Bottom) CONDITIONS Test conditions follow standard test methods procedures measuring thermal impedance, EIA/JESD51. SYMBOL UNITS NOTES °C/W °C/W °C/W
FBGA THERMAL RESISTANCE
DESCRIPTION Junction Ambient (Airflow 1m/s) Junction Case (Top) Junction Pins (Bottom) CONDITIONS Test conditions follow standard test methods procedures measuring thermal impedance, EIA/JESD51. SYMBOL UNITS NOTES °C/W °C/W °C/W
NOTE: VDDQ +3.3V ±0.165V 3.3V configuration; VDDQ +2.5V +0.4V/-0.125V 2.5V configuration. specified with output current increases with faster cycle times. IDDQ increases with faster cycle times greater output loading. "Device deselected" means device deselected cycle defined truth table. "Device selected" means device active (not deselected mode). Typical values measured 3.3V, 25°C 10ns cycle time. This parameter sampled. Preliminary package data.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
ELECTRICAL CHARACTERISTICS
(Notes (0°C +70°C; +3.3V ±0.165V; mode)
DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock time Output Times Clock output valid Clock output invalid Clock output Low-Z Clock output High-Z output valid output Low-Z output High-Z Setup Times Address Clock enable (CKE#) Control signals Data-in Hold Times Address Clock enable (CKE#) Control signals Data-in NOTE: SYMBOL
tKHKH tKHKL tKLKH tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX tGHQZ tAVKH tEVKH tCVKH tDVKH tKHAX tKHEX tKHCX tKHDX
-7.5
UNITS NOTES
This parameter sampled. Measured HIGH above below VIL. Refer Technical Note TN-55-01, "Designing with SRAMs," more thorough discussion these parameters. This parameter sampled. This parameter measured with output loading shown Figure 3.3V Figure 2.5V I/O. Transition measured ±200mV from steady state voltage. considered "Don't Care" during WRITEs; however, controlling help fine-tune system turnaround timing. This synchronous device. addresses must meet specified setup hold times rising edges when they being registered into device. other synchronous inputs must meet setup hold times with stable logic levels rising edges clock (CLK) when chip enabled. Chip enable must valid each rising edge when ADV/LD# remain enabled. Test conditions specified with output loading shown Figure 3.3V (VDDQ +3.3V ±0.165V) Figure 2.5V (VDDQ +2.5V +0.4V/-0.125V). WRITE cycle defined R/W# having been registered into device ADV/LD# LOW. READ cycle defined R/W# HIGH with ADV/LD# LOW. Both cases must meet setup hold times.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
3.3V TEST CONDITIONS
Input pulse levels 3.3V Input rise fall times Input timing reference levels 1.5V Output reference levels 1.5V Output load Figures
2.5V TEST CONDITIONS
Input pulse levels 2.5V Input rise fall times Input timing reference levels 1.25V Output reference levels 1.25V Output load Figures
3.3V Output Load Equivalents
1.5V
2.5V Output Load Equivalents
1.25V
Figure
Figure
+3.3V
+2.5V
Figure
Figure
LOAD DERATING CURVES
Micron 256K 128K 128K SRAM timing dependent upon capacitive loading outputs. Consult factory copies current versus voltage curves.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
SNOOZE MODE
SNOOZE MODE low-current, "power-down" mode which device deselected current reduced ISB2Z. duration SNOOZE MODE dictated length time HIGH state. After device enters SNOOZE MODE, inputs except become disabled outputs High-Z. asynchronous, active HIGH input that causes device enter SNOOZE MODE. When becomes logic HIGH, ISB2Z guaranteed after time tZZI met. READ WRITE operation pending when device enters SNOOZE MODE guaranteed complete successfully. Therefore, SNOOZE MODE must initiated until valid pending operations completed. Similarly, when exiting SNOOZE MODE during tRZZ, only DESELECT READ cycle should given.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SNOOZE MODE Current during SNOOZE MODE Version) active input ignored inactive input sampled active snooze current inactive exit snooze current
NOTE: This parameter sampled.
CONDITIONS
SYMBOL ISB2Z ISB2ZP
tRZZ tZZI tRZZI
UNITS
NOTES
2(tKHKH) 2(tKHKH) 2(tKHKH)
SNOOZE MODE WAVEFORM
SUPPLY ISB2Z RZZI DESELECT READ Only
INPUTS (except
Outputs
High-Z
DON'T CARE
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
READ/WRITE TIMING
tEVKH tKHEX
KHKH
tKHKL tKLKH
CKE#
tCVKH tKHCX
ADV/LD# R/W# BWx# ADDRESS
tAVKH tKHAX
tDVKH tKHDX
tKHQV tKHQX1 tKHQX
tGLQV
tKHQZ
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
tGHQZ
Q(A4+1)
D(A5)
Q(A6)
tKHQX
COMMAND
WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5)
tGLQX
READ Q(A6)
WRITE D(A7)
DESELECT
DON'T CARE
UNDEFINED
READ/WRITE TIMING PARAMETERS
tKHKH
tKHKL tKLKH tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX
-7.5
UNITS tGHQZ tAVKH
tEVKH tCVKH tDVKH tKHAX tKHEX tKHCX tKHDX
-7.5
UNITS
NOTE:
this waveform, tied LOW. Burst sequence order determined MODE linear, interleaved). BURST operations optional. represents three signals. When represents CE2# Data coherency provided possible operations. READ initiated, most current data used. most recent data from input data register.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
NOP, STALL, DESELECT CYCLES
CKE# ADV/LD# R/W# BWx# ADDRESS COMMAND
WRITE D(A1) READ Q(A2) STALL
D(A1)
READ Q(A3)
Q(A2)
WRITE D(A4)
tKHQZ
Q(A3)
STALL
D(A4)
READ Q(A5) DESELECT
Q(A5)
tKHQX
CONTINUE DESELECT
DON'T CARE
UNDEFINED
NOP, STALL, DESELECT TIMING PARAMETERS
tKHQX tKHQZ -7.5 UNITS
NOTE: IGNORE CLOCK EDGE STALL cycle (clock illustrates CKE# being used create "pause." WRITE performed during this cycle. this waveform, tied LOW. represents three signals. When represents CE2# Data coherency provided possible operations. READ initiated, most current data used. most recent data from input data register.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
0.15
+0.03 -0.02
0.32
+0.06 -0.10
22.10
+0.10 -0.15
0.65
20.10 ±0.10 DETAIL
0.62 14.00 ±0.10 +0.20 -0.05 GAGE PLANE
1.50 ±0.10 0.10
16.00
0.25
0.10
+0.10 -0.05
1.00 (TYP) 0.60 ±0.15 DETAIL
1.40 ±0.05
NOTE: dimensions millimeters typical where noted. Package width length include mold protrusion; allowable mold protrusion 0.25mm side.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
165-PIN FBGA
0.85 ±0.075 0.12
SEATING PLANE
BALL 165X 0.45 SOLDER BALL DIAMETER REFERS POST REFLOW CONDITION. PRE-REFLOW DIAMETER 0.40 10.00 1.00 BALL 1.20
7.50 ±0.05
15.00 ±0.10
14.00
7.00 ±0.05 1.00
6.50 ±0.05 5.00 ±0.05 13.00 ±0.10
MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE: PLASTIC LAMINATE SOLDER BALL MATERIAL: EUTECTIC SOLDER BALL PAD: .33mm
NOTE: dimensions millimeters typical where noted.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
119-PIN
22.00 ±0.20
19.94 ±0.10 Substrate material: resin laminate 0.60 ±0.10 14.00 ±0.10 11.94 ±0.10 SEATING PLANE 0.15 2.40 0.90 ±0.10
CORNER
CORNER
0.75 ±0.15 (dimension applies noncollapsed solder ball)
1.27 (TYP) 7.62
1.27 (TYP) 20.32
NOTE: dimensions millimeters typical where noted. Solder ball land 0.6mm.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron registered trademark Micron logo logo trademarks Micron Technology, Inc. Zero Turnaround trademarks Integrated Device Technology, Inc., architecture supported Micron Technology, Inc., Motorola, Inc.
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED SRAM
REVISION HISTORY
Removed note "Not Recommended Designs," Rev. 6/01 June 7/01 Added Industrial Temperature note references, Rev. 3/01, FINAL March 6/01 Added 119-pin PBGA package, Rev. 1/01, FINAL January 10/01 Removed FBGA Part Marking Guide, 8/00-A, FINAL August 22/00 Changed FBGA capacitance values, 8/00, FINAL August 7/00 2.5pF from 4pF; MAX. 3.5pF from from 6pF; MAX. from CCK; 2.5pF from 5pF; MAX. 3.5pF from Added FBGA Part Marking Guide, Rev. 7/00, Preliminary July 13/00 Removed 119-pin PBGA package references Added 165-pin FBGA package, Rev. 6/00, Preliminary 23/00 Removed "Smart ZBT" references
4Mb: 256K 128K 32/36 Pipelined SRAM MT55L256L18P1_D.p65 Rev. 10/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.

ZBT® SRAM High frequency percent utilization Fast cycle times: 6n

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