2.5V/1.8V In-System Programmable SuperFAST High Density PLDs Dece

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2.5V/1.8V In-System Programmable SuperFAST High Density PLDs Dece

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ispMACH 4000B/C Family
2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
December 2001 Data Sheet
Features
High Performance
fMAX 350MHz maximum operating frequency 2.5ns propagation delay four global clock pins with programmable clock polarity control output
Broad Device Offering
macrocells pins pins/balls TQFP fpBGA packages Commercial industrial temperature ranges
Easy System Integration
Operation with 3.3V, 2.5V 1.8V LVCMOS Operation with 2.5V (4000B) 1.8V (4000C) supplies Hot-socketing Open-drain capability Input pull-up, pull-down bus-keeper Programmable output slew rate 3.3V compatible IEEE 1149.1 boundary scan testable 2.5V/1.8V In-System Programmable (ISPTM) using IEEE 1532 compliant interface pins with fast setup path
Ease Design
Enhanced macrocells with individual clock, reset, preset clock enable controls four global controls Individual local control Excellent First-Time-Fitand refit Fast path, SpeedLockingPath, wide-PT path Wide input gating input logic blocks) fast counters, state machines address decoders
Power
1.8V core E2CMOS® technology CMOS design techniques provide static dynamic power
Table ispMACH 4000B/C Family Selection Guide
ispMACH 4032B/C* Macrocells User Options (ns) (ns) (ns) fMAX (MHz) Supply Voltages Pins/Package 30/32 1.75 2.5/1.8V TQFP TQFP ispMACH 4064B/C* 30/32/64 1.75 2.5/1.8V TQFP TQFP TQFP ispMACH 4128B/C* 64/92 2.5/1.8V ispMACH 4256B/C* 64/128/160 2.5/1.8V ispMACH 4384B/C* 128/192 2.5/1.8V ispMACH 4512B/C* 128/208 2.5/1.8V
TQFP TQFP
TQFP TQFP fpBGA** TQFP fpBGA TQFP fpBGA
*Preliminary **128-I/O 160-I/O configuration.
www.latticesemi.com
ispm4k_04
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4000 Introduction
high performance ispMACH 4000 family from Lattice offers SuperFAST CPLD solution. family blend Lattice's most popular architectures: ispLSI® 2000 ispMACH Retaining best both families, ispMACH 4000 architecture focuses significant innovations combine highest performance with power flexible CPLD family. ispMACH 4000 combines high speed power with flexibility needed ease design. With robust Global Routing Pool Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention density migration. ispMACH 4000 family offers densities ranging from macrocells. There multiple density-I/O combinations Thin Quad Flat Pack (TQFP) Fine Pitch (fpBGA) packages ranging from pins/balls. Table shows macrocell, package options, along with other parameters. ispMACH 4000 family enhanced system integration capabilities. supports 2.5V (4000B) 1.8V (4000C) supply voltages 3.3V, 2.5V 1.8V interface voltages. ispMACH 4000 also offers enhanced features such slew rate control, compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs socketing. ispMACH 4000 family members 2.5V/1.8V in-system programmable through IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing automated test equipment.
Overview
ispMACH 4000 devices consist multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected Global Routing Pool (GRP). Output Routing Pools (ORPs) connect GLBs Blocks (IOBs), which contain multiple cells. This architecture shown Figure Figure Functional Block Diagram
CLK0/I CLK1/I CLK2/I CLK3/I VCCO0 VCCO1 Block Bank Generic Logic Block Block GOE0 GOE1
Block Bank
Global Routing Pool
Generic Logic Block
Generic Logic Block
Block
Generic Logic Block
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
I/Os ispMACH 4000 split into banks. Each bank separate power supply. Inputs support variety standards independent chip bank power supply. Outputs support standards compatible with power supply provided bank. Support variety standards helps designers implement designs mixed voltage environments.
ispMACH 4000 Architecture
There total GLBs ispMACH 4032, increasing GLBs ispMACH 4512. Each inputs. inputs come from outputs from brought back into connected inputs other device. Even feedback signals return same GLB, they still must through GRP. This mechanism ensures that GLBs communicate with each other with consistent predictable delays. outputs from also sent ORP. then sends them associated cells block.
Generic Logic Block
ispMACH 4000 consists programmable array, logic allocator, macrocells clock generator. Macrocells decoupled from product terms through logic allocator pins decoupled from macrocells through ORP. Figure illustrates GLB. Figure Generic Logic Block
CLK0 CLK1 CLK2 CLK3
Clock Generator
1+OE Feedback Signals 1+OE
1+OE 1+OE 1+OE 1+OE 1+OE 1+OE Product Term Output Enable Sharing
Logic Allocator
Inputs from
Array
programmable Array consists inputs output product terms. inputs from used form lines Array (true complement inputs). Each line array connected output product terms wired-AND. Each logic product terms feed logic allocator with remaining three control product terms feeding Shared Clock, Shared Initialization Shared Shared Clock Shared Initialization signals optionally inverted before being macrocells. Every five product terms from logic product terms forms product term cluster starting with PT0. There product term cluster every macrocell GLB. Figure graphical representation Array.
Array Inputs, Product Terms
Macrocells
Lattice Semiconductor
Figure Array
In[0] In[34] In[35]
ispMACH 4000B/C Family Data Sheet
Cluster
PT75 PT76 PT77 Cluster PT78 PT79 PT80 Shared Clock PT81 Shared Initialization PT82 Shared PTOE Note: Indicates programmable fuse.
Enhanced Logic Allocator
Within logic allocator, product terms allocated macrocells product term clusters. Each product term cluster associated with macrocell. cluster size ispMACH 4000 family (total product terms. software automatically considers availability distribution product term clusters fits functions within GLB. logic allocator designed provide three speed paths: 5-PT fast bypass path, 20-PT Speed Locking path 80-PT path. availability these three paths lets designers trade timing variability increased performance. enhanced Logic Allocator ispMACH 4000 family consists following blocks: Product Term Allocator Cluster Allocator Wide Steering Logic Figure shows macrocell slice Logic Allocator. There such slices GLB. Figure Macrocell Slice
from from Fast 5-PT Path 1-80 (MC)
From 5-PT
Cluster
Individual Product Term Allocator
from Cluster Allocator
from
SuperWIDESteering Logic
Lattice Semiconductor Product Term Allocator
ispMACH 4000B/C Family Data Sheet
product term allocator assigns product terms from cluster either logic control applications required design being implemented. Product terms that used logic steered into 5-input gate associated with cluster. Product terms that used control steered either macrocell cell associated with cluster. Table shows available functions each five product terms cluster. gate output connects associated cell, providing fast path narrow combinatorial functions, logic allocator. Table Individual Steering
Product Term PTn+1 PTn+2 PTn+3 PTn+4 Logic Logic Logic Logic Logic Logic Single XOR/OR Individual Clock Clock) Individual Initialization Individual Clock Enable Initialization/CE) Individual Initialization Initialization) Individual (PTOE) Control
Cluster Allocator
cluster allocator allows clusters steered neighboring macrocells, thus allowing creation functions with more product terms. Table shows which clusters steered which macrocells. Used this manner, cluster allocator used form functions product terms. Additionally, cluster allocator accepts inputs from wide steering logic. Using these inputs, functions product terms created. Table Available Clusters Each Macrocell
Macrocell Available Clusters
Wide Steering Logic
wide steering logic allows output cluster allocator connected input cluster allocator n+4. Thus, cluster chains formed with product terms, supporting wide product term functions allowing performance increased through single implementation. Table shows product term chains.
Lattice Semiconductor
Table Product Term Expansion Capability
Expansion Chains Chain-0 Chain-1 Chain-2 Chain-3
ispMACH 4000B/C Family Data Sheet
Macrocells Associated with Expansion Chain (with Wrap Around)
Macrocell
Every time super cluster allocator used, there incremental delay tEXP When super cluster allocator used, destinations other than being steered given value ground (i.e., super cluster steered (n+4), then ground).
Macrocell
macrocells driven outputs from logic allocator. Each macrocell contains programmable gate, programmable register/latch, along with routing logic control functions. Figure shows graphical representation macrocell. macrocells feed GRP. direct input from cell allows designers macrocell construct high-speed input registers. programmable delay this path allows designers choose between fastest possible set-up time zero hold time. Figure Macrocell
Power-up Reset
Shared Initialization Initialization (optional) Initialization/CE (optional) Delay From Cell
From Logic Allocator
D/T/L
Single
Block CLK0 Block CLK1 Block CLK2 Block CLK3 Clock (optional) Shared Clock
Enhanced Clock Multiplexer
clock input flip-flop select four block clocks along with shared clock, true complement forms optional individual term clock. multiplexer structure used select clock. eight sources clock multiplexer follows: Block CLK0 Block CLK1
Lattice Semiconductor
Block CLK2 Block CLK3 Clock Clock Inverted Shared Clock Ground
ispMACH 4000B/C Family Data Sheet
Clock Enable Multiplexer
Each macrocell clock enable multiplexer. This allows clock enable signal selected from following four sources: Initialization/CE Initialization/CE Inverted Shared Clock Logic High
Initialization Control
ispMACH 4000 family architecture accommodates both block-level macrocell-level reset capability. There block-level initialization term that distributed macrocell registers GLB. macrocell level, product terms "stolen" from cluster associated with macrocell used set/reset functionality. reset/preset swapping feature each macrocell allows reset preset exchanged, providing flexibility. Note that reset/preset swapping selection feature affects power-up reset well. flip-flops power known state predictable system initialization. macrocell configured signal from block-level initialization, then that macrocell will during device power-up. macrocell configured RESET signal from block-level initialization configured set/reset, then that macrocell will RESET powerup. guarantee initialization values, rise must monotonic, clock must inactive until reset delay time elapsed.
Clock Generator
Each ispMACH 4000 device four clock pins that also routed used inputs. These pins drive clock generator each GLB, shown Figure clock generator provides four clock signals that used anywhere GLB. These four clock signals consist number combinations true complement edges global clock signals. Figure Clock Generator
CLK0 Block CLK0
CLK1
Block CLK1
CLK2 Block CLK2
CLK3
Block CLK3
Lattice Semiconductor Output Routing Pool (ORP)
ispMACH 4000B/C Family Data Sheet
Output Routing Pool allows macrocell outputs connected several cells within block. This provides greater flexibility determining pinout allows design changes occur without affecting pinout. output routing pool also provides parallel capability routing macrocell-level product terms. This allows product term follow macrocell output switched between cells. Additionally, output routing pool allows macrocell output true complement forms 5-PT bypass signal bypass output routing multipliers feed cell directly. enhanced ispMACH 4000 family consists following elements: Output Routing Multiplexers Routing Multiplexers Output Routing Pool Bypass Multiplexers Figure shows structure from cell perspective. This referred slice. Each many slices there cells corresponding block. Figure Slice
Routing Multiplexer From Macrocell Cell
5-PT Fast Path From Macrocell
Bypass Multiplexer Cell Output
Output Routing Multiplexer
Output Routing Multiplexers
details connections between macrocells cells vary across devices within device dependent maximum number I/Os available. Tables provide connection details. Table Combinations Blocks with I/Os
Cell M10, M10, M11, M12, M10, M11, M12, M13, M14, M10, M11, M12, M13, M14, M15, M12, M13, M14, M15, M14, M15, Available Macrocells
Lattice Semiconductor
Table Combinations Blocks with I/Os
Cell M10, M10, M11, M10, M11, M12, M10, M11, M12, M13, M10, M11, M12, M13, M14, M10, M11, M12, M13, M14, M15, M10, M11, M12, M13, M14, M15, M11, M12, M13, M14, M15, M12, M13, M14, M15, M13, M14, M15, M14, M15, M15,
ispMACH 4000B/C Family Data Sheet
Available Macrocells
Table Combinations Blocks with I/Os
Cell M10, M10, M11, M12, M13, M14, M12, M13, M14, M15, Available Macrocells
Table Combinations Blocks with I/Os
Cell M10, M10, M11, M12, M10, M11, M12, M13, M14, M10, M11, M12, M13, M14, M15, M12, M13, M14, M15, M14, M15, M10, M11, M12, M13, M14, M15, Available Macrocells
Lattice Semiconductor Bypass Fast Output Multiplexers
ispMACH 4000B/C Family Data Sheet
bypass fast-path output multiplexer multiplexer allows 5-PT fast path bypass connected directly with either regular output inverted output. This multiplexer also allows register output bypass achieve faster tCO.
Output Enable Routing Multiplexers
Routing Pool provides corresponding local output enable (OE) product term cell.
Cell
cell contains following programmable elements: output buffer, input buffer, multiplexer maintenance circuitry. Figure details cell. Figure Cell
From VCCO
VCCO From Macrocell
*Global fuses
Each output supports variety output standards dependent VCCO supplied bank. Outputs also configured open drain operation. Each input programmed support variety standards, independent VCCO supplied bank. standards supported are: LVTTL LVCMOS LVCMOS 3.3V Compatible LVCMOS I/Os dedicated inputs have capability provide bus-keeper latch, Pull-up Resistor Pull-down Resistor. fourth option provide none these. selection done global basis. default both hardware software such that when device erased user does specify, input structure configured Pull-up Resistor. Each ispMACH 4000 device individually programmable output slew rate control bit. Each output individually configured higher speed transition (~3V/ns) lower noise transition (~1V/ns). highspeed designs with long, unterminated traces, slow-slew rate will introduce fewer reflections, less noise keep ground bounce minimum. designs with short traces well terminated lines, fast slew rate used achieve highest speed. slew rate adjusted independent power.
Global Generation
Most ispMACH 4000 family devices have 4-bit wide Global Bus, except ispMACH 4032 device that 2-bit wide Global Bus. This derived from 4-bit internal global dual purpose pins. Each signal that drives optionally inverted.
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Each block-level that connects bits Global with four fuses. Hence, 256-macrocell device (with blocks), each line driven from product terms. Figures show graphical representation global generation. Figure Global Generation Devices Except ispMACH 4032
Internal Global lines) Global 4-Bit Global
Shared PTOE (Block Shared PTOE (Block
Global Fuses
Fuse connection Hard wired
(0:3) cells
Figure Global Generation ispMACH 4032
Internal Global lines)
Global
4-Bit Global
Shared PTOE (Block Shared PTOE (Block
Global Fuses
Fuse connection Hard wired
(0:3) cells
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Power Power Management
ispMACH 4000 family designed with high speed power design techniques offer both high speed power. With advanced power cell sense-amplifier design approach (full CMOS logic approach), ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering standby power without needing "turbo bits" other power management schemes associated with traditional sense-amplifier approach.
IEEE 1149.1-Compliant Boundary Scan Testability
ispMACH 4000 devices have boundary scan cells compliant IEEE 1149.1 standard. This allows functional testing circuit board which device mounted through serial scan path that access critical logic notes. Internal registers linked internally, allowing test data shifted loaded directly onto test nodes, test node data captured shifted verification. addition, these devices linked into board-level serial scan path more board-level testing. test access port operates with LVCMOS interface that corresponds power supply voltage.
Quick Configuration
facilitate most efficient board test, physical nature cells must before running continuity tests. these tests fast, nature, overhead time that required configuration I/Os' physical nature should minimal that board test time minimized. ispMACH 4000 family devices allows this offering user ability quickly configure physical nature cells. This quick configuration takes milliseconds complete, whereas takes seconds entire device programmed. Lattice's ispVMSystem programming software either perform quick configuration through parallel port, generate test vectors necessary third-party test system.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides number significant benefits including: rapid prototyping, lower inventory levels, higher quality ability make in-field modifications. ispMACH 4000 devices provide In-System Programming (ISPTM) capability through Boundary Scan Test Access Port. This capability been implemented manner that ensures that port remains complaint IEEE 1149.1 standard. using IEEE 1149.1 communication interface through which achieved, users benefit standard, welldefined interface. ispMACH 4000 devices also compliant with IEEE 1532 standard. ispMACH 4000 devices programmed across commercial temperature voltage range. PCbased Lattice software facilitates in-system programming ispMACH 4000 devices. software takes JEDEC file output produced design implementation software, along with information about scan chain, creates vectors used drive scan chain. software these vectors drive scan chain parallel port Alternatively, software output files formats understood common automated test equipment. This equipment then used program ispMACH 4000 devices during testing circuit board.
Security
programmable security provided ispMACH 4000 devices deterrent unauthorized copying array configuration patterns. Once programmed, this defeats readback programmed pattern device programmer, securing proprietary designs from competitors. Programming verification also defeated security bit. only reset erasing entire device.
Socketing
ispMACH 4000 devices well-suited applications that require socketing capability. socketing device requires that device, during power-up down, tolerate active signals I/Os inputs without being damaged. Additionally, requires that effects loading minimal active signals.
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Density Migration
ispMACH 4000 family been designed ensure that different density devices same package have same pin-out. Furthermore, architecture ensures high success rate when performing design migration from lower density parts higher density parts. many cases, possible shift lower utilization design targeted high density device lower density device. However, exact details final resource utilization will impact likely success each case.
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Absolute Maximum Ratings1,
ispMACH 4000C (1.8V) ispMACH 4000B (2.5V) Supply Voltage -0.5 2.5V .-0.5 5.5V Output Supply Voltage VCCO -0.5 4.5V .-0.5 4.5V Input Tristate Voltage Applied4 -0.5 4.5V .-0.5 4.5V Storage Temperature 150°C 150°C Junction Temperature (Tj) with Power Applied 150°C 150°C
Stress above those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation device these other conditions above those indicated operational sections this specification implied. Compliance with Lattice Thermal Management document required. voltages referenced GND. Overshoot undershoot (VIH (MAX) volts permitted duration 20ns.
Recommended Operating Conditions
Symbol TJCOM TJIND Supply Voltage 1.8V Devices Supply Voltage 2.5V Devices Junction Commercial Temperature Junction Industrial Temperature Parameter 1.65 1.95 Units
Erase Reprogram Specifications
Parameter Erase/Reprogram Cycle
Note: Valid over commercial temperature range.
1,000
Units Cycles
Socketing Characteristics1,2,3
Symbol Parameter Input Leakage Current Condition (MAX) ±150 Units
Insensitive sequence VCCO. However, assumes monotonic rise/fall rates VCCO. (MAX), VCCO VCCO (MAX). additive ,IPD IBH. Device defaults pull-up until fuse circuitry active.
Recommended Operating Conditions
VCCO (V)1 Standard LVTTL LVCMOS LVCMOS LVCMOS 1.65 1.95
Typical values VCCO average values.
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Electrical Characteristics
Over Recommended Operating Conditions
Symbol IIL, IIH1 IBHLS IBHHS IBHLO IBHHO VBHT Parameter Input Leakage Current Weak Pull-up Resistor Current Hold Sustaining Current Hold High Sustaining Current Hold Overdrive Current Hold High Overdrive Current Hold Trip Points Capacitance2 Clock Capacitance2 Global Input Capacitance2 Condition (MAX) 0.7VCCO (MAX) VCCO (MAX) (MAX) VCCO 3.3V, 2.5V, 1.8V 1.8V, (MAX) VCCO 3.3V, 2.5V, 1.8V 1.8V, (MAX) VCCO 3.3V, 2.5V, 1.8V 1.8V, (MAX) (MAX) (MIN) Units
Weak Pull-down Resistor Current (MAX) (MAX)
Input leakage current measured with configured input with output driver tristated. measured with output driver active. maintenance circuits disabled.
Supply Current
Over Recommended Operating Conditions
Symbol ispMACH 4256B/C ICC1, ICC4 Operating Power Supply Current Standby Power Supply Current 2.5V 1.8V 2.5V 1.8V 2.5V 1.8V 2.5V 1.8V 12.5 12.5 Parameter Condition Units
ispMACH 4512B/C ICC1, ICC4
Operating Power Supply Current Standby Power Supply Current
25°C, frequency 1.0MHz. Device configured with 16-bit counters. varies with specific device configuration operating frequency. 25°C
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Electrical Characteristics
Over Recommended Operating Conditions
Standard LVTTL LVCMOS LVCMOS LVCMOS -0.3 -0.3 -0.3 -0.3 -0.3 0.80 0.80 0.70 0.35VCCO 1.70 0.65VCCO 0.40 0.20 0.40 0.20 0.40 0.20 0.40 0.20 VCCO VCCO 0.40 VCCO 0.20 VCCO 0.40 VCCO 0.20 VCCO 0.40 VCCO 0.20 VCCO 0.45 VCCO 0.20 VCCO IOL1 (mA) IOH1 (mA) -4.0 -0.1 -4.0 -0.1 -4.0 -0.1 -2.0 -0.1 -0.5
average current drawn I/Os between adjacent bank connections, between last bank bank, shown logic signals connection table, shall exceed n*8mA. Where number I/Os between bank connections between last bank bank.
Typical Output Current (mA)
3.3V VCCO
Typical Output Current (mA)
2.5V VCCO
Output Voltage
Output Voltage
Typical Output Current (mA)
1.8V VCCO
Output Voltage
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C External Switching Characteristics (Preliminary)
Over Recommended Operating Conditions
Parameter tPD_MC tSIR tSIRZ tHIR tHIRZ tPTOE/DIS tGPTOE/DIS tGOE/DIS tWIR fMAX4 fMAX (Ext.)
13.4
10.0 11.0 12.5 20.0 10.0
-105 10.0 13.4 14.7 16.7 26.7 13.4 Units
Description1,2,3 5-PT bypass combinatorial propagation delay 20-PT combinatorial propagation delay through macrocell register setup time before clock register setup time before clock with T-type register register setup time before clock, input register path register setup time before clock with zero hold register hold time after clock register hold time after clock with T-type register register hold time after clock, input register path register hold time after clock, input register path with zero hold register clock-to-output delay External reset output delay External reset pulse duration Input output local product term output enable/disable Input output global product term output enable/disable Global input output enable/disable Global clock width, high Global gate width (for transparent) high (for high transparent) Input register clock width, high Clock frequency with internal feedback Clock frequency with external feedback, tCO)]
11.6
Timing numbers based default LVCMOS buffers. timing adjusters provided calculate other standards. Measured using standard switching circuit, assuming loading output switching. Pulse widths clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using feedback. Only available industrial grade.
Timing v.2.6
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4512B/C External Switching Characteristics (Preliminary)
Over Recommended Operating Conditions
Parameter tPD_MC tSIR tSIRZ tHIR tHIRZ tPTOE/DIS tGPTOE/DIS tGOE/DIS tWIR fMAX4 fMAX (Ext.)
13.4
10.0 11.0 12.5 20.0 10.0
-105 10.0 13.4 10.0 14.7 16.7 26.7 13.4 Units
Description1,2,3 5-PT bypass combinatorial propagation delay 20-PT combinatorial propagation delay through macrocell register setup time before clock register setup time before clock with T-type register register setup time before clock, input register path register setup time before clock with zero hold register hold time after clock register hold time after clock with T-type register register hold time after clock, input register path register hold time after clock, input register path with zero hold register clock-to-output delay External reset output delay External reset pulse duration Input output local product term output enable/disable Input output global product term output enable/disable Global input output enable/disable Global clock width, high Global gate width (for transparent) high (for high transparent) Input register clock width, high Clock frequency with internal feedback Clock frequency with external feedback, tCO)]
11.6
Timing numbers based default LVCMOS buffers. timing adjusters provided calculate other standards. Measured using standard switching circuit, assuming loading output switching. Pulse widths clock widths less than minimum will cause unknown behavior. Standard 16-bit counter using feedback. Only available industrial grade.
Timing v.0.1
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Timing Model
task determining timing through ispMACH 4000 family, like CPLD, relatively simple. timing model provided Figure shows specific delay paths. Once implementation given function determined either conceptually from software report file, delay path function easily determined from timing model. Lattice design tools report timing delays based same timing model particular design. Note that internal timing parameters given reference only, tested. external timing parameters tested guaranteed every device. more information timing model usage, please refer Technical Note TN1004: ispMACH 4000 Timing Model Design Usage Guidelines. Figure ispMACH 4000 Timing Model
Routing/GLB Delays From Feedback tPDb tPDi tIOI tROUTE tBLA tINREG tINDIO tMCELL tEXP
DATA
tFBK tBUF tIOO tDIS In/Out Delays
Feedback
tORP
SCLK
tGCLK_IN tIOI
tPTCLK tBCLK tPTSR tBSR
C.E. Reg.
Register/Latch Delays
Control Delays tGOE tIOI In/Out Delays
tGPTOE tPTOE
Note: Italicized items optional delay adders.
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C Internal Timing Parameters (Preliminary)
Over Recommended Operating Conditions
Parameter In/Out Delays tGOE tGCLK_IN tBUF tDIS tROUTE tMCELL tINREG tFBK tPDb tPDi tS_PT tST_PT tCOi tCES tCEH tSL_PT tGOi tPDLi tSRi tSRR tBCLK tPTCLK tBSR tPTSR tGPTOE tPTOE Input Buffer Delay Global Delay Global Clock Input Buffer Delay Delay through Output Buffer Output Enable Time Output Disable Time Delay through Macrocell Delay Input Buffer Macrocell Register Delay Internal Feedback Delay 5-PT Bypass Propagation Delay Macrocell Propagation Delay Register Setup Time, Flip-Flop D-Register Setup Clock) Register Setup Time, Flip-Flop Register Setup Time, Flip-Flop Clock) Register Hold Time, Flip-Flop Register Hold Time, Flip-Flop Register Clock Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time Latch Setup Time Clock) Latch Hold Time Latch Gate Time Propagation Delay through Transparent Latch Asynchronous Reset Delay Asynchronous Reset Recovery Block Clock Delay Macrocell Clock Delay Block Set/Reset Delay Macrocell Set/Reset Delay Global Delay Macrocell Delay 0.65 1.45 0.65 1.45 1.55 1.55 1.20 2.25 0.65 1.45 1.55 0.65 2.45 1.40 0.90 1.55 1.55 1.40 0.90 0.90 0.00 0.05 0.05 0.40 0.40 0.30 0.50 2.00 1.40 1.15 1.10 0.85 4.40 1.40 1.08 2.42 1.08 2.42 2.58 2.58 2.00 3.75 1.08 2.42 2.58 1.08 4.08 2.33 1.50 2.58 2.58 2.33 1.50 1.50 0.00 0.08 0.08 0.67 0.67 0.50 0.83 3.33 2.33 1.92 1.83 1.42 7.33 2.33 1.63 3.63 1.63 3.63 3.88 3.88 3.00 5.63 1.63 3.63 3.88 1.63 6.13 3.50 2.25 3.88 3.88 3.50 2.25 2.25 0.00 0.13 0.13 1.00 1.00 0.75 1.25 5.00 3.50 2.88 2.75 2.13 11.00 3.50 2.17 4.83 2.17 4.83 5.17 5.17 4.00 7.50 2.17 4.83 5.17 2.17 8.17 4.67 3.00 5.17 5.17 4.67 3.00 3.00 0.00 0.17 0.17 1.33 1.33 1.00 1.67 6.67 4.67 3.83 3.67 2.83 14.67 4.67 Description -101 Units
Routing/GLB Delays
Register/Latch Delays
Control Delays
Note: Internal Timing Parameters tested reference only. Refer Timing Model this data sheet further details. Only available industrial grade.
Timing v.2.6
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4512B/C Internal Timing Parameters (Preliminary)
Over Recommended Operating Conditions
Parameter In/Out Delays tGOE tGCLK_IN tBUF tDIS tROUTE tMCELL tINREG tFBK tPDb tPDi tS_PT tST_PT tCOi tCES tCEH tSL_PT tGOi tPDLi tSRi tSRR tBCLK tPTCLK tBSR tPTSR tGPTOE tPTOE Input Buffer Delay Global Delay Global Clock Input Buffer Delay Delay through Output Buffer Output Enable Time Output Disable Time Delay through Macrocell Delay Input Buffer Macrocell Register Delay Internal Feedback Delay 5-PT Bypass Propagation Delay Macrocell Propagation Delay Register Setup Time, Flip-Flop D-Register Setup Clock) Register Setup Time, Flip-Flop Register Setup Time, Flip-Flop Clock) Register Hold Time, Flip-Flop Register Hold Time, Flip-Flop Register Clock Time Clock Enable Setup Time Clock Enable Hold Time Latch Setup Time Latch Setup Time Clock) Latch Hold Time Latch Gate Time Propagation Delay through Transparent Latch Asynchronous Reset Delay Asynchronous Reset Recovery Block Clock Delay Macrocell Clock Delay Block Set/Reset Delay Macrocell Set/Reset Delay Global Delay Macrocell Delay 0.76 1.69 0.76 1.69 1.58 1.58 1.63 2.63 0.76 1.69 1.63 0.76 2.86 1.87 1.05 1.81 1.81 1.63 1.05 0.93 0.00 0.06 0.06 0.47 0.47 0.35 0.58 2.33 1.63 1.34 1.28 0.99 5.13 1.63 1.08 2.42 1.08 2.42 2.25 2.25 2.33 3.75 1.08 2.42 2.33 1.08 4.08 2.67 1.50 2.58 2.58 2.33 1.50 1.33 0.00 0.08 0.08 0.67 0.67 0.50 0.83 3.33 2.33 1.92 1.83 1.42 7.33 2.33 1.63 3.63 1.63 3.63 3.38 3.38 3.50 5.63 1.63 3.63 3.50 1.63 6.13 4.00 2.25 3.88 3.88 3.50 2.25 2.00 0.00 0.13 0.13 1.00 1.00 0.75 1.25 5.00 3.50 2.88 2.75 2.13 11.00 3.50 2.17 4.83 2.17 4.83 4.50 4.50 4.67 7.50 2.17 4.83 4.67 2.17 8.17 5.33 3.00 5.17 5.17 4.67 3.00 2.67 0.00 0.17 0.17 1.33 1.33 1.00 1.67 6.67 4.67 3.83 3.67 2.83 14.67 4.67 Description -101 Units
Routing/GLB Delays
Register/Latch Delays
Control Delays
Note: Internal Timing Parameters tested reference only. Refer Timing Model this data sheet further details. Only available industrial grade.
Timing v.0.1
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C Timing Adders (Preliminary)1
Adder Type tINDIO tEXP tORP tBLA tIOI Input Adjusters LVTTL_in LVCMOS33_in LVCMOS25_in LVCMOS18_in PCI_in tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE Using LVTTL standard Using LVCMOS standard Using LVCMOS standard Using LVCMOS standard Using compatible input 0.60 0.60 0.60 0.00 0.60 0.60 0.60 0.60 0.00 0.60 0.60 0.60 0.60 0.00 0.60 0.60 0.60 0.60 0.00 0.60 Base Parameter tINREG tMCELL tROUTE Description Input register delay Product term expander delay Output routing pool delay Additional block loading adder -102 Units 1.40 0.33 0.10 0.04 2.33 0.56 0.17 0.07 3.50 0.83 0.25 0.10 4.67 1.11 0.33 0.13
Optional Delay Adders
tIOO Output Adjusters LVTTL_out tBUF, tEN, tDIS Output configured buffer 0.20 0.20 0.10 0.00 0.20 1.00 0.20 0.20 0.10 0.00 0.20 1.00 0.20 0.20 0.10 0.00 0.20 1.00 0.20 0.20 0.10 0.00 0.20 1.00 LVCMOS33_out tBUF, tEN, tDIS Output configured 3.3V buffer LVCMOS25_out tBUF, tEN, tDIS Output configured 2.5V buffer LVCMOS18_out tBUF, tEN, tDIS Output configured 1.8V buffer PCI_out Slow Slew Output configured tBUF, tEN, tDIS compatible buffer tBUF, Output configured slow slew rate
Note: Open drain timing same corresponding LVCMOS timing. Timing v.2.6 Refer Technical Note TN1004: ispMACH 4000 Timing Model Design Usage Guidelines information regarding usage these adders. Only available industrial grade.
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4512B/C Timing Adders (Preliminary)1
Adder Type tINDIO tEXP tORP tBLA tIOI Input Adjusters LVTTL_in LVCMOS33_in LVCMOS25_in LVCMOS18_in PCI_in tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE tIN, tGCLK_IN, tGOE Using LVTTL standard Using LVCMOS standard Using LVCMOS standard Using LVCMOS standard Using compatible input 0.60 0.60 0.60 0.00 0.60 0.60 0.60 0.60 0.00 0.60 0.60 0.60 0.60 0.00 0.60 0.60 0.60 0.60 0.00 0.60 Base Parameter tINREG tMCELL tROUTE Description Input register delay Product term expander delay Output routing pool delay Additional block loading adder 1.75 0.39 0.12 0.05 -102 Units 2.50 0.56 0.17 0.07 3.75 0.83 0.25 0.10 5.00 1.11 0.33 0.13
Optional Delay Adders
tIOO Output Adjusters LVTTL_out tBUF, tEN, tDIS Output configured buffer 0.20 0.20 0.10 0.00 0.20 1.00 0.20 0.20 0.10 0.00 0.20 1.00 0.20 0.20 0.10 0.00 0.20 1.00 0.20 0.20 0.10 0.00 0.20 1.00 LVCMOS33_out tBUF, tEN, tDIS Output configured 3.3V buffer LVCMOS25_out tBUF, tEN, tDIS Output configured 2.5V buffer LVCMOS18_out tBUF, tEN, tDIS Output configured 1.8V buffer PCI_out Slow Slew tBUF, tEN, tDIS tBUF, Output configured compatible buffer Output configured slow slew rate
Note: Open drain timing same corresponding LVCMOS timing. Timing v.0.1 Refer Technical Note TN1004: ispMACH 4000 Timing Model Design Usage Guidelines information regarding usage these adders. Only available industrial grade.
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Boundary Scan Waveforms Timing Specifications
Symbol tBTCP tBTCH tBTCL tBTSU tBTH tBRF tBTCO tBTOZ tBTVO tBTCPSU tBTCPH tBTUCO tBTUOZ tBTUOV [BSCAN test] clock cycle [BSCAN test] pulse width high [BSCAN test] pulse width [BSCAN test] setup time [BSCAN test] hold time [BSCAN test] rise fall time controller falling edge clock valid output controller falling edge clock data output disable controller falling edge clock data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge clock valid output BSCAN test Update reg, falling edge clock output disable BSCAN test Update reg, falling edge clock output enable Parameter Min. Max. Units mV/ns
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Power Consumption
ispMACH 4000C Typical Frequency
(mA) ispMACH 4256C ispMACH 4512C (mA) ispMACH 4256B ispMACH 4512B
ispMACH 4000B Typical Frequency
Frequency (MHz)
Note: devices configured with maximum number 16-bit counters, typical current 1.8V,
Frequency (MHz)
Note: devices configured with maximum number 16-bit counters, typical current 2.5V,
Power Estimation Coefficients
Device ispMACH 4032B ispMACH 4032C ispMACH 4064B ispMACH 4064C ispMACH 4128B ispMACH 4128C ispMACH 4256B ispMACH 4256C ispMACH 4384B ispMACH 4384C ispMACH 4512B ispMACH 4512C 0.0115 0.0115 0.0115 0.0115
Note: further information about these coefficients, refer Technical Note TN1005, Power Estimation ispMACH 4000B/C Devices.
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Switching Test Conditions
Figure shows output test load that used testing. specific values resistance, capacitance, voltage, other test conditions shown Table Figure Output Test Load, LVTTL LVCMOS Standards VCCO Test Point
0213A/ispm4k
Table Test Fixture Required Components
Test Condition LVCMOS I/O, LVCMOS LVCMOS LVCMOS LVCMOS
includes test fixtures probe capacitance.
35pF 35pF 35pF
Timing Ref. LVCMOS 1.5V LVCMOS VCCO/2 LVCMOS VCCO/2 1.5V 1.5V
VCCO LVCMOS 3.0V LVCMOS 2.3V LVCMOS 1.65V 3.0V 3.0V 3.0V 3.0V
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Signal Descriptions
Signal Names GOE0, GOE1 CLK0/I, CLK1/I, CLK2/I, CLK3/I VCCO0, VCCO1 Description Input This IEEE 1149.1 Test Mode Select input, which used control state machine Input This IEEE 1149.1 Test Clock input pin, used clock through state machine Input This IEEE 1149.1 Test Data pin, used load data Output This IEEE 1149.1 Test Data used shift data Input These pins Global Output Enable Input pins Ground Connected power supply pins logic core These pins configured either input input power supply pins each bank Input/Output1 These general purpose used logic array. reference (alpha) macrocell reference (numeric). 0-15 ispMACH 4032 ispMACH 4064 ispMACH 4128 ispMACH 4256 ispMACH 4384 ispMACH 4512
some packages, certain only available inputs. signal connections table details.
A-AH
ispMACH 4256B/C 4512B/C Power Supply Connections1
Signal VCCO0 VCCO1 (Bank0) (Bank1) TQFP TQFP 130, 157, 110, 128, 134, 155, 101, 119, 131, 132, fpBGA2, B15, D11, F13, H10, J10, L13, A16, C11, F14, G10, K10, L14, P11, A11, A12, A13, A15, B11, B12, B14, D10, D12, D16, E10, E13, E14, E15, E16, F15, F16, G12, G13, G14, J11, K15, L12, L15, L16, M12, M13, M15, M16, N10, N12, N14, P12, R11, R12, R16, T11, T12, T13,
grounds must electrically connected board level. However, purposes current loading, grounds associated with bank shown. Internal GNDs GNDs (Bank 0/1) connected inside package. VCCO balls connect power planes within package, VCCO0 VCCO1. connect (NC) balls listed ispMACH 4256B/C devices only. There signals ispMACH 4512B/C devices.
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C Logic Signal Connections: TQFP
Bank (Bank (Bank (Bank ispMACH 4256B/C
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C Logic Signal Connections: TQFP (Cont.)
Bank (Bank (Bank CLK1/I CLK2/I (Bank (Bank ispMACH 4256B/C
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C Logic Signal Connections: TQFP (Cont.)
Bank (Bank (Bank (Bank (Bank (Bank (Bank ispMACH 4256B/C
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C Logic Signal Connections: TQFP (Cont.)
Bank
*This input only this package.
P2/GOE1 CLK3/I CLK0/I A2/GOE0 (Bank (Bank
ispMACH 4256B/C
ispMACH 4256B/C, 4512B/C Logic Signal Connections: TQFP
ispMACH 4256B/C Number Bank Number VCCO (Bank ispMACH 4512B/C VCCO (Bank
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C, 4512B/C Logic Signal Connections: TQFP (Cont.)
ispMACH 4256B/C Number Bank Number (Bank VCCO (Bank (Bank VCCO (Bank (Bank ispMACH 4512B/C (Bank VCCO (Bank (Bank VCCO (Bank (Bank
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C, 4512B/C Logic Signal Connections: TQFP (Cont.)
ispMACH 4256B/C Number Bank Number (Bank VCCO (Bank CLK1/I (Bank CLK2/I VCCO (Bank (Bank (Bank VCCO (Bank ispMACH 4512B/C (Bank VCCO (Bank CLK1/I (Bank CLK2/I AX10 AX12 AX14 VCCO (Bank (Bank BX10 BX12 BX14 (Bank VCCO (Bank CX14 CX12 CX10 AX^0 AX^1 AX^2 AX^3 AX^4 AX^5 AX^6 AX^7 BX^0 BX^1 BX^2 BX^3 BX^4 BX^5 BX^6 BX^7 CX^7 CX^6 CX^5 CX^4 CX^3
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C, 4512B/C Logic Signal Connections: TQFP (Cont.)
ispMACH 4256B/C Number Bank Number (Bank VCCO (Bank (Bank VCCO (Bank (Bank ispMACH 4512B/C (Bank GX14 GX12 GX10 VCCO (Bank JX10 JX12 JX14 (Bank NX10 NX12 NX14 VCCO (Bank (Bank OX14 OX12 OX10 CX^2 CX^1 CX^0 GX^7 GX^6 GX^5 GX^4 GX^3 GX^2 GX^1 GX^0 JX^0 JX^1 JX^2 JX^3 JX^4 JX^5 JX^6 JX^7 NX^0 NX^1 NX^2 NX^3 NX^4 NX^5 NX^6 NX^7 OX^7 OX^6 OX^5 OX^4 OX^3 OX^2
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C, 4512B/C Logic Signal Connections: TQFP (Cont.)
ispMACH 4256B/C Number Bank Number (Bank VCCO (Bank P2/GOE1 CLK3/I (Bank CLK0/I A2/GOE0 VCCO (Bank (Bank ispMACH 4512B/C (Bank VCCO (Bank PX14 PX12 PX10 PX2/GOE1 CLK3/I (Bank CLK0/I A2//GOE0 VCCO (Bank (Bank OX^1 OX^0 PX^7 PX^6 PX^5 PX^4 PX^3 PX^2 PX^1 PX^0
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C, 4512B/C Logic Signal Connections: fpBGA
Ball Number VCCO (Bank VCCO (Bank VCCO (Bank ispMACH 4256B/C Bank Number ispMACH 4512B/C
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C, 4512B/C Logic Signal Connections: fpBGA (Cont.)
Ball Number VCCO (Bank VCCO (Bank VCCO (Bank ispMACH 4256B/C Bank Number ispMACH 4512B/C
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C, 4512B/C Logic Signal Connections: fpBGA (Cont.)
Ball Number VCCO (Bank ispMACH 4256B/C Bank Number CLK1/I CLK2/I ispMACH 4512B/C CLK1/I CLK2/I AX10 AX12 AX14 EX12 DX12 BX10 BX12 BX14 AX^0 AX^1 AX^2 AX^3 AX^4 AX^5 AX^6 AX^7 DX^0 DX^2 EX^0 EX^2 EX^4 EX^6 DX^4 DX^6 BX^0 BX^1 BX^2 BX^3 BX^4 BX^5 BX^6 BX^7 FX^0 FX^1
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C, 4512B/C Logic Signal Connections: fpBGA (Cont.)
Ball Number VCCO (Bank VCCO (Bank VCCO (Bank ispMACH 4256B/C Bank Number CX14 CX12 CX10 FX10 FX12 FX14 HX12 GX14 GX12 GX10 JX10 JX12 JX14 ispMACH 4512B/C FX^2 FX^3 FX^4 CX^7 CX^6 CX^5 CX^4 CX^3 CX^2 CX^1 CX^0 HX^0 HX^2 FX^5 FX^6 FX^7 HX^4 HX^6 GX^7 GX^6 GX^5 GX^4 GX^3 GX^2 GX^1 GX^0 JX^0 JX^1 JX^2 JX^3 JX^4 JX^5 JX^6 JX^7 IX^0 IX^2
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C, 4512B/C Logic Signal Connections: fpBGA (Cont.)
Ball Number VCCO (Bank VCCO (Bank VCCO (Bank ispMACH 4256B/C Bank Number ispMACH 4512B/C KX10 IX12 NX10 NX12 NX14 KX12 KX14 OX14 OX12 OX10 LX12 MX12 KX^0 KX^1 KX^2 KX^3 KX^4 KX^5 IX^4 IX^6 NX^0 NX^1 NX^2 NX^3 NX^4 NX^5 NX^6 NX^7 KX^6 KX^7 OX^7 OX^6 OX^5 OX^4 OX^3 OX^2 OX^1 OX^0 MX^0 MX^2 LX^0 LX^2 LX^4 LX^6 MX^4 MX^6
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
ispMACH 4256B/C, 4512B/C Logic Signal Connections: fpBGA (Cont.)
Ball Number VCCO (Bank ispMACH 4256B/C Bank Number P2/GOE1 CLK3/I CLK0/I A2/GOE0 ispMACH 4512B/C PX14 PX12 PX10 PX2/GOE1 CLK3/I CLK0/I A2/GOE0 PX^7 PX^6 PX^5 PX^4 PX^3 PX^2 PX^1 PX^0
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Part Number Description
XXXX
Device Family Device Number 4032 Macrocells 4064 Macrocells 4128 Macrocells 4256 Macrocells 4384 Macrocells 4512 Macrocells Supply Voltage 2.5V 1.8V Speed 3.0ns 3.5ns 4.0ns 5.0ns 7.5ns 10.0ns Production Status Blank Final production Engineering Samples Grade Commercial Industrial Designator I/Os Pin/Ball Count Package TQFP fpBGA
0212/ispm4K
Ordering Information
Commercial
Part Number LC4256B-3T100C LC4256B-5T100C LC4256B-75T100C LC4256B-3T176C LC4256B-5T176C LC4256B-75T176C LC4256B-3F256AC LC4256B-5F256AC LC4256B-75F256AC LC4256C-3T100C LC4256C-5T100C LC4256C-75T100C LC4256C-3T176C LC4256C-5T176C LC4256C-75T176C LC4256C-3F256AC LC4256C-5F256AC LC4256C-75F256AC Macrocells Voltage Package TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA Pin/Ball Count Grade
Lattice Semiconductor
ispMACH 4000B/C Family Data Sheet
Commercial (Cont.)
Part Number LC4512B-35T176C LC4512B-5T176C LC4512B-75T176C LC4512B-35F256C LC4512B-5F256C LC4512B-75F256C LC4512C-35T176C LC4512C-5T176C LC4512C-75T176C LC4512C-35F256C LC4512C-5F256C LC4512C-75F256C
Macrocells
Voltage
Package TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP fpBGA fpBGA fpBGA
Pin/Ball Count
Grade
Note: speed grades these devices dual marked. example, commercial grade -3xxxxC also marked with industrial grade -5xxxxI. commercial grade always speed grade faster than associated dual mark industrial grade.
Industrial
Part Number LC4256B-5T100I LC4256B-75T100I LC4256B-10T100I LC4256B-5T176I LC4256B-75T176I LC4256B-10T176I LC4256B-5F256AI LC4256B-75F256AI LC4256B-10F256AI LC4256C-5T100I LC4256C-75T100I LC4256C-10T100I LC4256C-5T176I LC4256C-75T176I LC4256C-10T176I LC4256C-5F256AI LC4256C-75F256AI LC4256C-10F256AI Macrocells Voltage 10.0 10.0 10.0 10.0 10.0 10.0 Package TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP TQFP TQFP TQFP fpBGA fpBGA fpBGA Pin/Ball Count Grade
Lattice Semiconductor
Industrial (Cont.)
Part Number LC4512B-5T176I LC4512B-75T176I LC4512B-10T176I LC4512B-5F256I LC4512B-75F256I LC4512B-10F256I LC4512C-5T176I LC4512C-75T176I LC4512C-10T176I LC4512C-5F256I LC4512C-75F256I LC4512C-10F256I Macrocells Voltage 10.0 10.0 10.0 10.0
ispMACH 4000B/C Family Data Sheet
Package TQFP TQFP TQFP fpBGA fpBGA fpBGA TQFP TQFP TQFP fpBGA fpBGA fpBGA
Pin/Ball Count
Grade
Note: speed grades these devices dual marked. example, commercial grade -3xxxxC also marked with industrial grade -5xxxxI. commercial grade always speed grade faster than associated dual mark industrial grade.
Further Information
addition this data sheet, following technical notes helpful when designing with ispMACH 4000B/C family: ispMACH 4000 Timing Model Design Usage Guidelines (TN1004) ispMACH 4000B/C Power Consumption (TN1005)

2.5V/1.8V In-System Programmable SuperFAST High Density PLDs Dece

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